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Minor SPARC T4 and M7 fixes and additions.

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* config/sparc/sparc.c (sparc_option_override): Set function
	alignment for -mcpu=niagara7 to 64 to match the I$ line.
	* config/sparc/sparc.h (BRANCH_COST): Set the SPARC M7 branch
	latency to 1.
	* config/sparc/sparc.h (BRANCH_COST): Set the SPARC T4 branch
	latency to 2.
	* config/sparc/sol2.h: Fix a ASM_CPU32_DEFAULT_SPEC typo.
	* gcc.target/sparc/niagara7-align.c: New test.

From-SVN: r248184
This commit is contained in:
Sheldon Lobo 2017-05-18 09:34:26 +00:00 committed by Sheldon Lobo
parent 243c288370
commit 00a84d0edd
6 changed files with 36 additions and 8 deletions
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10
gcc/ChangeLog
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@ -1,3 +1,13 @@
2017-05-18 Sheldon Lobo <sheldon.lobo@oracle.com>
* config/sparc/sparc.c (sparc_option_override): Set function
alignment for -mcpu=niagara7 to 64 to match the I$ line.
* config/sparc/sparc.h (BRANCH_COST): Set the SPARC M7 branch
latency to 1.
* config/sparc/sparc.h (BRANCH_COST): Set the SPARC T4 branch
latency to 2.
* config/sparc/sol2.h: Fix a ASM_CPU32_DEFAULT_SPEC typo.
2017-05-18 Marek Polacek <polacek@redhat.com>
PR sanitizer/80797

2
gcc/config/sparc/sol2.h
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@ -169,7 +169,7 @@ along with GCC; see the file COPYING3. If not see
#undef CPP_CPU64_DEFAULT_SPEC
#define CPP_CPU64_DEFAULT_SPEC ""
#undef ASM_CPU32_DEFAULT_SPEC
#define ASM_CPU32_DEFAUILT_SPEC AS_SPARC32_FLAG AS_NIAGARA7_FLAG
#define ASM_CPU32_DEFAULT_SPEC AS_SPARC32_FLAG AS_NIAGARA7_FLAG
#undef ASM_CPU64_DEFAULT_SPEC
#define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG AS_NIAGARA7_FLAG
#endif

13
gcc/config/sparc/sparc.c
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@ -1528,15 +1528,18 @@ sparc_option_override (void)
target_flags |= MASK_LRA;
/* Supply a default value for align_functions. */
if (align_functions == 0
&& (sparc_cpu == PROCESSOR_ULTRASPARC
if (align_functions == 0)
{
if (sparc_cpu == PROCESSOR_ULTRASPARC
|| sparc_cpu == PROCESSOR_ULTRASPARC3
|| sparc_cpu == PROCESSOR_NIAGARA
|| sparc_cpu == PROCESSOR_NIAGARA2
|| sparc_cpu == PROCESSOR_NIAGARA3
|| sparc_cpu == PROCESSOR_NIAGARA4
|| sparc_cpu == PROCESSOR_NIAGARA7))
align_functions = 32;
|| sparc_cpu == PROCESSOR_NIAGARA4)
align_functions = 32;
else if (sparc_cpu == PROCESSOR_NIAGARA7)
align_functions = 64;
}
/* Validate PCC_STRUCT_RETURN. */
if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)

11
gcc/config/sparc/sparc.h
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@ -1566,7 +1566,10 @@ do { \
and annulled branches insert 4 bubbles.
On Niagara-2 and Niagara-3, a not-taken branch costs 1 cycle whereas
a taken branch costs 6 cycles. */
a taken branch costs 6 cycles.
The T4 Supplement specifies the branch latency at 2 cycles.
The M7 Supplement specifies the branch latency at 1 cycle. */
#define BRANCH_COST(speed_p, predictable_p) \
((sparc_cpu == PROCESSOR_V9 \
@ -1579,7 +1582,11 @@ do { \
: ((sparc_cpu == PROCESSOR_NIAGARA2 \
|| sparc_cpu == PROCESSOR_NIAGARA3) \
? 5 \
: 3))))
: (sparc_cpu == PROCESSOR_NIAGARA4 \
? 2 \
: (sparc_cpu == PROCESSOR_NIAGARA7 \
? 1 \
: 3))))))
/* Control the assembler format that we output. */

4
gcc/testsuite/ChangeLog
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@ -1,3 +1,7 @@
2017-05-18 Sheldon Lobo <sheldon.lobo@oracle.com>
* gcc.target/sparc/niagara7-align.c: New test.
2017-05-18 Marek Polacek <polacek@redhat.com>
PR sanitizer/80797

4
gcc/testsuite/gcc.target/sparc/niagara7-align.c Normal file
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@ -0,0 +1,4 @@
/* { dg-do compile } */
/* { dg-options "-falign-functions -mcpu=niagara7" } */
/* { dg-final { scan-assembler "\.align 64" } } */
void foo(void) {}