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c4x.c (c4x_fp_reglist): Const-ify. 

* c4x.c (c4x_fp_reglist): Const-ify.
	* cris.c (cris_print_operand): Likewise.
	* i386.c (ix86_va_arg): Likewise.
	* ia64/unwind-ia64.c (unw_decode_table): Likewise.
	* m32r.c (m32r_hard_regno_mode_ok): Likewise.
	* m32r.h (m32r_hard_regno_mode_ok): Likewise.
	* mcore.c (regno_reg_class, mcore_unique_section): Likewise.
	* mcore.h (regno_reg_class): Likewise.
	* mips.c (gen_int_relational): Likewise.
	* ns32k.c (ns32k_reg_class_contents, regclass_map): Likewise.
	* ns32k.h (ns32k_reg_class_contents, regclass_map): Likewise.
	* pdp11.c (pdp11_assemble_integer): Likewise.
	* pj.h (INITIALIZE_TRAMPOLINE): Likewise.
	* s390.c (s390_branch_condition_mnemonic, regclass_map):
	Likewise.
	* s390.h (regclass_map): Likewise.
	* sh.c (shift_amounts): Likewise.
	* sh.md (rot_tab): Likewise.

From-SVN: r50517
This commit is contained in:
Kaveh R. Ghazi 2002-03-10 01:39:04 +00:00 committed by Kaveh Ghazi
parent 1c0d0c3e56
commit 0139adcaa7
18 changed files with 43 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
gcc/ChangeLog
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@ -1,3 +1,24 @@
2002-03-09 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
* c4x.c (c4x_fp_reglist): Const-ify.
* cris.c (cris_print_operand): Likewise.
* i386.c (ix86_va_arg): Likewise.
* ia64/unwind-ia64.c (unw_decode_table): Likewise.
* m32r.c (m32r_hard_regno_mode_ok): Likewise.
* m32r.h (m32r_hard_regno_mode_ok): Likewise.
* mcore.c (regno_reg_class, mcore_unique_section): Likewise.
* mcore.h (regno_reg_class): Likewise.
* mips.c (gen_int_relational): Likewise.
* ns32k.c (ns32k_reg_class_contents, regclass_map): Likewise.
* ns32k.h (ns32k_reg_class_contents, regclass_map): Likewise.
* pdp11.c (pdp11_assemble_integer): Likewise.
* pj.h (INITIALIZE_TRAMPOLINE): Likewise.
* s390.c (s390_branch_condition_mnemonic, regclass_map):
Likewise.
* s390.h (regclass_map): Likewise.
* sh.c (shift_amounts): Likewise.
* sh.md (rot_tab): Likewise.
2002-03-09 Geoffrey Keating <geoffk@redhat.com>
* config/rs6000/rs6000.md (ne0+4): Add extra CLOBBER.

2
gcc/config/c4x/c4x.c
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@ -514,7 +514,7 @@ static const int c4x_int_reglist[3][6] =
{AR2_REGNO, RC_REGNO, RS_REGNO, RE_REGNO, 0, 0}
};
static int c4x_fp_reglist[2] = {R2_REGNO, R3_REGNO};
static const int c4x_fp_reglist[2] = {R2_REGNO, R3_REGNO};
/* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a

2
gcc/config/cris/cris.c
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@ -1264,7 +1264,7 @@ cris_print_operand (file, x, code)
rtx operand = x;
/* Size-strings corresponding to MULT expressions. */
static const char *mults[] = { "BAD:0", ".b", ".w", "BAD:3", ".d" };
static const char *const mults[] = { "BAD:0", ".b", ".w", "BAD:3", ".d" };
/* New code entries should just be added to the switch below. If
handling is finished, just return. If handling was just a

2
gcc/config/i386/i386.c
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@ -2509,7 +2509,7 @@ rtx
ix86_va_arg (valist, type)
tree valist, type;
{
static int intreg[6] = { 0, 1, 2, 3, 4, 5 };
static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
tree f_gpr, f_fpr, f_ovf, f_sav;
tree gpr, fpr, ovf, sav, t;
int size, rsize;

2
gcc/config/ia64/unwind-ia64.c
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@ -1212,7 +1212,7 @@ unw_decode_b3_x4 (unsigned char *dp, unsigned char code, void *arg)
typedef unsigned char *(*unw_decoder) (unsigned char *, unsigned char, void *);
static unw_decoder unw_decode_table[2][8] =
static const unw_decoder unw_decode_table[2][8] =
{
/* prologue table: */
{

2
gcc/config/m32r/m32r.c
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@ -172,7 +172,7 @@ enum m32r_mode_class
/* Value is 1 if register/mode pair is acceptable on arc. */
unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] =
const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] =
{
T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, S_MODES, S_MODES, S_MODES,

2
gcc/config/m32r/m32r.h
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@ -638,7 +638,7 @@ extern enum m32r_sdata m32r_sdata;
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
extern unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER];
extern const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER];
extern unsigned int m32r_mode_class[];
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
((m32r_hard_regno_mode_ok[REGNO] & m32r_mode_class[MODE]) != 0)

4
gcc/config/mcore/mcore.c
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@ -62,7 +62,7 @@ rtx arch_compare_op1;
/* Provides the class number of the smallest class containing
reg number. */
int regno_reg_class[FIRST_PSEUDO_REGISTER] =
const int regno_reg_class[FIRST_PSEUDO_REGISTER] =
{
GENERAL_REGS, ONLYR1_REGS, LRW_REGS, LRW_REGS,
LRW_REGS, LRW_REGS, LRW_REGS, LRW_REGS,
@ -3519,7 +3519,7 @@ mcore_unique_section (decl, reloc)
int reloc ATTRIBUTE_UNUSED;
{
int len;
char * name;
const char * name;
char * string;
const char * prefix;

2
gcc/config/mcore/mcore.h
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@ -518,7 +518,7 @@ enum reg_class
reg number REGNO. This could be a conditional expression
or could index an array. */
extern int regno_reg_class[FIRST_PSEUDO_REGISTER];
extern const int regno_reg_class[FIRST_PSEUDO_REGISTER];
#define REGNO_REG_CLASS(REGNO) regno_reg_class[REGNO]
/* When defined, the compiler allows registers explicitly used in the

4
gcc/config/mips/mips.c
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@ -2884,7 +2884,7 @@ gen_int_relational (test_code, result, cmp0, cmp1, p_invert)
int unsignedp; /* != 0 for unsigned comparisons. */
};
static struct cmp_info info[ (int)ITEST_MAX ] = {
static const struct cmp_info info[ (int)ITEST_MAX ] = {
{ XOR, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
{ XOR, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
@ -2900,7 +2900,7 @@ gen_int_relational (test_code, result, cmp0, cmp1, p_invert)
enum internal_test test;
enum machine_mode mode;
struct cmp_info *p_info;
const struct cmp_info *p_info;
int branch_p;
int eqne_p;
int invert;

4
gcc/config/ns32k/ns32k.c
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@ -47,9 +47,9 @@ int ns32k_num_files = 0;
initialized in time. Also this is more convenient as an array of ints.
We know that HARD_REG_SET fits in an unsigned int */
unsigned int ns32k_reg_class_contents[N_REG_CLASSES][1] = REG_CLASS_CONTENTS;
const unsigned int ns32k_reg_class_contents[N_REG_CLASSES][1] = REG_CLASS_CONTENTS;
enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
{
GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,

4
gcc/config/ns32k/ns32k.h
View File

@ -1388,8 +1388,8 @@ do { \
#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address(FILE, ADDR)
extern unsigned int ns32k_reg_class_contents[N_REG_CLASSES][1];
extern enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; /* smallest class containing REGNO */
extern const unsigned int ns32k_reg_class_contents[N_REG_CLASSES][1];
extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; /* smallest class containing REGNO */
/*
Local variables:

2
gcc/config/pdp11/pdp11.c
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@ -984,7 +984,7 @@ pdp11_assemble_integer (x, size, aligned_p)
/* register move costs, indexed by regs */
static int move_costs[N_REG_CLASSES][N_REG_CLASSES] =
static const int move_costs[N_REG_CLASSES][N_REG_CLASSES] =
{
/* NO MUL GEN LFPU NLFPU FPU ALL */

2
gcc/config/pj/pj.h
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@ -734,7 +734,7 @@ struct pj_args
#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
{ \
static int off[4] = { 1, 0, 4, 3 }; \
static const int off[4] = { 1, 0, 4, 3 }; \
int i; \
\
/* Move the FNADDR and CXT into the instruction stream. Do this byte \

4
gcc/config/s390/s390.c
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@ -344,7 +344,7 @@ s390_branch_condition_mnemonic (code, inv)
rtx code;
int inv;
{
static const char *mnemonic[16] =
static const char *const mnemonic[16] =
{
NULL, "o", "h", "nle",
"l", "nhe", "lh", "ne",
@ -600,7 +600,7 @@ override_options ()
/* Map for smallest class containing reg regno. */
enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
{ GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,

2
gcc/config/s390/s390.h
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@ -518,7 +518,7 @@ enum reg_class
#define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
extern enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; /* smalled class containing REGNO */
extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; /* smalled class containing REGNO */
/* The class value for index registers, and the one for base regs. */

2
gcc/config/sh/sh.c
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@ -1136,7 +1136,7 @@ static const char shift_insns[] =
One bit right shifts clobber the T bit, so when possible, put one bit
shifts in the middle of the sequence, so the ends are eligible for
branch delay slots. */
static short shift_amounts[32][5] = {
static const short shift_amounts[32][5] = {
{0}, {1}, {2}, {2, 1},
{2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
{8}, {8, 1}, {8, 2}, {8, 1, 2},

2
gcc/config/sh/sh.md
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@ -2013,7 +2013,7 @@
"TARGET_SH1"
"
{
static char rot_tab[] = {
static const char rot_tab[] = {
000, 000, 000, 000, 000, 000, 010, 001,
001, 001, 011, 013, 003, 003, 003, 003,
003, 003, 003, 003, 003, 013, 012, 002,