expr.c (emit_group_load): Revise to allow splitting TCmode source into DImode pieces.
* expr.c (emit_group_load): Revise to allow splitting TCmode source into DImode pieces. * pa-64.h (LONG_DOUBLE_TYPE_SIZE): Define to 128. * pa64-regs.h (CLASS_CANNOT_CHANGE_MODE_P): Inhibit changes from SImode for floating-point register class. * pa.c (function_arg): Fix handling of modes wider than one word for TARGET_64BIT. From-SVN: r56805
This commit is contained in:
John David Anglin
John David Anglin
parent
b10f218708
commit
015b1ad1df
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@ -1,3 +1,14 @@
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2002-09-04 John David Anglin <dave@hiauly1.hia.nrc.ca>
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* expr.c (emit_group_load): Revise to allow splitting TCmode source
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into DImode pieces.
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* pa-64.h (LONG_DOUBLE_TYPE_SIZE): Define to 128.
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* pa64-regs.h (CLASS_CANNOT_CHANGE_MODE_P): Inhibit changes from SImode
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for floating-point register class.
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* pa.c (function_arg): Fix handling of modes wider than one word for
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TARGET_64BIT.
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Wed Sep 4 18:48:10 2002 J"orn Rennecke <joern.rennecke@superh.com>
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* combine.c (make_compound_operation): Don't generate zero / sign
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@ -65,10 +65,8 @@ Boston, MA 02111-1307, USA. */
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#define FLOAT_TYPE_SIZE 32
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#undef DOUBLE_TYPE_SIZE
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#define DOUBLE_TYPE_SIZE 64
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/* This should be 128, but until we work out the ABI for the 128bit
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FP codes supplied by HP we'll keep it at 64 bits. */
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#undef LONG_DOUBLE_TYPE_SIZE
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#define LONG_DOUBLE_TYPE_SIZE 64
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#define LONG_DOUBLE_TYPE_SIZE 128
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/* Temporary until we figure out what to do with those *(&@$ 32bit
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relocs which appear in stabs. */
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@ -7446,6 +7446,8 @@ function_arg (cum, mode, type, named, incoming)
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int incoming;
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{
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int max_arg_words = (TARGET_64BIT ? 8 : 4);
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int arg_size = FUNCTION_ARG_SIZE (mode, type);
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int alignment = 0;
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int fpr_reg_base;
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int gpr_reg_base;
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rtx retval;
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@ -7456,16 +7458,15 @@ function_arg (cum, mode, type, named, incoming)
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this routine should return zero. FUNCTION_ARG_PARTIAL_NREGS will
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handle arguments which are split between regs and stack slots if
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the ABI mandates split arguments. */
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if (cum->words + FUNCTION_ARG_SIZE (mode, type) > max_arg_words
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if (cum->words + arg_size > max_arg_words
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|| mode == VOIDmode)
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return NULL_RTX;
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}
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else
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{
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int offset = 0;
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if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
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offset = 1;
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if (cum->words + offset >= max_arg_words
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if (arg_size > 1)
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alignment = cum->words & 1;
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if (cum->words + alignment >= max_arg_words
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|| mode == VOIDmode)
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return NULL_RTX;
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}
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@ -7474,70 +7475,54 @@ function_arg (cum, mode, type, named, incoming)
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particularly in their handling of FP registers. We might
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be able to cleverly share code between them, but I'm not
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going to bother in the hope that splitting them up results
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in code that is more easily understood.
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in code that is more easily understood. */
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The 64bit code probably is very wrong for structure passing. */
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if (TARGET_64BIT)
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{
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/* Advance the base registers to their current locations.
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Remember, gprs grow towards smaller register numbers while
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fprs grow to higher register numbers. Also remember FP regs
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are always 4 bytes wide, while the size of an integer register
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varies based on the size of the target word. */
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fprs grow to higher register numbers. Also remember that
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although FP regs are 32-bit addressable, we pretend that
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the registers are 64-bits wide. */
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gpr_reg_base = 26 - cum->words;
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fpr_reg_base = 32 + cum->words;
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/* If the argument is more than a word long, then we need to align
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the base registers. Same caveats as above. */
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if (FUNCTION_ARG_SIZE (mode, type) > 1)
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/* Arguments wider than one word need special treatment. */
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if (arg_size > 1)
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{
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if (mode != BLKmode)
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{
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/* First deal with alignment of the doubleword. */
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gpr_reg_base -= (cum->words & 1);
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/* Double-extended precision (80-bit), quad-precision (128-bit)
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and aggregates including complex numbers are aligned on
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128-bit boundaries. The first eight 64-bit argument slots
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are associated one-to-one, with general registers r26
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through r19, and also with floating-point registers fr4
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through fr11. Arguments larger than one word are always
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passed in general registers. */
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/* This seems backwards, but it is what HP specifies. We need
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gpr_reg_base to point to the smaller numbered register of
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the integer register pair. So if we have an even register
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number, then decrement the gpr base. */
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gpr_reg_base -= ((gpr_reg_base % 2) == 0);
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rtx loc[8];
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int i, offset = 0, ub = arg_size;
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/* FP values behave sanely, except that each FP reg is only
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half of word. */
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fpr_reg_base += ((fpr_reg_base % 2) == 0);
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}
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else
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/* Align the base register. */
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gpr_reg_base -= alignment;
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ub = MIN (ub, max_arg_words - cum->words - alignment);
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for (i = 0; i < ub; i++)
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{
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rtx loc[8];
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int i, offset = 0, ub;
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ub = FUNCTION_ARG_SIZE (mode, type);
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ub = MIN (ub,
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MAX (0, max_arg_words - cum->words - (cum->words & 1)));
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gpr_reg_base -= (cum->words & 1);
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for (i = 0; i < ub; i++)
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{
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loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
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gen_rtx_REG (DImode,
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gpr_reg_base),
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GEN_INT (offset));
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gpr_reg_base -= 1;
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offset += 8;
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}
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if (ub == 0)
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return NULL_RTX;
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else if (ub == 1)
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return XEXP (loc[0], 0);
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else
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return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
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loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
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gen_rtx_REG (DImode, gpr_reg_base),
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GEN_INT (offset));
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gpr_reg_base -= 1;
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offset += 8;
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}
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return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
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}
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}
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else
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{
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/* If the argument is larger than a word, then we know precisely
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which registers we must use. */
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if (FUNCTION_ARG_SIZE (mode, type) > 1)
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if (arg_size > 1)
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{
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if (cum->words)
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{
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@ -7559,19 +7544,6 @@ function_arg (cum, mode, type, named, incoming)
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}
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}
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if (TARGET_64BIT && mode == TFmode)
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{
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return
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gen_rtx_PARALLEL
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(mode,
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gen_rtvec (2,
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gen_rtx_EXPR_LIST (VOIDmode,
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gen_rtx_REG (DImode, gpr_reg_base + 1),
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const0_rtx),
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gen_rtx_EXPR_LIST (VOIDmode,
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gen_rtx_REG (DImode, gpr_reg_base),
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GEN_INT (8))));
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}
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/* Determine if the argument needs to be passed in both general and
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floating point registers. */
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if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
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@ -234,16 +234,21 @@ enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS,
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/* If defined, gives a class of registers that cannot be used as the
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operand of a SUBREG that changes the mode of the object illegally. */
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/* ??? This may not actually be necessary anymore. But until I can prove
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otherwise it will stay. */
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#define CLASS_CANNOT_CHANGE_MODE (FP_REGS)
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/* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
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#define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
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(GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
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/* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE.
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/* The same information, inverted:
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Return the class number of the smallest class containing
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SImode loads to floating-point registers are not zero-extended.
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The definition for LOAD_EXTEND_OP specifies that integer loads
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narrower than BITS_PER_WORD will be zero-extended. As a result,
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we inhibit changes from SImode unless they are to a mode that is
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identical in size. */
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#define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
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((FROM) == SImode && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
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/* Return the class number of the smallest class containing
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reg number REGNO. This could be a conditional expression
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or could index an array. */
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21
gcc/expr.c
21
gcc/expr.c
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@ -2265,21 +2265,26 @@ emit_group_load (dst, orig_src, ssize)
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}
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else if (GET_CODE (src) == CONCAT)
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{
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if ((bytepos == 0
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&& bytelen == GET_MODE_SIZE (GET_MODE (XEXP (src, 0))))
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|| (bytepos == (HOST_WIDE_INT) GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
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&& bytelen == GET_MODE_SIZE (GET_MODE (XEXP (src, 1)))))
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unsigned int slen = GET_MODE_SIZE (GET_MODE (src));
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unsigned int slen0 = GET_MODE_SIZE (GET_MODE (XEXP (src, 0)));
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if ((bytepos == 0 && bytelen == slen0)
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|| (bytepos != 0 && bytepos + bytelen <= slen))
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{
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tmps[i] = XEXP (src, bytepos != 0);
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/* The following assumes that the concatenated objects all
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have the same size. In this case, a simple calculation
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can be used to determine the object and the bit field
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to be extracted. */
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tmps[i] = XEXP (src, bytepos / slen0);
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if (! CONSTANT_P (tmps[i])
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&& (GET_CODE (tmps[i]) != REG || GET_MODE (tmps[i]) != mode))
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tmps[i] = extract_bit_field (tmps[i], bytelen * BITS_PER_UNIT,
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0, 1, NULL_RTX, mode, mode, ssize);
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(bytepos % slen0) * BITS_PER_UNIT,
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1, NULL_RTX, mode, mode, ssize);
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}
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else if (bytepos == 0)
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{
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rtx mem = assign_stack_temp (GET_MODE (src),
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GET_MODE_SIZE (GET_MODE (src)), 0);
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rtx mem = assign_stack_temp (GET_MODE (src), slen, 0);
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emit_move_insn (mem, src);
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tmps[i] = adjust_address (mem, mode, 0);
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}
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