i860.h (EXPAND_BUILTIN_SAVEREGS): New.
* i860.h (EXPAND_BUILTIN_SAVEREGS): New.
(BUILD_VA_LIST_TYPE): New.
(EXPAND_BUILTIN_VA_START): New.
(EXPAND_BUILTIN_VA_ARG): New.
* i860.c (output_delayed_branch): Disable.
(output_delay_insn): Likewise.
(i860_saveregs): New.
(i860_build_va_list): New.
(i860_va_start): New.
(i860_va_arg): New.
* i860.md: Disable all peepholes using output_delayed_branch.
* i860/sysv4.h (I860_SVR4_VA_LIST): New.
From-SVN: r28259
This commit is contained in:
Richard Henderson
Richard Henderson
parent
eb11a47347
commit
0174469a67
@ -1,3 +1,18 @@
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Sun Jul 25 23:51:59 1999 Richard Henderson <rth@cygnus.com>
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* i860.h (EXPAND_BUILTIN_SAVEREGS): New.
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(BUILD_VA_LIST_TYPE): New.
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(EXPAND_BUILTIN_VA_START): New.
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(EXPAND_BUILTIN_VA_ARG): New.
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* i860.c (output_delayed_branch): Disable.
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(output_delay_insn): Likewise.
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(i860_saveregs): New.
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(i860_build_va_list): New.
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(i860_va_start): New.
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(i860_va_arg): New.
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* i860.md: Disable all peepholes using output_delayed_branch.
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* i860/sysv4.h (I860_SVR4_VA_LIST): New.
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Sun Jul 25 23:44:13 1999 Richard Henderson <rth@cygnus.com>
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* clipper.h (EXPAND_BUILTIN_SAVEREGS): Remove argument.
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@ -29,6 +29,7 @@ Boston, MA 02111-1307, USA. */
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#include <stdio.h>
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#include "flags.h"
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#include "rtl.h"
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#include "tree.h"
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#include "regs.h"
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#include "hard-reg-set.h"
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#include "real.h"
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@ -38,6 +39,7 @@ Boston, MA 02111-1307, USA. */
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#include "output.h"
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#include "recog.h"
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#include "insn-attr.h"
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#include "expr.h"
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static rtx find_addr_reg ();
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@ -1323,6 +1325,7 @@ output_block_move (operands)
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return "";
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}
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#if 0
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/* Output a delayed branch insn with the delay insn in its
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branch slot. The delayed branch insn template is in TEMPLATE,
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with operands OPERANDS. The insn in its delay slot is INSN.
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@ -1343,6 +1346,9 @@ output_block_move (operands)
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or l%x,%0,%1
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*/
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/* ??? Disabled because this re-recognition is incomplete and causes
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constrain_operands to segfault. Anyone who cares should fix up
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the code to use the DBR pass. */
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char *
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output_delayed_branch (template, operands, insn)
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@ -1512,6 +1518,7 @@ output_delay_insn (delay_insn)
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output_asm_insn (template, recog_operand);
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return "";
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}
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#endif
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/* Special routine to convert an SFmode value represented as a
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CONST_DOUBLE into its equivalent unsigned long bit pattern.
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@ -2095,3 +2102,250 @@ function_epilogue (asm_file, local_bytes)
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text_section();
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#endif
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}
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/* Expand a library call to __builtin_saveregs. */
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rtx
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i860_saveregs ()
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{
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rtx fn = gen_rtx_SYMBOL_REF (Pmode, "__builtin_saveregs");
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rtx save = gen_reg_rtx (Pmode);
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rtx valreg = LIBCALL_VALUE (Pmode);
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rtx ret;
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/* The return value register overlaps the first argument register.
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Save and restore it around the call. */
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emit_move_insn (save, valreg);
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ret = emit_library_call_value (fn, NULL_RTX, 1, Pmode, 0);
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if (GET_CODE (ret) != REG || REGNO (ret) < FIRST_PSEUDO_REGISTER)
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ret = copy_to_reg (ret);
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emit_move_insn (valreg, save);
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return ret;
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}
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tree
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i860_build_va_list ()
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{
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tree field_ireg_used, field_freg_used, field_reg_base, field_mem_ptr;
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tree record;
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record = make_node (RECORD_TYPE);
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field_ireg_used = build_decl (FIELD_DECL, get_identifier ("__ireg_used"),
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unsigned_type_node);
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field_freg_used = build_decl (FIELD_DECL, get_identifier ("__freg_used"),
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unsigned_type_node);
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field_reg_base = build_decl (FIELD_DECL, get_identifier ("__reg_base"),
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ptr_type_node);
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field_mem_ptr = build_decl (FIELD_DECL, get_identifier ("__mem_ptr"),
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ptr_type_node);
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DECL_FIELD_CONTEXT (field_ireg_used) = record;
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DECL_FIELD_CONTEXT (field_freg_used) = record;
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DECL_FIELD_CONTEXT (field_reg_base) = record;
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DECL_FIELD_CONTEXT (field_mem_ptr) = record;
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#ifdef I860_SVR4_VA_LIST
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TYPE_FIELDS (record) = field_ireg_used;
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TREE_CHAIN (field_ireg_used) = field_freg_used;
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TREE_CHAIN (field_freg_used) = field_reg_base;
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TREE_CHAIN (field_reg_base) = field_mem_ptr;
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#else
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TYPE_FIELDS (record) = field_reg_base;
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TREE_CHAIN (field_reg_base) = field_mem_ptr;
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TREE_CHAIN (field_mem_ptr) = field_ireg_used;
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TREE_CHAIN (field_ireg_used) = field_freg_used;
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#endif
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layout_type (record);
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return record;
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}
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void
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i860_va_start (stdarg_p, valist, nextarg)
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int stdarg_p;
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tree valist;
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rtx nextarg;
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{
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tree saveregs, t;
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saveregs = make_tree (build_pointer_type (va_list_type_node),
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expand_builtin_saveregs ());
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saveregs = build1 (INDIRECT_REF, va_list_type_node, saveregs);
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if (stdarg_p)
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{
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tree field_ireg_used, field_freg_used, field_reg_base, field_mem_ptr;
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tree ireg_used, freg_used, reg_base, mem_ptr;
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#ifdef I860_SVR4_VA_LIST
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field_ireg_used = TYPE_FIELDS (va_list_type_node);
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field_freg_used = TREE_CHAIN (field_ireg_used);
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field_reg_base = TREE_CHAIN (field_freg_used);
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field_mem_ptr = TREE_CHAIN (field_reg_base);
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#else
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field_reg_base = TYPE_FIELDS (va_list_type_node);
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field_mem_ptr = TREE_CHAIN (field_reg_base);
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field_ireg_used = TREE_CHAIN (field_mem_ptr);
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field_freg_used = TREE_CHAIN (field_ireg_used);
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#endif
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ireg_used = build (COMPONENT_REF, TREE_TYPE (field_ireg_used),
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valist, field_ireg_used);
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freg_used = build (COMPONENT_REF, TREE_TYPE (field_freg_used),
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valist, field_freg_used);
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reg_base = build (COMPONENT_REF, TREE_TYPE (field_reg_base),
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valist, field_reg_base);
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mem_ptr = build (COMPONENT_REF, TREE_TYPE (field_mem_ptr),
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valist, field_mem_ptr);
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t = build_int_2 (current_function_args_info.ints, 0);
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t = build (MODIFY_EXPR, TREE_TYPE (ireg_used), ireg_used, t);
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TREE_SIDE_EFFECTS (t) = 1;
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expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
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t = build_int_2 (ROUNDUP (current_function_args_info.floats, 8), 0);
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t = build (MODIFY_EXPR, TREE_TYPE (freg_used), freg_used, t);
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TREE_SIDE_EFFECTS (t) = 1;
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expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
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t = build (COMPONENT_REF, TREE_TYPE (field_reg_base),
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saveregs, field_reg_base);
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t = build (MODIFY_EXPR, TREE_TYPE (reg_base), reg_base, t);
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TREE_SIDE_EFFECTS (t) = 1;
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expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
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t = make_tree (ptr_type_node, nextarg);
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t = build (MODIFY_EXPR, TREE_TYPE (mem_ptr), mem_ptr, t);
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TREE_SIDE_EFFECTS (t) = 1;
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expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
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}
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else
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{
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t = build (MODIFY_EXPR, va_list_type_node, valist, saveregs);
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TREE_SIDE_EFFECTS (t) = 1;
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expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
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}
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}
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#define NUM_PARM_FREGS 8
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#define NUM_PARM_IREGS 12
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#ifdef I860_SVR4_VARARGS
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#define FREG_OFFSET 0
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#define IREG_OFFSET (NUM_PARM_FREGS * UNITS_PER_WORD)
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#else
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#define FREG_OFFSET (NUM_PARM_IREGS * UNITS_PER_WORD)
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#define IREG_OFFSET 0
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#endif
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rtx
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i860_va_arg (valist, type)
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tree valist, type;
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{
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tree field_ireg_used, field_freg_used, field_reg_base, field_mem_ptr;
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tree type_ptr_node, t;
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rtx lab_over = NULL_RTX;
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rtx ret, val;
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HOST_WIDE_INT align;
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#ifdef I860_SVR4_VA_LIST
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field_ireg_used = TYPE_FIELDS (va_list_type_node);
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field_freg_used = TREE_CHAIN (field_ireg_used);
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field_reg_base = TREE_CHAIN (field_freg_used);
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field_mem_ptr = TREE_CHAIN (field_reg_base);
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#else
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field_reg_base = TYPE_FIELDS (va_list_type_node);
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field_mem_ptr = TREE_CHAIN (field_reg_base);
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field_ireg_used = TREE_CHAIN (field_mem_ptr);
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field_freg_used = TREE_CHAIN (field_ireg_used);
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#endif
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field_ireg_used = build (COMPONENT_REF, TREE_TYPE (field_ireg_used),
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valist, field_ireg_used);
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field_freg_used = build (COMPONENT_REF, TREE_TYPE (field_freg_used),
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valist, field_freg_used);
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field_reg_base = build (COMPONENT_REF, TREE_TYPE (field_reg_base),
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valist, field_reg_base);
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field_mem_ptr = build (COMPONENT_REF, TREE_TYPE (field_mem_ptr),
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valist, field_mem_ptr);
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ret = gen_reg_rtx (Pmode);
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type_ptr_node = build_pointer_type (type);
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if (! AGGREGATE_TYPE_P (type))
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{
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int nparm, incr, ofs;
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tree field;
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rtx lab_false;
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if (FLOAT_TYPE_P (type))
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{
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field = field_freg_used;
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nparm = NUM_PARM_FREGS;
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incr = 2;
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ofs = FREG_OFFSET;
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}
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else
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{
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field = field_ireg_used;
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nparm = NUM_PARM_IREGS;
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incr = int_size_in_bytes (type) / UNITS_PER_WORD;
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ofs = IREG_OFFSET;
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}
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lab_false = gen_label_rtx ();
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lab_over = gen_label_rtx ();
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emit_cmp_and_jump_insns (expand_expr (field, NULL_RTX, 0, 0),
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GEN_INT (nparm - incr), GT, const0_rtx,
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TYPE_MODE (TREE_TYPE (field)),
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TREE_UNSIGNED (field), 0, lab_false);
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t = fold (build (POSTINCREMENT_EXPR, TREE_TYPE (field), field,
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build_int_2 (incr, 0)));
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TREE_SIDE_EFFECTS (t) = 1;
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t = fold (build (MULT_EXPR, TREE_TYPE (field), field,
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build_int_2 (UNITS_PER_WORD, 0)));
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TREE_SIDE_EFFECTS (t) = 1;
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t = fold (build (PLUS_EXPR, ptr_type_node, field_reg_base,
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fold (build (PLUS_EXPR, TREE_TYPE (field), t,
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build_int_2 (ofs, 0)))));
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TREE_SIDE_EFFECTS (t) = 1;
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val = expand_expr (t, ret, VOIDmode, EXPAND_NORMAL);
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if (val != ret)
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emit_move_insn (ret, val);
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emit_jump_insn (gen_jump (lab_over));
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emit_barrier ();
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emit_label (lab_false);
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}
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align = TYPE_ALIGN (type);
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if (align < BITS_PER_WORD)
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align = BITS_PER_WORD;
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align /= BITS_PER_UNIT;
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t = build (PLUS_EXPR, ptr_type_node, field_mem_ptr,
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build_int_2 (align - 1, 0));
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t = build (BIT_AND_EXPR, ptr_type_node, t, build_int_2 (-align, -1));
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val = expand_expr (t, ret, VOIDmode, EXPAND_NORMAL);
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if (val != ret)
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emit_move_insn (ret, val);
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t = fold (build (PLUS_EXPR, ptr_type_node,
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make_tree (ptr_type_node, ret),
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build_int_2 (int_size_in_bytes (type), 0)));
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t = build (MODIFY_EXPR, ptr_type_node, field_mem_ptr, t);
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TREE_SIDE_EFFECTS (t) = 1;
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expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
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if (lab_over)
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emit_label (lab_over);
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return ret;
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}
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@ -596,6 +596,22 @@ struct cumulative_args { int ints, floats; };
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#define FUNCTION_EPILOGUE(FILE, SIZE) function_epilogue ((FILE), (SIZE))
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/* Generate necessary RTL for __builtin_saveregs(). */
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#define EXPAND_BUILTIN_SAVEREGS() \
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i860_saveregs()
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/* Define the `__builtin_va_list' type for the ABI. */
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#define BUILD_VA_LIST_TYPE(VALIST) \
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(VALIST) = i860_build_va_list ()
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/* Implement `va_start' for varargs and stdarg. */
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#define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
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i860_va_start (stdarg, valist, nextarg)
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/* Implement `va_arg'. */
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#define EXPAND_BUILTIN_VA_ARG(valist, type) \
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i860_va_arg (valist, type)
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|
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/* Store in the variable DEPTH the initial difference between the
|
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frame pointer reg contents and the stack pointer reg contents,
|
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as of the start of the function body. This depends on the layout
|
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@ -1428,5 +1444,7 @@ extern char *output_move_double ();
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extern char *output_fp_move_double ();
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extern char *output_block_move ();
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extern char *output_delay_insn ();
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#if 0
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extern char *output_delayed_branch ();
|
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#endif
|
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extern void output_load_address ();
|
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|
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@ -2072,20 +2072,24 @@ fmul.ss %1,%0,%4\;fmul.ss %3,%4,%0\";
|
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|
||||
;; Here are two simple peepholes which fill the delay slot of
|
||||
;; an unconditional branch.
|
||||
|
||||
(define_peephole
|
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[(set (match_operand:SI 0 "register_operand" "=rf")
|
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(match_operand:SI 1 "single_insn_src_p" "gfG"))
|
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(set (pc) (label_ref (match_operand 2 "" "")))]
|
||||
""
|
||||
"* return output_delayed_branch (\"br %l2\", operands, insn);")
|
||||
|
||||
(define_peephole
|
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[(set (match_operand:SI 0 "memory_operand" "=m")
|
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(match_operand:SI 1 "reg_or_0_operand" "rfJ"))
|
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(set (pc) (label_ref (match_operand 2 "" "")))]
|
||||
""
|
||||
"* return output_delayed_branch (\"br %l2\", operands, insn);")
|
||||
;
|
||||
;; ??? All disabled, because output_delayed_branch is a crock
|
||||
;; that will reliably segfault. This should be using the dbr
|
||||
;; pass in any case. Anyone who cares is welcome to fix it.
|
||||
;
|
||||
;(define_peephole
|
||||
; [(set (match_operand:SI 0 "register_operand" "=rf")
|
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; (match_operand:SI 1 "single_insn_src_p" "gfG"))
|
||||
; (set (pc) (label_ref (match_operand 2 "" "")))]
|
||||
; ""
|
||||
; "* return output_delayed_branch (\"br %l2\", operands, insn);")
|
||||
;
|
||||
;(define_peephole
|
||||
; [(set (match_operand:SI 0 "memory_operand" "=m")
|
||||
; (match_operand:SI 1 "reg_or_0_operand" "rfJ"))
|
||||
; (set (pc) (label_ref (match_operand 2 "" "")))]
|
||||
; ""
|
||||
; "* return output_delayed_branch (\"br %l2\", operands, insn);")
|
||||
|
||||
(define_insn "tablejump"
|
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[(set (pc) (match_operand:SI 0 "register_operand" "r"))
|
||||
@ -2093,13 +2097,13 @@ fmul.ss %1,%0,%4\;fmul.ss %3,%4,%0\";
|
||||
""
|
||||
"bri %0\;nop")
|
||||
|
||||
(define_peephole
|
||||
[(set (match_operand:SI 0 "memory_operand" "=m")
|
||||
(match_operand:SI 1 "reg_or_0_operand" "rfJ"))
|
||||
(set (pc) (match_operand:SI 2 "register_operand" "r"))
|
||||
(use (label_ref (match_operand 3 "" "")))]
|
||||
""
|
||||
"* return output_delayed_branch (\"bri %2\", operands, insn);")
|
||||
;(define_peephole
|
||||
; [(set (match_operand:SI 0 "memory_operand" "=m")
|
||||
; (match_operand:SI 1 "reg_or_0_operand" "rfJ"))
|
||||
; (set (pc) (match_operand:SI 2 "register_operand" "r"))
|
||||
; (use (label_ref (match_operand 3 "" "")))]
|
||||
; ""
|
||||
; "* return output_delayed_branch (\"bri %2\", operands, insn);")
|
||||
|
||||
;;- jump to subroutine
|
||||
(define_expand "call"
|
||||
@ -2137,37 +2141,37 @@ fmul.ss %1,%0,%4\;fmul.ss %3,%4,%0\";
|
||||
return \"call %0\;nop\";
|
||||
}")
|
||||
|
||||
(define_peephole
|
||||
[(set (match_operand:SI 0 "register_operand" "=rf")
|
||||
(match_operand:SI 1 "single_insn_src_p" "gfG"))
|
||||
(call (match_operand:SI 2 "memory_operand" "m")
|
||||
(match_operand 3 "" "i"))]
|
||||
;;- Don't use operand 1 for most machines.
|
||||
"! reg_mentioned_p (operands[0], operands[2])"
|
||||
"*
|
||||
{
|
||||
/* strip the MEM. */
|
||||
operands[2] = XEXP (operands[2], 0);
|
||||
if (GET_CODE (operands[2]) == REG)
|
||||
return output_delayed_branch (\"calli %2\", operands, insn);
|
||||
return output_delayed_branch (\"call %2\", operands, insn);
|
||||
}")
|
||||
;(define_peephole
|
||||
; [(set (match_operand:SI 0 "register_operand" "=rf")
|
||||
; (match_operand:SI 1 "single_insn_src_p" "gfG"))
|
||||
; (call (match_operand:SI 2 "memory_operand" "m")
|
||||
; (match_operand 3 "" "i"))]
|
||||
; ;;- Don't use operand 1 for most machines.
|
||||
; "! reg_mentioned_p (operands[0], operands[2])"
|
||||
; "*
|
||||
;{
|
||||
; /* strip the MEM. */
|
||||
; operands[2] = XEXP (operands[2], 0);
|
||||
; if (GET_CODE (operands[2]) == REG)
|
||||
; return output_delayed_branch (\"calli %2\", operands, insn);
|
||||
; return output_delayed_branch (\"call %2\", operands, insn);
|
||||
;}")
|
||||
|
||||
(define_peephole
|
||||
[(set (match_operand:SI 0 "memory_operand" "=m")
|
||||
(match_operand:SI 1 "reg_or_0_operand" "rfJ"))
|
||||
(call (match_operand:SI 2 "call_insn_operand" "m")
|
||||
(match_operand 3 "" "i"))]
|
||||
;;- Don't use operand 1 for most machines.
|
||||
""
|
||||
"*
|
||||
{
|
||||
/* strip the MEM. */
|
||||
operands[2] = XEXP (operands[2], 0);
|
||||
if (GET_CODE (operands[2]) == REG)
|
||||
return output_delayed_branch (\"calli %2\", operands, insn);
|
||||
return output_delayed_branch (\"call %2\", operands, insn);
|
||||
}")
|
||||
;(define_peephole
|
||||
; [(set (match_operand:SI 0 "memory_operand" "=m")
|
||||
; (match_operand:SI 1 "reg_or_0_operand" "rfJ"))
|
||||
; (call (match_operand:SI 2 "call_insn_operand" "m")
|
||||
; (match_operand 3 "" "i"))]
|
||||
; ;;- Don't use operand 1 for most machines.
|
||||
; ""
|
||||
; "*
|
||||
;{
|
||||
; /* strip the MEM. */
|
||||
; operands[2] = XEXP (operands[2], 0);
|
||||
; if (GET_CODE (operands[2]) == REG)
|
||||
; return output_delayed_branch (\"calli %2\", operands, insn);
|
||||
; return output_delayed_branch (\"call %2\", operands, insn);
|
||||
;}")
|
||||
|
||||
(define_expand "call_value"
|
||||
[(set (match_operand 0 "register_operand" "=rf")
|
||||
@ -2205,39 +2209,39 @@ fmul.ss %1,%0,%4\;fmul.ss %3,%4,%0\";
|
||||
return \"call %1\;nop\";
|
||||
}")
|
||||
|
||||
(define_peephole
|
||||
[(set (match_operand:SI 0 "register_operand" "=rf")
|
||||
(match_operand:SI 1 "single_insn_src_p" "gfG"))
|
||||
(set (match_operand 2 "" "=rf")
|
||||
(call (match_operand:SI 3 "call_insn_operand" "m")
|
||||
(match_operand 4 "" "i")))]
|
||||
;;- Don't use operand 4 for most machines.
|
||||
"! reg_mentioned_p (operands[0], operands[3])"
|
||||
"*
|
||||
{
|
||||
/* strip the MEM. */
|
||||
operands[3] = XEXP (operands[3], 0);
|
||||
if (GET_CODE (operands[3]) == REG)
|
||||
return output_delayed_branch (\"calli %3\", operands, insn);
|
||||
return output_delayed_branch (\"call %3\", operands, insn);
|
||||
}")
|
||||
;(define_peephole
|
||||
; [(set (match_operand:SI 0 "register_operand" "=rf")
|
||||
; (match_operand:SI 1 "single_insn_src_p" "gfG"))
|
||||
; (set (match_operand 2 "" "=rf")
|
||||
; (call (match_operand:SI 3 "call_insn_operand" "m")
|
||||
; (match_operand 4 "" "i")))]
|
||||
; ;;- Don't use operand 4 for most machines.
|
||||
; "! reg_mentioned_p (operands[0], operands[3])"
|
||||
; "*
|
||||
;{
|
||||
; /* strip the MEM. */
|
||||
; operands[3] = XEXP (operands[3], 0);
|
||||
; if (GET_CODE (operands[3]) == REG)
|
||||
; return output_delayed_branch (\"calli %3\", operands, insn);
|
||||
; return output_delayed_branch (\"call %3\", operands, insn);
|
||||
;}")
|
||||
|
||||
(define_peephole
|
||||
[(set (match_operand:SI 0 "memory_operand" "=m")
|
||||
(match_operand:SI 1 "reg_or_0_operand" "rJf"))
|
||||
(set (match_operand 2 "" "=rf")
|
||||
(call (match_operand:SI 3 "call_insn_operand" "m")
|
||||
(match_operand 4 "" "i")))]
|
||||
;;- Don't use operand 4 for most machines.
|
||||
""
|
||||
"*
|
||||
{
|
||||
/* strip the MEM. */
|
||||
operands[3] = XEXP (operands[3], 0);
|
||||
if (GET_CODE (operands[3]) == REG)
|
||||
return output_delayed_branch (\"calli %3\", operands, insn);
|
||||
return output_delayed_branch (\"call %3\", operands, insn);
|
||||
}")
|
||||
;(define_peephole
|
||||
; [(set (match_operand:SI 0 "memory_operand" "=m")
|
||||
; (match_operand:SI 1 "reg_or_0_operand" "rJf"))
|
||||
; (set (match_operand 2 "" "=rf")
|
||||
; (call (match_operand:SI 3 "call_insn_operand" "m")
|
||||
; (match_operand 4 "" "i")))]
|
||||
; ;;- Don't use operand 4 for most machines.
|
||||
; ""
|
||||
; "*
|
||||
;{
|
||||
; /* strip the MEM. */
|
||||
; operands[3] = XEXP (operands[3], 0);
|
||||
; if (GET_CODE (operands[3]) == REG)
|
||||
; return output_delayed_branch (\"calli %3\", operands, insn);
|
||||
; return output_delayed_branch (\"call %3\", operands, insn);
|
||||
;}")
|
||||
|
||||
;; Call subroutine returning any type.
|
||||
|
||||
@ -2301,10 +2305,10 @@ fmul.ss %1,%0,%4\;fmul.ss %3,%4,%0\";
|
||||
return \"orh %H2,%?r0,%?r31\;or %L2,%?r31,%?r31\;ld.l %?r31(%1),%0\";
|
||||
}")
|
||||
|
||||
(define_peephole
|
||||
[(set (match_operand:SI 0 "register_operand" "=rf")
|
||||
(match_operand:SI 1 "single_insn_src_p" "gfG"))
|
||||
(set (pc) (match_operand:SI 2 "register_operand" "r"))
|
||||
(use (label_ref (match_operand 3 "" "")))]
|
||||
"REGNO (operands[0]) != REGNO (operands[2])"
|
||||
"* return output_delayed_branch (\"bri %2\", operands, insn);")
|
||||
;(define_peephole
|
||||
; [(set (match_operand:SI 0 "register_operand" "=rf")
|
||||
; (match_operand:SI 1 "single_insn_src_p" "gfG"))
|
||||
; (set (pc) (match_operand:SI 2 "register_operand" "r"))
|
||||
; (use (label_ref (match_operand 3 "" "")))]
|
||||
; "REGNO (operands[0]) != REGNO (operands[2])"
|
||||
; "* return output_delayed_branch (\"bri %2\", operands, insn);")
|
||||
|
||||
@ -34,6 +34,10 @@ Boston, MA 02111-1307, USA. */
|
||||
#define CPP_PREDEFINES \
|
||||
"-Di860 -Dunix -DSVR4 -D__svr4__ -Asystem(unix) -Asystem(svr4) -Acpu(i860) -Amachine(i860)"
|
||||
|
||||
/* For the benefit of i860_va_arg, flag it this way too. */
|
||||
|
||||
#define I860_SVR4_VA_LIST 1
|
||||
|
||||
/* The prefix to be used in assembler output for all names of registers.
|
||||
This string gets prepended to all i860 register names (svr4 only). */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user