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[AArch64] Don't split 64-bit constant stores to volatile location 

The optimisation to optimise:
   typedef unsigned long long u64;

   void bar(u64 *x)
   {
     *x = 0xabcdef10abcdef10;
   }

from:
        mov     x1, 61200
        movk    x1, 0xabcd, lsl 16
        movk    x1, 0xef10, lsl 32
        movk    x1, 0xabcd, lsl 48
        str     x1, [x0]

into:
        mov     w1, 61200
        movk    w1, 0xabcd, lsl 16
        stp     w1, w1, [x0]

ends up producing two distinct stores if the destination is volatile:
  void bar(u64 *x)
  {
    *(volatile u64 *)x = 0xabcdef10abcdef10;
  }
        mov     w1, 61200
        movk    w1, 0xabcd, lsl 16
        str     w1, [x0]
        str     w1, [x0, 4]

because we end up not merging the strs into an stp. It's questionable whether the use of STP is valid for volatile in the first place.
To avoid unnecessary pain in a context where it's unlikely to be performance critical [1] (use of volatile), this patch avoids this
transformation for volatile destinations, so we produce the original single STR-X.

Bootstrapped and tested on aarch64-none-linux-gnu.

[1] https://lore.kernel.org/lkml/20190821103200.kpufwtviqhpbuv2n@willie-the-truck/

	* config/aarch64/aarch64.md (mov<mode>): Don't call
	aarch64_split_dimode_const_store on volatile MEM.

	* gcc.target/aarch64/nosplit-di-const-volatile_1.c: New test.

From-SVN: r276098
This commit is contained in:
Kyrylo Tkachov 2019-09-24 13:39:40 +00:00 committed by Kyrylo Tkachov
parent 937960dfd7
commit 01b9402c48
4 changed files with 26 additions and 2 deletions
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5
gcc/ChangeLog
View File

@ -1,3 +1,8 @@
2019-09-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64.md (mov<mode>): Don't call
aarch64_split_dimode_const_store on volatile MEM.
2019-09-24 Stamatis Markianos-Wright <stam.markianos-wright@arm.com>
* config/aarch64/aarch64-option-extensions.def (fp16fml):

4
gcc/config/aarch64/aarch64.md
View File

@ -1104,8 +1104,8 @@
(match_operand:GPI 1 "general_operand"))]
""
"
if (MEM_P (operands[0]) && CONST_INT_P (operands[1])
&& <MODE>mode == DImode
if (MEM_P (operands[0]) && !MEM_VOLATILE_P (operands[0])
&& CONST_INT_P (operands[1]) && <MODE>mode == DImode
&& aarch64_split_dimode_const_store (operands[0], operands[1]))
DONE;

4
gcc/testsuite/ChangeLog
View File

@ -1,3 +1,7 @@
2019-09-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* gcc.target/aarch64/nosplit-di-const-volatile_1.c: New test.
2019-09-24 Jakub Jelinek <jakub@redhat.com>
PR middle-end/91866

15
gcc/testsuite/gcc.target/aarch64/nosplit-di-const-volatile_1.c Normal file
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@ -0,0 +1,15 @@
/* Check that storing the 64-bit immediate to a volatile location is done
with a single store. */
/* { dg-do compile } */
/* { dg-options "-O2" } */
typedef unsigned long long u64;
void bar (u64 *x)
{
*(volatile u64 *)x = 0xabcdef10abcdef10ULL;
}
/* { dg-final { scan-assembler-times "str\tx..?, .*" 1 } } */
/* { dg-final { scan-assembler-not "str\tw..?, .*" } } */