aarch64: ilp32 testsuite fixes
This fixes test failures on ilp32 introduced in r11-3032-gd4febc75e8dfab23bd3132d5747eded918f85107. The assembler checks in extend-syntax.c simply needed adjusting for 32-bit pointers. It appears the subsp.c test has never passed on ILP32 due to a missed optimisation there. Since this isn't a code quality regression, disable that check on ILP32. gcc/testsuite/ChangeLog: * gcc.target/aarch64/extend-syntax.c: Fix assembler checks for ilp32, disable check-function-bodies on ilp32. * gcc.target/aarch64/subsp.c: Only check second scan-assembler on lp64 since the code on ilp32 is missing the optimization needed for this test to pass.
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@ -20,6 +20,7 @@ unsigned long long *add1(unsigned long long *p, unsigned x)
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*/
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unsigned long long add2(unsigned long long x, unsigned y)
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{
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/* { dg-final { scan-assembler-times "add\tx0, x0, w1, uxtw" 1 { target ilp32 } } } */
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return x + y;
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}
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@ -34,6 +35,9 @@ double *add3(double *p, int x)
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return p + x;
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}
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// add1 and add3 should both generate this on ILP32:
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/* { dg-final { scan-assembler-times "add\tw0, w0, w1, lsl 3" 2 { target ilp32 } } } */
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// Hits *sub_zero_extendsi_di (*sub_<optab><ALLX:mode>_<GPI:mode>).
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/*
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** sub1:
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@ -42,6 +46,7 @@ double *add3(double *p, int x)
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*/
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unsigned long long sub1(unsigned long long x, unsigned n)
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{
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/* { dg-final { scan-assembler-times "sub\tx0, x0, w1, uxtw" 1 { target ilp32 } } } */
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return x - n;
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}
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@ -67,6 +72,9 @@ double *sub3(double *p, int n)
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return p - n;
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}
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// sub2 and sub3 should both generate this on ILP32:
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/* { dg-final { scan-assembler-times "sub\tw0, w0, w1, lsl 3" 2 { target ilp32 } } } */
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// Hits *adds_zero_extendsi_di (*adds_<optab><ALLX:mode>_<GPI:mode>).
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int adds1(unsigned long long x, unsigned y)
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{
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@ -97,7 +105,8 @@ int subs1(unsigned long long x, unsigned y)
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unsigned long long *w;
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int subs2(unsigned long long *x, int y)
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{
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/* { dg-final { scan-assembler-times "subs\tx\[0-9\]+, x\[0-9\]+, w\[0-9\]+, sxtw 3" 1 } } */
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/* { dg-final { scan-assembler-times "subs\tx\[0-9\]+, x\[0-9\]+, w\[0-9\]+, sxtw 3" 1 { target lp64 } } } */
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/* { dg-final { scan-assembler-times "subs\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" 1 { target ilp32 } } } */
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unsigned long long *t = x - y;
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w = t;
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return !!t;
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@ -117,4 +126,4 @@ int cmp2(unsigned long long x, int y)
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return x == ((unsigned long long)y << 3);
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}
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/* { dg-final { check-function-bodies "**" "" "" } } */
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/* { dg-final { check-function-bodies "**" "" "" { target lp64 } } } */
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@ -16,4 +16,4 @@ f2 (int *x, int y)
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}
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/* { dg-final { scan-assembler "sub\tsp, sp, x\[0-9\]*\n" } } */
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/* { dg-final { scan-assembler "sub\tsp, sp, w\[0-9\]*, sxtw 4\n" } } */
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/* { dg-final { scan-assembler "sub\tsp, sp, w\[0-9\]*, sxtw 4\n" { target lp64 } } } */
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