i386.md (fix_trunc<mode>di_sse): Remove "x" from "xm" alternative.
* config/i386/i386.md (fix_trunc<mode>di_sse): Remove "x" from "xm" alternative. (fix_trunc<mode>si_sse): Ditto. (*floatsisf2_mixed, *floatsisf2_sse): Ditto. (*floatsidf2_mixed, *floatsidf2_sse): Ditto. (*floatdisf2_mixed, *floatdisf2_sse): Ditto. (*floatdidf2_mixed, *floatdidf2_sse): Ditto. (floathi<mode>2): Rename from floathisf2 and floathidf2. Macroize expander using SSEMODEF mode macro. (floatsi<mode>2): Rename from floatsisf2 and floashidf2. Macroize expander using SSEMODEF mode macro. (*floathi<mode>2_i387): Rename from *floathisf2_i387 and *floathidf2_i387. Macroize insn using X87MODEF12 mode macro. (*floatsi<mode>2_i387): Rename from *floatsisf2_i387 and *floatsidf2_i387. Macroize insn using X87MODEF12 mode macro. (*floatdi<mode>2_i387): Rename from *floatdisf2_i387 and *floatdidf2_i387. Macroize insn using X87MODEF12 mode macro. (float<mode>xf2): Rename from floathixf2, floatsixf2 and floatdixf2. Macroize insn using X87MODEF mode macro. From-SVN: r123693
This commit is contained in:
Uros Bizjak
Uros Bizjak
parent
11202768fe
commit
0218c0120c
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@ -1,3 +1,25 @@
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2007-04-10 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.md (fix_trunc<mode>di_sse): Remove "x" from "xm"
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alternative.
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(fix_trunc<mode>si_sse): Ditto.
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(*floatsisf2_mixed, *floatsisf2_sse): Ditto.
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(*floatsidf2_mixed, *floatsidf2_sse): Ditto.
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(*floatdisf2_mixed, *floatdisf2_sse): Ditto.
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(*floatdidf2_mixed, *floatdidf2_sse): Ditto.
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(floathi<mode>2): Rename from floathisf2 and floathidf2. Macroize
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expander using SSEMODEF mode macro.
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(floatsi<mode>2): Rename from floatsisf2 and floashidf2. Macroize
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expander using SSEMODEF mode macro.
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(*floathi<mode>2_i387): Rename from *floathisf2_i387 and
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*floathidf2_i387. Macroize insn using X87MODEF12 mode macro.
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(*floatsi<mode>2_i387): Rename from *floatsisf2_i387 and
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*floatsidf2_i387. Macroize insn using X87MODEF12 mode macro.
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(*floatdi<mode>2_i387): Rename from *floatdisf2_i387 and
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*floatdidf2_i387. Macroize insn using X87MODEF12 mode macro.
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(float<mode>xf2): Rename from floathixf2, floatsixf2 and floatdixf2.
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Macroize insn using X87MODEF mode macro.
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2007-04-09 H.J. Lu <hongjiu.lu@intel.com>
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* config/i386/sse.md (sse2_pinsrw): Removed.
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@ -4184,7 +4184,7 @@
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;; When SSE is available, it is always faster to use it!
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(define_insn "fix_trunc<mode>di_sse"
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[(set (match_operand:DI 0 "register_operand" "=r,r")
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(fix:DI (match_operand:SSEMODEF 1 "nonimmediate_operand" "x,xm")))]
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(fix:DI (match_operand:SSEMODEF 1 "nonimmediate_operand" "x,m")))]
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"TARGET_64BIT && SSE_FLOAT_MODE_P (<MODE>mode)
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&& (!TARGET_FISTTP || TARGET_SSE_MATH)"
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"cvtts<ssemodefsuffix>2si{q}\t{%1, %0|%0, %1}"
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@ -4195,7 +4195,7 @@
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(define_insn "fix_trunc<mode>si_sse"
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[(set (match_operand:SI 0 "register_operand" "=r,r")
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(fix:SI (match_operand:SSEMODEF 1 "nonimmediate_operand" "x,xm")))]
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(fix:SI (match_operand:SSEMODEF 1 "nonimmediate_operand" "x,m")))]
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"SSE_FLOAT_MODE_P (<MODE>mode)
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&& (!TARGET_FISTTP || TARGET_SSE_MATH)"
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"cvtts<ssemodefsuffix>2si\t{%1, %0|%0, %1}"
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@ -4482,40 +4482,44 @@
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;; Even though we only accept memory inputs, the backend _really_
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;; wants to be able to do this between registers.
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(define_expand "floathisf2"
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[(set (match_operand:SF 0 "register_operand" "")
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(float:SF (match_operand:HI 1 "nonimmediate_operand" "")))]
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"TARGET_80387 || TARGET_SSE_MATH"
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(define_expand "floathi<mode>2"
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[(set (match_operand:SSEMODEF 0 "register_operand" "")
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(float:SSEMODEF (match_operand:HI 1 "nonimmediate_operand" "")))]
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"TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
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{
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if (TARGET_SSE_MATH)
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if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
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{
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emit_insn (gen_floatsisf2 (operands[0],
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convert_to_mode (SImode, operands[1], 0)));
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emit_insn
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(gen_floatsi<mode>2 (operands[0],
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convert_to_mode (SImode, operands[1], 0)));
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DONE;
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}
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})
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(define_insn "*floathisf2_i387"
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[(set (match_operand:SF 0 "register_operand" "=f,f")
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(float:SF (match_operand:HI 1 "nonimmediate_operand" "m,?r")))]
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"TARGET_80387 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)"
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(define_insn "*floathi<mode>2_i387"
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[(set (match_operand:X87MODEF12 0 "register_operand" "=f,f")
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(float:X87MODEF12
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(match_operand:HI 1 "nonimmediate_operand" "m,?r")))]
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"TARGET_80387
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&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
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|| TARGET_MIX_SSE_I387)"
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"@
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fild%z1\t%1
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#"
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[(set_attr "type" "fmov,multi")
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(set_attr "mode" "SF")
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(set_attr "mode" "<MODE>")
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(set_attr "unit" "*,i387")
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(set_attr "fp_int_src" "true")])
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(define_expand "floatsisf2"
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[(set (match_operand:SF 0 "register_operand" "")
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(float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
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"TARGET_80387 || TARGET_SSE_MATH"
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(define_expand "floatsi<mode>2"
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[(set (match_operand:SSEMODEF 0 "register_operand" "")
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(float:SSEMODEF (match_operand:SI 1 "nonimmediate_operand" "")))]
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"TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
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"")
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(define_insn "*floatsisf2_mixed"
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[(set (match_operand:SF 0 "register_operand" "=f,?f,x,x")
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(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
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(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,m")))]
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"TARGET_MIX_SSE_I387"
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"@
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fild%z1\t%1
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@ -4531,7 +4535,7 @@
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(define_insn "*floatsisf2_sse"
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[(set (match_operand:SF 0 "register_operand" "=x,x")
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(float:SF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
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(float:SF (match_operand:SI 1 "nonimmediate_operand" "r,m")))]
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"TARGET_SSE_MATH"
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"cvtsi2ss\t{%1, %0|%0, %1}"
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[(set_attr "type" "sseicvt")
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@ -4540,97 +4544,9 @@
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(set_attr "amdfam10_decode" "vector,double")
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(set_attr "fp_int_src" "true")])
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(define_insn "*floatsisf2_i387"
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[(set (match_operand:SF 0 "register_operand" "=f,f")
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(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r")))]
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"TARGET_80387"
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"@
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fild%z1\t%1
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#"
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[(set_attr "type" "fmov,multi")
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(set_attr "mode" "SF")
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(set_attr "unit" "*,i387")
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(set_attr "fp_int_src" "true")])
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(define_expand "floatdisf2"
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[(set (match_operand:SF 0 "register_operand" "")
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(float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
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"TARGET_80387 || (TARGET_64BIT && TARGET_SSE_MATH)"
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"")
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(define_insn "*floatdisf2_mixed"
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[(set (match_operand:SF 0 "register_operand" "=f,?f,x,x")
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(float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
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"TARGET_64BIT && TARGET_MIX_SSE_I387"
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"@
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fild%z1\t%1
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#
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cvtsi2ss{q}\t{%1, %0|%0, %1}
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cvtsi2ss{q}\t{%1, %0|%0, %1}"
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[(set_attr "type" "fmov,multi,sseicvt,sseicvt")
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(set_attr "mode" "SF")
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(set_attr "unit" "*,i387,*,*")
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(set_attr "athlon_decode" "*,*,vector,double")
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(set_attr "amdfam10_decode" "*,*,vector,double")
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(set_attr "fp_int_src" "true")])
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(define_insn "*floatdisf2_sse"
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[(set (match_operand:SF 0 "register_operand" "=x,x")
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(float:SF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
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"TARGET_64BIT && TARGET_SSE_MATH"
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"cvtsi2ss{q}\t{%1, %0|%0, %1}"
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[(set_attr "type" "sseicvt")
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(set_attr "mode" "SF")
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(set_attr "athlon_decode" "vector,double")
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(set_attr "amdfam10_decode" "vector,double")
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(set_attr "fp_int_src" "true")])
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(define_insn "*floatdisf2_i387"
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[(set (match_operand:SF 0 "register_operand" "=f,f")
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(float:SF (match_operand:DI 1 "nonimmediate_operand" "m,?r")))]
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"TARGET_80387"
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"@
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fild%z1\t%1
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#"
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[(set_attr "type" "fmov,multi")
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(set_attr "mode" "SF")
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(set_attr "unit" "*,i387")
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(set_attr "fp_int_src" "true")])
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(define_expand "floathidf2"
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[(set (match_operand:DF 0 "register_operand" "")
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(float:DF (match_operand:HI 1 "nonimmediate_operand" "")))]
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"TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
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{
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if (TARGET_SSE2 && TARGET_SSE_MATH)
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{
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emit_insn (gen_floatsidf2 (operands[0],
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convert_to_mode (SImode, operands[1], 0)));
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DONE;
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}
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})
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(define_insn "*floathidf2_i387"
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[(set (match_operand:DF 0 "register_operand" "=f,f")
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(float:DF (match_operand:HI 1 "nonimmediate_operand" "m,?r")))]
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"TARGET_80387 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)"
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"@
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fild%z1\t%1
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#"
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[(set_attr "type" "fmov,multi")
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(set_attr "mode" "DF")
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(set_attr "unit" "*,i387")
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(set_attr "fp_int_src" "true")])
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(define_expand "floatsidf2"
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[(set (match_operand:DF 0 "register_operand" "")
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(float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
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"TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
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"")
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(define_insn "*floatsidf2_mixed"
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[(set (match_operand:DF 0 "register_operand" "=f,?f,x,x")
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(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
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(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,m")))]
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"TARGET_SSE2 && TARGET_MIX_SSE_I387"
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"@
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fild%z1\t%1
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@ -4646,7 +4562,7 @@
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(define_insn "*floatsidf2_sse"
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[(set (match_operand:DF 0 "register_operand" "=x,x")
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(float:DF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
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(float:DF (match_operand:SI 1 "nonimmediate_operand" "r,m")))]
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"TARGET_SSE2 && TARGET_SSE_MATH"
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"cvtsi2sd\t{%1, %0|%0, %1}"
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[(set_attr "type" "sseicvt")
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@ -4655,18 +4571,52 @@
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(set_attr "amdfam10_decode" "vector,double")
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(set_attr "fp_int_src" "true")])
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(define_insn "*floatsidf2_i387"
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[(set (match_operand:DF 0 "register_operand" "=f,f")
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(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r")))]
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(define_insn "*floatsi<mode>2_i387"
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[(set (match_operand:X87MODEF12 0 "register_operand" "=f,f")
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(float:X87MODEF12
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(match_operand:SI 1 "nonimmediate_operand" "m,?r")))]
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"TARGET_80387"
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"@
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fild%z1\t%1
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#"
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[(set_attr "type" "fmov,multi")
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(set_attr "mode" "DF")
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(set_attr "mode" "<MODE>")
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(set_attr "unit" "*,i387")
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(set_attr "fp_int_src" "true")])
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(define_expand "floatdisf2"
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[(set (match_operand:SF 0 "register_operand" "")
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(float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
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"TARGET_80387 || (TARGET_64BIT && TARGET_SSE_MATH)"
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"")
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(define_insn "*floatdisf2_mixed"
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[(set (match_operand:SF 0 "register_operand" "=f,?f,x,x")
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(float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,m")))]
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"TARGET_64BIT && TARGET_MIX_SSE_I387"
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"@
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fild%z1\t%1
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#
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cvtsi2ss{q}\t{%1, %0|%0, %1}
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cvtsi2ss{q}\t{%1, %0|%0, %1}"
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[(set_attr "type" "fmov,multi,sseicvt,sseicvt")
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(set_attr "mode" "SF")
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(set_attr "unit" "*,i387,*,*")
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(set_attr "athlon_decode" "*,*,vector,double")
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(set_attr "amdfam10_decode" "*,*,vector,double")
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(set_attr "fp_int_src" "true")])
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(define_insn "*floatdisf2_sse"
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[(set (match_operand:SF 0 "register_operand" "=x,x")
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(float:SF (match_operand:DI 1 "nonimmediate_operand" "r,m")))]
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"TARGET_64BIT && TARGET_SSE_MATH"
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"cvtsi2ss{q}\t{%1, %0|%0, %1}"
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[(set_attr "type" "sseicvt")
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(set_attr "mode" "SF")
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(set_attr "athlon_decode" "vector,double")
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(set_attr "amdfam10_decode" "vector,double")
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(set_attr "fp_int_src" "true")])
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(define_expand "floatdidf2"
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[(set (match_operand:DF 0 "register_operand" "")
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(float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
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@ -4681,7 +4631,7 @@
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(define_insn "*floatdidf2_mixed"
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[(set (match_operand:DF 0 "register_operand" "=f,?f,x,x")
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(float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
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(float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,m")))]
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"TARGET_64BIT && TARGET_SSE2 && TARGET_MIX_SSE_I387"
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"@
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fild%z1\t%1
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@ -4697,7 +4647,7 @@
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(define_insn "*floatdidf2_sse"
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[(set (match_operand:DF 0 "register_operand" "=x,x")
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(float:DF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
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(float:DF (match_operand:DI 1 "nonimmediate_operand" "r,m")))]
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"TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH"
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"cvtsi2sd{q}\t{%1, %0|%0, %1}"
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[(set_attr "type" "sseicvt")
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@ -4706,45 +4656,22 @@
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(set_attr "amdfam10_decode" "vector,double")
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(set_attr "fp_int_src" "true")])
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(define_insn "*floatdidf2_i387"
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[(set (match_operand:DF 0 "register_operand" "=f,f")
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(float:DF (match_operand:DI 1 "nonimmediate_operand" "m,?r")))]
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(define_insn "*floatdi<mode>2_i387"
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[(set (match_operand:X87MODEF12 0 "register_operand" "=f,f")
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(float:X87MODEF12
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(match_operand:DI 1 "nonimmediate_operand" "m,?r")))]
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"TARGET_80387"
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"@
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fild%z1\t%1
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#"
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[(set_attr "type" "fmov,multi")
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(set_attr "mode" "DF")
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(set_attr "mode" "<MODE>")
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(set_attr "unit" "*,i387")
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(set_attr "fp_int_src" "true")])
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(define_insn "floathixf2"
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(define_insn "float<mode>xf2"
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[(set (match_operand:XF 0 "register_operand" "=f,f")
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(float:XF (match_operand:HI 1 "nonimmediate_operand" "m,?r")))]
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"TARGET_80387"
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"@
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fild%z1\t%1
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#"
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[(set_attr "type" "fmov,multi")
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(set_attr "mode" "XF")
|
||||
(set_attr "unit" "*,i387")
|
||||
(set_attr "fp_int_src" "true")])
|
||||
|
||||
(define_insn "floatsixf2"
|
||||
[(set (match_operand:XF 0 "register_operand" "=f,f")
|
||||
(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r")))]
|
||||
"TARGET_80387"
|
||||
"@
|
||||
fild%z1\t%1
|
||||
#"
|
||||
[(set_attr "type" "fmov,multi")
|
||||
(set_attr "mode" "XF")
|
||||
(set_attr "unit" "*,i387")
|
||||
(set_attr "fp_int_src" "true")])
|
||||
|
||||
(define_insn "floatdixf2"
|
||||
[(set (match_operand:XF 0 "register_operand" "=f,f")
|
||||
(float:XF (match_operand:DI 1 "nonimmediate_operand" "m,?r")))]
|
||||
(float:XF (match_operand:X87MODEI 1 "nonimmediate_operand" "m,?r")))]
|
||||
"TARGET_80387"
|
||||
"@
|
||||
fild%z1\t%1
|
||||
|
|
@ -4806,9 +4733,6 @@
|
|||
ix86_expand_convert_uns_didf_sse (operands[0], operands[1]);
|
||||
DONE;
|
||||
})
|
||||
|
||||
;; SSE extract/set expanders
|
||||
|
||||
|
||||
;; Add instructions
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue