invoke.texi (-mslow-flash-data): Document new option.
gcc/ChangeLog 2013-11-25 Terry Guo <terry.guo@arm.com> * doc/invoke.texi (-mslow-flash-data): Document new option. * config/arm/arm.opt (mslow-flash-data): New option. * config/arm/arm-protos.h (arm_max_const_double_inline_cost): Declare it. * config/arm/arm.h (TARGET_USE_MOVT): Always true when literal pools are disabled. (arm_disable_literal_pool): Declare it. * config/arm/arm.c (arm_disable_literal_pool): New variable. (arm_option_override): Handle new option. (thumb2_legitimate_address_p): Don't allow symbol references when literal pools are disabled. (arm_max_const_double_inline_cost): New function. * config/arm/arm.md (types.md): Include it before ... (use_literal_pool): New attribute. (enabled): Use new attribute. (split pattern): Replace symbol+offset with MOVW/MOVT. gcc/testsuite/ChangeLog 2013-11-25 Terry Guo <terry.guo@arm.com> * gcc.target/arm/thumb2-slow-flash-data.c: New. From-SVN: r205342
This commit is contained in:
Terry Guo
Xuepeng Guo
parent
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02231c1350
@ -1,3 +1,22 @@
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2013-11-25 Terry Guo <terry.guo@arm.com>
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* doc/invoke.texi (-mslow-flash-data): Document new option.
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* config/arm/arm.opt (mslow-flash-data): New option.
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* config/arm/arm-protos.h (arm_max_const_double_inline_cost): Declare
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it.
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* config/arm/arm.h (TARGET_USE_MOVT): Always true when literal pools
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are disabled.
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(arm_disable_literal_pool): Declare it.
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* config/arm/arm.c (arm_disable_literal_pool): New variable.
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(arm_option_override): Handle new option.
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(thumb2_legitimate_address_p): Don't allow symbol references when
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literal pools are disabled.
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(arm_max_const_double_inline_cost): New function.
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* config/arm/arm.md (types.md): Include it before ...
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(use_literal_pool): New attribute.
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(enabled): Use new attribute.
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(split pattern): Replace symbol+offset with MOVW/MOVT.
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2013-11-24 Steven Bosscher <steven@gcc.gnu.org>
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PR bootstrap/59279
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@ -121,6 +121,7 @@ extern rtx arm_gen_compare_reg (RTX_CODE, rtx, rtx, rtx);
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extern rtx arm_gen_return_addr_mask (void);
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extern void arm_reload_in_hi (rtx *);
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extern void arm_reload_out_hi (rtx *);
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extern int arm_max_const_double_inline_cost (void);
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extern int arm_const_double_inline_cost (rtx);
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extern bool arm_const_double_by_parts (rtx);
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extern bool arm_const_double_by_immediates (rtx);
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@ -869,6 +869,9 @@ int arm_arch_thumb_hwdiv;
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than core registers. */
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int prefer_neon_for_64bits = 0;
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/* Nonzero if we shouldn't use literal pools. */
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bool arm_disable_literal_pool = false;
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/* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference,
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we must report the mode of the memory reference from
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TARGET_PRINT_OPERAND to TARGET_PRINT_OPERAND_ADDRESS. */
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@ -2573,6 +2576,16 @@ arm_option_override (void)
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if (TARGET_APCS_FRAME)
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flag_shrink_wrap = false;
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/* We only support -mslow-flash-data on armv7-m targets. */
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if (target_slow_flash_data
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&& ((!(arm_arch7 && !arm_arch_notm) && !arm_arch7em)
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|| (TARGET_THUMB1 || flag_pic || TARGET_NEON)))
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error ("-mslow-flash-data only supports non-pic code on armv7-m targets");
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/* Currently, for slow flash data, we just disable literal pools. */
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if (target_slow_flash_data)
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arm_disable_literal_pool = true;
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/* Register global variables with the garbage collector. */
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arm_add_gc_roots ();
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}
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@ -6417,6 +6430,25 @@ thumb2_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
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&& thumb2_legitimate_index_p (mode, xop0, strict_p)));
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}
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/* Normally we can assign constant values to target registers without
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the help of constant pool. But there are cases we have to use constant
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pool like:
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1) assign a label to register.
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2) sign-extend a 8bit value to 32bit and then assign to register.
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Constant pool access in format:
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(set (reg r0) (mem (symbol_ref (".LC0"))))
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will cause the use of literal pool (later in function arm_reorg).
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So here we mark such format as an invalid format, then the compiler
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will adjust it into:
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(set (reg r0) (symbol_ref (".LC0")))
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(set (reg r0) (mem (reg r0))).
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No extra register is required, and (mem (reg r0)) won't cause the use
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of literal pools. */
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else if (arm_disable_literal_pool && code == SYMBOL_REF
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&& CONSTANT_POOL_ADDRESS_P (x))
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return 0;
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else if (GET_MODE_CLASS (mode) != MODE_FLOAT
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&& code == SYMBOL_REF
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&& CONSTANT_POOL_ADDRESS_P (x)
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@ -16222,6 +16254,19 @@ push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc,
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minipool_fix_tail = fix;
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}
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/* Return maximum allowed cost of synthesizing a 64-bit constant VAL inline.
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Returns the number of insns needed, or 99 if we always want to synthesize
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the value. */
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int
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arm_max_const_double_inline_cost ()
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{
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/* Let the value get synthesized to avoid the use of literal pools. */
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if (arm_disable_literal_pool)
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return 99;
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return ((optimize_size || arm_ld_sched) ? 3 : 4);
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}
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/* Return the cost of synthesizing a 64-bit constant VAL inline.
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Returns the number of insns needed, or 99 if we don't know how to
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do it. */
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@ -329,7 +329,9 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
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/* Should MOVW/MOVT be used in preference to a constant pool. */
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#define TARGET_USE_MOVT \
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(arm_arch_thumb2 && !optimize_size && !current_tune->prefer_constant_pool)
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(arm_arch_thumb2 \
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&& (arm_disable_literal_pool \
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|| (!optimize_size && !current_tune->prefer_constant_pool)))
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/* We could use unified syntax for arm mode, but for now we just use it
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for Thumb-2. */
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@ -554,6 +556,11 @@ extern int arm_arch_thumb_hwdiv;
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than core registers. */
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extern int prefer_neon_for_64bits;
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/* Nonzero if we shouldn't use literal pools. */
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#ifndef USED_FOR_TARGET
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extern bool arm_disable_literal_pool;
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#endif
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#ifndef TARGET_DEFAULT
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#define TARGET_DEFAULT (MASK_APCS_FRAME)
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#endif
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@ -82,6 +82,9 @@
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;; Processor type. This is created automatically from arm-cores.def.
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(include "arm-tune.md")
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;; Instruction classification types
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(include "types.md")
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; IS_THUMB is set to 'yes' when we are generating Thumb code, and 'no' when
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; generating ARM code. This is used to control the length of some insn
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; patterns that share the same RTL in both ARM and Thumb code.
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@ -191,6 +194,12 @@
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(const_string "yes")]
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(const_string "no")))
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(define_attr "use_literal_pool" "no,yes"
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(cond [(and (eq_attr "type" "f_loads,f_loadd")
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(match_test "CONSTANT_P (operands[1])"))
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(const_string "yes")]
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(const_string "no")))
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; Allows an insn to disable certain alternatives for reasons other than
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; arch support.
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(define_attr "insn_enabled" "no,yes"
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@ -210,6 +219,10 @@
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(match_test "arm_restrict_it"))
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(const_string "no")
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(and (eq_attr "use_literal_pool" "yes")
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(match_test "arm_disable_literal_pool"))
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(const_string "no")
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(eq_attr "arch_enabled" "no")
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(const_string "no")
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@ -245,9 +258,6 @@
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(set_attr "length" "4")
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(set_attr "pool_range" "250")])
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;; Instruction classification types
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(include "types.md")
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; Load scheduling, set from the arm_ld_sched variable
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; initialized by arm_option_override()
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(define_attr "ldsched" "no,yes" (const (symbol_ref "arm_ld_sched")))
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@ -6049,7 +6059,7 @@
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"TARGET_32BIT
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&& reload_completed
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&& (arm_const_double_inline_cost (operands[1])
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<= ((optimize_size || arm_ld_sched) ? 3 : 4))"
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<= arm_max_const_double_inline_cost ())"
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[(const_int 0)]
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"
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arm_split_constant (SET, SImode, curr_insn,
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@ -6312,6 +6322,47 @@
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"
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)
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;; A normal way to do (symbol + offset) requires three instructions at least
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;; (depends on how big the offset is) as below:
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;; movw r0, #:lower16:g
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;; movw r0, #:upper16:g
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;; adds r0, #4
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;;
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;; A better way would be:
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;; movw r0, #:lower16:g+4
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;; movw r0, #:upper16:g+4
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;;
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;; The limitation of this way is that the length of offset should be a 16-bit
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;; signed value, because current assembler only supports REL type relocation for
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;; such case. If the more powerful RELA type is supported in future, we should
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;; update this pattern to go with better way.
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(define_split
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[(set (match_operand:SI 0 "arm_general_register_operand" "")
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(const:SI (plus:SI (match_operand:SI 1 "general_operand" "")
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(match_operand:SI 2 "const_int_operand" ""))))]
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"TARGET_THUMB2
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&& arm_disable_literal_pool
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&& reload_completed
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&& GET_CODE (operands[1]) == SYMBOL_REF"
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[(clobber (const_int 0))]
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"
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int offset = INTVAL (operands[2]);
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if (offset < -0x8000 || offset > 0x7fff)
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{
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arm_emit_movpair (operands[0], operands[1]);
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emit_insn (gen_rtx_SET (SImode, operands[0],
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gen_rtx_PLUS (SImode, operands[0], operands[2])));
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}
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else
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{
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rtx op = gen_rtx_CONST (SImode,
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gen_rtx_PLUS (SImode, operands[1], operands[2]));
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arm_emit_movpair (operands[0], op);
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}
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"
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)
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;; Split symbol_refs at the later stage (after cprop), instead of generating
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;; movt/movw pair directly at expand. Otherwise corresponding high_sum
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;; and lo_sum would be merged back into memory load at cprop. However,
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@ -271,3 +271,7 @@ Enable unaligned word and halfword accesses to packed data.
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mneon-for-64bits
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Target Report RejectNegative Var(use_neon_for_64bits) Init(0)
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Use Neon to perform 64-bits operations rather than core registers.
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mslow-flash-data
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Target Report Var(target_slow_flash_data) Init(0)
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Assume loading data from flash is slower than fetching instructions.
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@ -533,6 +533,7 @@ Objective-C and Objective-C++ Dialects}.
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-mfix-cortex-m3-ldrd @gol
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-munaligned-access @gol
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-mneon-for-64bits @gol
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-mslow-flash-data @gol
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-mrestrict-it}
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@emph{AVR Options}
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@ -12345,6 +12346,13 @@ Enables using Neon to handle scalar 64-bits operations. This is
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disabled by default since the cost of moving data from core registers
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to Neon is high.
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@item -mslow-flash-data
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@opindex mslow-flash-data
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Assume loading data from flash is slower than fetching instruction.
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Therefore literal load is minimized for better performance.
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This option is only supported when compiling for ARMv7 M-profile and
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off by default.
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@item -mrestrict-it
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@opindex mrestrict-it
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Restricts generation of IT blocks to conform to the rules of ARMv8.
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@ -1,3 +1,7 @@
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2013-11-25 Terry Guo <terry.guo@arm.com>
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* gcc.target/arm/thumb2-slow-flash-data.c: New.
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2013-11-23 Uros Bizjak <ubizjak@gmail.com>
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* gcc.dg/float-exact-1.c: Use dg-add-options ieee.
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74
gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data.c
Normal file
74
gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data.c
Normal file
@ -0,0 +1,74 @@
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/* The option -mslow-flash-data is just for performance tuning, it
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doesn't totally disable the use of literal pools. But for below
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simple cases, the use of literal pool should be replaced by
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movw/movt or read-only constant pool. */
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/* { dg-do compile } */
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/* { dg-require-effective-target arm_cortex_m } */
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/* { dg-require-effective-target arm_thumb2_ok } */
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/* { dg-options "-O2 -mthumb -mslow-flash-data" } */
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float sf;
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double df;
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long long l;
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static char *p = "Hello World";
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float
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testsf (float *p)
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{
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if (*p > 1.1234f)
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return 2.1234f;
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else
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return 3.1234f;
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}
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double
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testdf (double *p)
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{
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if (*p > 4.1234)
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return 2.1234;
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else
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return 3.1234;
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}
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long long
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testll (long long *p)
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{
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if (*p > 0x123456789ABCDEFll)
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return 0x111111111ll;
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else
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return 0x222222222ll;
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}
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char *
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testchar ()
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{
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return p + 4;
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}
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int
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foo (int a, int b)
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{
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int i;
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volatile *labelref = &&label1;
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if (a > b)
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{
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while (i < b)
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{
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a += *labelref;
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i += 1;
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}
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goto *labelref;
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}
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else
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b = b + 3;
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a = a * b;
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label1:
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return a + b;
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}
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/* { dg-final { scan-assembler-times "movt" 13 } } */
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/* { dg-final { scan-assembler-times "movt.*LC0\\+4" 1 } } */
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