[arm] Early split zero- and sign-extension
This patch changes the insn patterns for zero- and sign-extend into define_expands that generate the appropriate word operations immediately. * config/arm/arm.md (zero_extend<mode>di2): Convert to define_expand. (extend<mode>di2): Likewise. From-SVN: r277166
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@ -1,3 +1,8 @@
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2019-10-18 Richard Earnshaw <rearnsha@arm.com>
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* config/arm/arm.md (zero_extend<mode>di2): Convert to define_expand.
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(extend<mode>di2): Likewise.
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2019-10-18 Richard Earnshaw <rearnsha@arm.com>
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2019-10-18 Richard Earnshaw <rearnsha@arm.com>
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* config/arm/arm-protos.h (arm_decompose_di_binop): New prototype.
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* config/arm/arm-protos.h (arm_decompose_di_binop): New prototype.
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@ -4196,31 +4196,64 @@
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;; Zero and sign extension instructions.
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;; Zero and sign extension instructions.
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(define_insn "zero_extend<mode>di2"
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(define_expand "zero_extend<mode>di2"
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[(set (match_operand:DI 0 "s_register_operand" "=r,?r")
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[(set (match_operand:DI 0 "s_register_operand" "")
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(zero_extend:DI (match_operand:QHSI 1 "<qhs_zextenddi_op>"
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(zero_extend:DI (match_operand:QHSI 1 "<qhs_zextenddi_op>" "")))]
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"<qhs_zextenddi_cstr>")))]
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"TARGET_32BIT <qhs_zextenddi_cond>"
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"TARGET_32BIT <qhs_zextenddi_cond>"
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"#"
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{
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[(set_attr "length" "4,8")
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rtx res_lo, res_hi, op0_lo, op0_hi;
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(set_attr "arch" "*,*")
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res_lo = gen_lowpart (SImode, operands[0]);
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(set_attr "ce_count" "2")
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res_hi = gen_highpart (SImode, operands[0]);
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(set_attr "predicable" "yes")
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if (can_create_pseudo_p ())
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(set_attr "type" "mov_reg,multiple")]
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{
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op0_lo = <MODE>mode == SImode ? operands[1] : gen_reg_rtx (SImode);
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op0_hi = gen_reg_rtx (SImode);
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}
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else
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{
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op0_lo = <MODE>mode == SImode ? operands[1] : res_lo;
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op0_hi = res_hi;
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}
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if (<MODE>mode != SImode)
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emit_insn (gen_rtx_SET (op0_lo,
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gen_rtx_ZERO_EXTEND (SImode, operands[1])));
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emit_insn (gen_movsi (op0_hi, const0_rtx));
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if (res_lo != op0_lo)
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emit_move_insn (res_lo, op0_lo);
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if (res_hi != op0_hi)
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emit_move_insn (res_hi, op0_hi);
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DONE;
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}
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)
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)
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(define_insn "extend<mode>di2"
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(define_expand "extend<mode>di2"
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[(set (match_operand:DI 0 "s_register_operand" "=r,?r,?r")
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[(set (match_operand:DI 0 "s_register_operand" "")
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(sign_extend:DI (match_operand:QHSI 1 "<qhs_extenddi_op>"
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(sign_extend:DI (match_operand:QHSI 1 "<qhs_extenddi_op>" "")))]
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"<qhs_extenddi_cstr>")))]
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"TARGET_32BIT <qhs_sextenddi_cond>"
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"TARGET_32BIT <qhs_sextenddi_cond>"
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"#"
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{
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[(set_attr "length" "4,8,8")
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rtx res_lo, res_hi, op0_lo, op0_hi;
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(set_attr "ce_count" "2")
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res_lo = gen_lowpart (SImode, operands[0]);
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(set_attr "shift" "1")
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res_hi = gen_highpart (SImode, operands[0]);
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(set_attr "predicable" "yes")
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if (can_create_pseudo_p ())
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(set_attr "arch" "*,a,t")
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{
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(set_attr "type" "mov_reg,multiple,multiple")]
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op0_lo = <MODE>mode == SImode ? operands[1] : gen_reg_rtx (SImode);
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op0_hi = gen_reg_rtx (SImode);
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}
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else
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{
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op0_lo = <MODE>mode == SImode ? operands[1] : res_lo;
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op0_hi = res_hi;
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}
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if (<MODE>mode != SImode)
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emit_insn (gen_rtx_SET (op0_lo,
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gen_rtx_SIGN_EXTEND (SImode, operands[1])));
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emit_insn (gen_ashrsi3 (op0_hi, op0_lo, GEN_INT (31)));
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if (res_lo != op0_lo)
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emit_move_insn (res_lo, op0_lo);
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if (res_hi != op0_hi)
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emit_move_insn (res_hi, op0_hi);
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DONE;
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}
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)
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)
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;; Splits for all extensions to DImode
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;; Splits for all extensions to DImode
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