Add -march=icelake.
gcc/ * config.gcc: Add -march=icelake. * config/i386/driver-i386.c (host_detect_local_cpu): Detect icelake. * config/i386/i386-c.c (ix86_target_macros_internal): Handle icelake. * config/i386/i386.c (processor_costs): Add m_ICELAKE. (PTA_ICELAKE, PTA_AVX512VNNI, PTA_GFNI, PTA_VAES, PTA_AVX512VBMI2, PTA_VPCLMULQDQ, PTA_RDPID, PTA_AVX512BITALG): New. (processor_target_table): Add icelake. (ix86_option_override_internal): Handle new PTAs. (get_builtin_code_for_version): Handle icelake. (M_INTEL_COREI7_ICELAKE): New. (fold_builtin_cpu): Handle icelake. * config/i386/i386.h (TARGET_ICELAKE, PROCESSOR_ICELAKE): New. * doc/invoke.texi: Add -march=icelake. gcc/testsuite/ * gcc.target/i386/funcspec-56.inc: Handle new march. * g++.dg/ext/mv16.C: Ditto. libgcc/ * config/i386/cpuinfo.h (processor_subtypes): Add INTEL_COREI7_ICELAKE. From-SVN: r257331
This commit is contained in:
Julia Koval
Julia Koval
parent
31766e6833
commit
02da1e9cae
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@ -1,3 +1,19 @@
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2018-02-02 Julia Koval <julia.koval@intel.com>
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* config.gcc: Add -march=icelake.
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* config/i386/driver-i386.c (host_detect_local_cpu): Detect icelake.
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* config/i386/i386-c.c (ix86_target_macros_internal): Handle icelake.
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* config/i386/i386.c (processor_costs): Add m_ICELAKE.
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(PTA_ICELAKE, PTA_AVX512VNNI, PTA_GFNI, PTA_VAES, PTA_AVX512VBMI2,
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PTA_VPCLMULQDQ, PTA_RDPID, PTA_AVX512BITALG): New.
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(processor_target_table): Add icelake.
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(ix86_option_override_internal): Handle new PTAs.
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(get_builtin_code_for_version): Handle icelake.
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(M_INTEL_COREI7_ICELAKE): New.
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(fold_builtin_cpu): Handle icelake.
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* config/i386/i386.h (TARGET_ICELAKE, PROCESSOR_ICELAKE): New.
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* doc/invoke.texi: Add -march=icelake.
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2018-02-02 Julia Koval <julia.koval@intel.com>
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* config/i386/i386.c (ix86_option_override_internal): Change flags type
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@ -635,7 +635,7 @@ x86_64_archs="amdfam10 athlon64 athlon64-sse3 barcelona bdver1 bdver2 \
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bdver3 bdver4 znver1 btver1 btver2 k8 k8-sse3 opteron opteron-sse3 nocona \
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core2 corei7 corei7-avx core-avx-i core-avx2 atom slm nehalem westmere \
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sandybridge ivybridge haswell broadwell bonnell silvermont knl knm \
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skylake-avx512 cannonlake x86-64 native"
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skylake-avx512 cannonlake icelake x86-64 native"
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# Additional x86 processors supported by --with-cpu=. Each processor
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# MUST be separated by exactly one space.
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@ -822,8 +822,11 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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if (arch)
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{
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/* This is unknown family 0x6 CPU. */
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/* Assume Ice Lake. */
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if (has_gfni)
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cpu = "icelake";
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/* Assume Cannon Lake. */
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if (has_avx512vbmi)
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else if (has_avx512vbmi)
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cpu = "cannonlake";
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/* Assume Knights Mill. */
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else if (has_avx5124vnniw)
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@ -190,6 +190,10 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
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def_or_undef (parse_in, "__cannonlake");
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def_or_undef (parse_in, "__cannonlake__");
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break;
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case PROCESSOR_ICELAKE:
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def_or_undef (parse_in, "__icelake");
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def_or_undef (parse_in, "__icelake__");
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break;
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/* use PROCESSOR_max to not set/unset the arch macro. */
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case PROCESSOR_max:
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break;
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@ -311,6 +315,9 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
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case PROCESSOR_CANNONLAKE:
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def_or_undef (parse_in, "__tune_cannonlake__");
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break;
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case PROCESSOR_ICELAKE:
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def_or_undef (parse_in, "__tune_icelake__");
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break;
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case PROCESSOR_LAKEMONT:
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def_or_undef (parse_in, "__tune_lakemont__");
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break;
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@ -146,6 +146,7 @@ const struct processor_costs *ix86_cost = NULL;
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#define m_KNM (1U<<PROCESSOR_KNM)
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#define m_SKYLAKE_AVX512 (1U<<PROCESSOR_SKYLAKE_AVX512)
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#define m_CANNONLAKE (1U<<PROCESSOR_CANNONLAKE)
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#define m_ICELAKE (1U<<PROCESSOR_ICELAKE)
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#define m_INTEL (1U<<PROCESSOR_INTEL)
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#define m_GEODE (1U<<PROCESSOR_GEODE)
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@ -858,7 +859,8 @@ static const struct ptt processor_target_table[PROCESSOR_max] =
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{"knl", &slm_cost, 16, 15, 16, 7, 16},
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{"knm", &slm_cost, 16, 15, 16, 7, 16},
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{"skylake-avx512", &skylake_cost, 16, 10, 16, 10, 16},
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{"cannonlake", &core_cost, 16, 10, 16, 10, 16},
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{"cannonlake", &skylake_cost, 16, 10, 16, 10, 16},
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{"icelake", &skylake_cost, 16, 10, 16, 10, 16},
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{"intel", &intel_cost, 16, 15, 16, 7, 16},
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{"geode", &geode_cost, 0, 0, 0, 0, 0},
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{"k6", &k6_cost, 32, 7, 32, 7, 32},
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@ -3446,6 +3448,13 @@ ix86_option_override_internal (bool main_args_p,
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const wide_int_bitmask PTA_AVX5124FMAPS (HOST_WIDE_INT_1U << 61);
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const wide_int_bitmask PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1U << 62);
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const wide_int_bitmask PTA_SGX (HOST_WIDE_INT_1U << 63);
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const wide_int_bitmask PTA_AVX512VNNI (0, HOST_WIDE_INT_1U);
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const wide_int_bitmask PTA_GFNI (0, HOST_WIDE_INT_1U << 1);
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const wide_int_bitmask PTA_VAES (0, HOST_WIDE_INT_1U << 2);
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const wide_int_bitmask PTA_AVX512VBMI2 (0, HOST_WIDE_INT_1U << 3);
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const wide_int_bitmask PTA_VPCLMULQDQ (0, HOST_WIDE_INT_1U << 4);
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const wide_int_bitmask PTA_AVX512BITALG (0, HOST_WIDE_INT_1U << 5);
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const wide_int_bitmask PTA_RDPID (0, HOST_WIDE_INT_1U << 6);
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const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
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| PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
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@ -3467,6 +3476,9 @@ ix86_option_override_internal (bool main_args_p,
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| PTA_CLWB;
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const wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE_AVX512 | PTA_AVX512VBMI
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| PTA_AVX512IFMA | PTA_SHA;
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const wide_int_bitmask PTA_ICELAKE = PTA_CANNONLAKE | PTA_AVX512VNNI
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| PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG
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| PTA_RDPID;
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const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
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| PTA_AVX512F | PTA_AVX512CD;
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const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
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@ -3537,7 +3549,8 @@ ix86_option_override_internal (bool main_args_p,
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{"skylake", PROCESSOR_HASWELL, CPU_HASWELL, PTA_SKYLAKE},
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{"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
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PTA_SKYLAKE_AVX512},
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{"cannonlake", PROCESSOR_HASWELL, CPU_HASWELL, PTA_CANNONLAKE},
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{"cannonlake", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL, PTA_CANNONLAKE},
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{"icelake", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL, PTA_ICELAKE},
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{"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
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{"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
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{"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
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@ -4107,6 +4120,23 @@ ix86_option_override_internal (bool main_args_p,
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if (((processor_alias_table[i].flags & PTA_AVX512IFMA) != 0)
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&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512IFMA))
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opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512IFMA;
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if (((processor_alias_table[i].flags & PTA_AVX512VNNI) != 0)
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&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512VNNI))
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opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VNNI;
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if (((processor_alias_table[i].flags & PTA_GFNI) != 0)
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&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_GFNI))
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opts->x_ix86_isa_flags |= OPTION_MASK_ISA_GFNI;
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if (((processor_alias_table[i].flags & PTA_AVX512VBMI2) != 0)
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&& !(opts->x_ix86_isa_flags_explicit
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& OPTION_MASK_ISA_AVX512VBMI2))
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opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI2;
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if (((processor_alias_table[i].flags & PTA_VPCLMULQDQ) != 0)
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&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_VPCLMULQDQ))
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opts->x_ix86_isa_flags |= OPTION_MASK_ISA_VPCLMULQDQ;
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if (((processor_alias_table[i].flags & PTA_AVX512BITALG) != 0)
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&& !(opts->x_ix86_isa_flags_explicit
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& OPTION_MASK_ISA_AVX512BITALG))
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opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BITALG;
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if (((processor_alias_table[i].flags & PTA_AVX5124VNNIW) != 0)
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&& !(opts->x_ix86_isa_flags2_explicit
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@ -4123,6 +4153,12 @@ ix86_option_override_internal (bool main_args_p,
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if (((processor_alias_table[i].flags & PTA_SGX) != 0)
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&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_SGX))
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opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_SGX;
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if (((processor_alias_table[i].flags & PTA_VAES) != 0)
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&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_VAES))
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opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_VAES;
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if (((processor_alias_table[i].flags & PTA_RDPID) != 0)
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&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_RDPID))
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opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_RDPID;
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if ((processor_alias_table[i].flags
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& (PTA_PREFETCH_SSE | PTA_SSE)) != 0)
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@ -32124,7 +32160,10 @@ get_builtin_code_for_version (tree decl, tree *predicate_list)
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break;
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case PROCESSOR_HASWELL:
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case PROCESSOR_SKYLAKE_AVX512:
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if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_AVX512VBMI)
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if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_GFNI)
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arg_str = "icelake";
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else if (new_target->x_ix86_isa_flags
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& OPTION_MASK_ISA_AVX512VBMI)
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arg_str = "cannonlake";
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else if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_AVX512VL)
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arg_str = "skylake-avx512";
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@ -32849,7 +32888,8 @@ fold_builtin_cpu (tree fndecl, tree *args)
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M_INTEL_COREI7_BROADWELL,
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M_INTEL_COREI7_SKYLAKE,
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M_INTEL_COREI7_SKYLAKE_AVX512,
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M_INTEL_COREI7_CANNONLAKE
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M_INTEL_COREI7_CANNONLAKE,
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M_INTEL_COREI7_ICELAKE
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};
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static struct _arch_names_table
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@ -32874,6 +32914,7 @@ fold_builtin_cpu (tree fndecl, tree *args)
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{"skylake", M_INTEL_COREI7_SKYLAKE},
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{"skylake-avx512", M_INTEL_COREI7_SKYLAKE_AVX512},
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{"cannonlake", M_INTEL_COREI7_CANNONLAKE},
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{"icelake", M_INTEL_COREI7_ICELAKE},
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{"bonnell", M_INTEL_BONNELL},
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{"silvermont", M_INTEL_SILVERMONT},
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{"knl", M_INTEL_KNL},
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@ -383,6 +383,7 @@ extern const struct processor_costs ix86_size_cost;
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#define TARGET_KNM (ix86_tune == PROCESSOR_KNM)
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#define TARGET_SKYLAKE_AVX512 (ix86_tune == PROCESSOR_SKYLAKE_AVX512)
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#define TARGET_CANNONLAKE (ix86_tune == PROCESSOR_CANNONLAKE)
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#define TARGET_ICELAKE (ix86_tune == PROCESSOR_ICELAKE)
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#define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL)
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#define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC)
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#define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
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@ -2263,6 +2264,7 @@ enum processor_type
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PROCESSOR_KNM,
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PROCESSOR_SKYLAKE_AVX512,
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PROCESSOR_CANNONLAKE,
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PROCESSOR_ICELAKE,
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PROCESSOR_INTEL,
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PROCESSOR_GEODE,
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PROCESSOR_K6,
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@ -25606,6 +25606,14 @@ RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
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XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
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AVX512IFMA, SHA, CLWB and UMIP instruction set support.
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@item Icelake
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Intel Icelake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
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SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,
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RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
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XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
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AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ,
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AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES instruction set support.
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@item k6
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AMD K6 CPU with MMX instruction set support.
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@ -1,3 +1,8 @@
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2018-02-02 Julia Koval <julia.koval@intel.com>
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* gcc.target/i386/funcspec-56.inc: Handle new march.
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* g++.dg/ext/mv16.C: Ditto.
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2018-02-02 Georg-Johann Lay <avr@gjlay.de>
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* lib/target-supports.exp
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@ -60,6 +60,10 @@ int __attribute__ ((target("arch=cannonlake"))) foo () {
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return 16;
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}
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int __attribute__ ((target("arch=icelake"))) foo () {
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return 17;
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}
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int main ()
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{
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int val = foo ();
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@ -82,6 +86,8 @@ int main ()
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assert (val == 15);
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else if (__builtin_cpu_is ("cannonlake"))
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assert (val == 16);
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else if (__builtin_cpu_is ("icelake"))
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assert (val == 17);
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else
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assert (val == 0);
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@ -145,6 +145,7 @@ extern void test_arch_knl (void) __attribute__((__target__("arch=knl")));
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extern void test_arch_knm (void) __attribute__((__target__("arch=knm")));
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extern void test_arch_skylake_avx512 (void) __attribute__((__target__("arch=skylake-avx512")));
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extern void test_arch_cannonlake (void) __attribute__((__target__("arch=cannonlake")));
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extern void test_arch_icelake (void) __attribute__((__target__("arch=icelake")));
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extern void test_arch_k8 (void) __attribute__((__target__("arch=k8")));
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extern void test_arch_k8_sse3 (void) __attribute__((__target__("arch=k8-sse3")));
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extern void test_arch_opteron (void) __attribute__((__target__("arch=opteron")));
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@ -1,3 +1,7 @@
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2018-02-02 Julia Koval <julia.koval@intel.com>
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* config/i386/cpuinfo.h (processor_subtypes): Add INTEL_COREI7_ICELAKE.
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2018-01-26 Claudiu Zissulescu <claziss@synopsys.com>
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* config/arc/lib1funcs.S (__udivmodsi4): Use safe version for RF16
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@ -70,6 +70,7 @@ enum processor_subtypes
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INTEL_COREI7_SKYLAKE,
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INTEL_COREI7_SKYLAKE_AVX512,
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INTEL_COREI7_CANNONLAKE,
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INTEL_COREI7_ICELAKE,
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CPU_SUBTYPE_MAX
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};
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Loading…
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