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linux.h: Fix comment formatting. 

* config/mips/linux.h: Fix comment formatting.
	* config/mips/mips.c: Likewise.
	* config/mips/mips.h: Likewise.
	* config/mips/mips.md: Likewise.
	* config/mips/netbsd.h: Likewise.
	* config/mips/windiss.h: Likewise.

From-SVN: r75361
This commit is contained in:
Kazu Hirata 2004-01-03 18:33:14 +00:00 committed by Kazu Hirata
parent 78a816a6ec
commit 031a26c5b7
7 changed files with 49 additions and 40 deletions
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9
gcc/ChangeLog
View File

@ -1,3 +1,12 @@
2004-01-03 Kazu Hirata <kazu@cs.umass.edu>
* config/mips/linux.h: Fix comment formatting.
* config/mips/mips.c: Likewise.
* config/mips/mips.h: Likewise.
* config/mips/mips.md: Likewise.
* config/mips/netbsd.h: Likewise.
* config/mips/windiss.h: Likewise.
2004-01-02 Richard Henderson <rth@redhat.com>
* config/i386/i386.md (fp constant pool splitter): Reorg suppression

8
gcc/config/mips/mips.c
View File

@ -2352,7 +2352,7 @@ mips_rtx_costs (rtx x, int code, int outer_code, int *total)
*total = COSTS_N_INSNS (36);
return true;
}
/* FALLTHRU */
/* Fall through. */
case UDIV:
case UMOD:
@ -2822,7 +2822,7 @@ gen_int_relational (enum rtx_code test_code, rtx result, rtx cmp0,
return 0;
}
/* allocate a pseudo to calculate the value in. */
/* Allocate a pseudo to calculate the value in. */
result = gen_reg_rtx (mode);
}
@ -5065,7 +5065,7 @@ mips_conditional_register_usage (void)
for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
call_really_used_regs[regno] = call_used_regs[regno] = 1;
}
/* odd registers from fp21 to fp31 are now caller saved. */
/* Odd registers from fp21 to fp31 are now caller saved. */
if (mips_abi == ABI_N32)
{
int regno;
@ -8815,7 +8815,7 @@ mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
return 5;
} /* COP_REG_CLASS_P (from) */
/* fallthru */
/* Fall through. */
return 12;
}

50
gcc/config/mips/mips.md
View File

@ -3841,7 +3841,7 @@ dsrl\t%3,%3,1\n\
real_2expN (&offset, 31);
if (reg1) /* turn off complaints about unreached code */
if (reg1) /* Turn off complaints about unreached code. */
{
emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
do_pending_stack_adjust ();
@ -3864,7 +3864,7 @@ dsrl\t%3,%3,1\n\
emit_label (label2);
/* allow REG_NOTES to be set on last insn (labels don't have enough
/* Allow REG_NOTES to be set on last insn (labels don't have enough
fields, and can't be used for REG_NOTES anyway). */
emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
DONE;
@ -3907,7 +3907,7 @@ dsrl\t%3,%3,1\n\
emit_label (label2);
/* allow REG_NOTES to be set on last insn (labels don't have enough
/* Allow REG_NOTES to be set on last insn (labels don't have enough
fields, and can't be used for REG_NOTES anyway). */
emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
DONE;
@ -3949,7 +3949,7 @@ dsrl\t%3,%3,1\n\
emit_label (label2);
/* allow REG_NOTES to be set on last insn (labels don't have enough
/* Allow REG_NOTES to be set on last insn (labels don't have enough
fields, and can't be used for REG_NOTES anyway). */
emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
DONE;
@ -3991,7 +3991,7 @@ dsrl\t%3,%3,1\n\
emit_label (label2);
/* allow REG_NOTES to be set on last insn (labels don't have enough
/* Allow REG_NOTES to be set on last insn (labels don't have enough
fields, and can't be used for REG_NOTES anyway). */
emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
DONE;
@ -6868,7 +6868,7 @@ srl\t%M0,%M1,%2\n\
if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
FAIL;
/* set up operands from compare. */
/* Set up operands from compare. */
operands[1] = branch_cmp[0];
operands[2] = branch_cmp[1];
@ -6881,7 +6881,7 @@ srl\t%M0,%M1,%2\n\
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
operands[2] = force_reg (SImode, operands[2]);
/* fall through and generate default code */
/* Fall through and generate default code. */
})
@ -6985,7 +6985,7 @@ srl\t%M0,%M1,%2\n\
if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
FAIL;
/* set up operands from compare. */
/* Set up operands from compare. */
operands[1] = branch_cmp[0];
operands[2] = branch_cmp[1];
@ -6998,7 +6998,7 @@ srl\t%M0,%M1,%2\n\
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
operands[2] = force_reg (SImode, operands[2]);
/* fall through and generate default code */
/* Fall through and generate default code. */
})
(define_insn "sne_si_zero"
@ -7081,7 +7081,7 @@ srl\t%M0,%M1,%2\n\
if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
FAIL;
/* set up operands from compare. */
/* Set up operands from compare. */
operands[1] = branch_cmp[0];
operands[2] = branch_cmp[1];
@ -7094,7 +7094,7 @@ srl\t%M0,%M1,%2\n\
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
operands[2] = force_reg (SImode, operands[2]);
/* fall through and generate default code */
/* Fall through and generate default code. */
})
(define_insn "sgt_si"
@ -7142,7 +7142,7 @@ srl\t%M0,%M1,%2\n\
if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
FAIL;
/* set up operands from compare. */
/* Set up operands from compare. */
operands[1] = branch_cmp[0];
operands[2] = branch_cmp[1];
@ -7152,7 +7152,7 @@ srl\t%M0,%M1,%2\n\
DONE;
}
/* fall through and generate default code */
/* Fall through and generate default code. */
})
(define_insn "sge_si"
@ -7211,7 +7211,7 @@ srl\t%M0,%M1,%2\n\
if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
FAIL;
/* set up operands from compare. */
/* Set up operands from compare. */
operands[1] = branch_cmp[0];
operands[2] = branch_cmp[1];
@ -7221,7 +7221,7 @@ srl\t%M0,%M1,%2\n\
DONE;
}
/* fall through and generate default code */
/* Fall through and generate default code. */
})
(define_insn "slt_si"
@ -7279,7 +7279,7 @@ srl\t%M0,%M1,%2\n\
if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
FAIL;
/* set up operands from compare. */
/* Set up operands from compare. */
operands[1] = branch_cmp[0];
operands[2] = branch_cmp[1];
@ -7292,7 +7292,7 @@ srl\t%M0,%M1,%2\n\
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767)
operands[2] = force_reg (SImode, operands[2]);
/* fall through and generate default code */
/* Fall through and generate default code. */
})
(define_insn "sle_si_const"
@ -7405,7 +7405,7 @@ srl\t%M0,%M1,%2\n\
if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
FAIL;
/* set up operands from compare. */
/* Set up operands from compare. */
operands[1] = branch_cmp[0];
operands[2] = branch_cmp[1];
@ -7418,7 +7418,7 @@ srl\t%M0,%M1,%2\n\
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
operands[2] = force_reg (SImode, operands[2]);
/* fall through and generate default code */
/* Fall through and generate default code. */
})
(define_insn "sgtu_si"
@ -7466,7 +7466,7 @@ srl\t%M0,%M1,%2\n\
if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
FAIL;
/* set up operands from compare. */
/* Set up operands from compare. */
operands[1] = branch_cmp[0];
operands[2] = branch_cmp[1];
@ -7476,7 +7476,7 @@ srl\t%M0,%M1,%2\n\
DONE;
}
/* fall through and generate default code */
/* Fall through and generate default code. */
})
(define_insn "sgeu_si"
@ -7535,7 +7535,7 @@ srl\t%M0,%M1,%2\n\
if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
FAIL;
/* set up operands from compare. */
/* Set up operands from compare. */
operands[1] = branch_cmp[0];
operands[2] = branch_cmp[1];
@ -7545,7 +7545,7 @@ srl\t%M0,%M1,%2\n\
DONE;
}
/* fall through and generate default code */
/* Fall through and generate default code. */
})
(define_insn "sltu_si"
@ -7603,7 +7603,7 @@ srl\t%M0,%M1,%2\n\
if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
FAIL;
/* set up operands from compare. */
/* Set up operands from compare. */
operands[1] = branch_cmp[0];
operands[2] = branch_cmp[1];
@ -7616,7 +7616,7 @@ srl\t%M0,%M1,%2\n\
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767)
operands[2] = force_reg (SImode, operands[2]);
/* fall through and generate default code */
/* Fall through and generate default code. */
})
(define_insn "sleu_si_const"