linux.h: Fix comment formatting.
* config/mips/linux.h: Fix comment formatting. * config/mips/mips.c: Likewise. * config/mips/mips.h: Likewise. * config/mips/mips.md: Likewise. * config/mips/netbsd.h: Likewise. * config/mips/windiss.h: Likewise. From-SVN: r75361
This commit is contained in:
parent
78a816a6ec
commit
031a26c5b7
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@ -1,3 +1,12 @@
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2004-01-03 Kazu Hirata <kazu@cs.umass.edu>
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* config/mips/linux.h: Fix comment formatting.
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* config/mips/mips.c: Likewise.
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* config/mips/mips.h: Likewise.
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* config/mips/mips.md: Likewise.
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* config/mips/netbsd.h: Likewise.
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* config/mips/windiss.h: Likewise.
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2004-01-02 Richard Henderson <rth@redhat.com>
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* config/i386/i386.md (fp constant pool splitter): Reorg suppression
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@ -198,7 +198,7 @@ Boston, MA 02111-1307, USA. */
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/* The third parameter to the signal handler points to something with
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* this structure defined in asm/ucontext.h, but the name clashes with
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* struct ucontext from sys/ucontext.h so this private copy is used. */
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* struct ucontext from sys/ucontext.h so this private copy is used. */
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typedef struct _sig_ucontext {
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unsigned long uc_flags;
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struct _sig_ucontext *uc_link;
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@ -2352,7 +2352,7 @@ mips_rtx_costs (rtx x, int code, int outer_code, int *total)
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*total = COSTS_N_INSNS (36);
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return true;
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}
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/* FALLTHRU */
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/* Fall through. */
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case UDIV:
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case UMOD:
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@ -2822,7 +2822,7 @@ gen_int_relational (enum rtx_code test_code, rtx result, rtx cmp0,
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return 0;
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}
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/* allocate a pseudo to calculate the value in. */
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/* Allocate a pseudo to calculate the value in. */
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result = gen_reg_rtx (mode);
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}
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@ -3854,7 +3854,7 @@ mips_setup_incoming_varargs (const CUMULATIVE_ARGS *cum,
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if (fp_saved > 0)
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{
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/* We can't use move_block_from_reg, because it will use
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the wrong mode. */
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the wrong mode. */
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enum machine_mode mode;
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int off, i;
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@ -4643,7 +4643,7 @@ override_options (void)
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if (TARGET_SGI_O32_AS)
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{
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/* They don't recognize `.[248]byte'. */
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/* They don't recognize `.[248]byte'. */
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targetm.asm_out.unaligned_op.hi = "\t.align 0\n\t.half\t";
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targetm.asm_out.unaligned_op.si = "\t.align 0\n\t.word\t";
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/* The IRIX 6 O32 assembler gives an error for `align 0; .dword',
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@ -5065,7 +5065,7 @@ mips_conditional_register_usage (void)
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for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
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call_really_used_regs[regno] = call_used_regs[regno] = 1;
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}
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/* odd registers from fp21 to fp31 are now caller saved. */
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/* Odd registers from fp21 to fp31 are now caller saved. */
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if (mips_abi == ABI_N32)
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{
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int regno;
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@ -5505,7 +5505,7 @@ print_operand_reloc (FILE *file, rtx op, const char **relocs)
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fputc (')', file);
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}
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/* Output address operand X to FILE. */
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/* Output address operand X to FILE. */
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void
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print_operand_address (FILE *file, rtx x)
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@ -7415,7 +7415,7 @@ mips_secondary_reload_class (enum reg_class class,
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{
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if (GET_CODE (x) == MEM)
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{
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/* In this case we can use lwc1, swc1, ldc1 or sdc1. */
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/* In this case we can use lwc1, swc1, ldc1 or sdc1. */
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return NO_REGS;
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}
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else if (CONSTANT_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
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@ -8807,7 +8807,7 @@ mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
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else
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return 6;
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}
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} /* from == HI_REG, etc. */
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} /* from == HI_REG, etc. */
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else if (from == ST_REGS && GR_REG_CLASS_P (to))
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return 4;
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else if (COP_REG_CLASS_P (from))
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@ -8815,7 +8815,7 @@ mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
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return 5;
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} /* COP_REG_CLASS_P (from) */
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/* fallthru */
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/* Fall through. */
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return 12;
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}
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@ -169,7 +169,7 @@ extern const struct mips_cpu_info *mips_tune_info;
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#define MASK_UNINIT_CONST_IN_RODATA \
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0x00800000 /* Store uninitialized
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consts in rodata */
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#define MASK_FIX_SB1 0x01000000 /* Work around SB-1 errata. */
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#define MASK_FIX_SB1 0x01000000 /* Work around SB-1 errata. */
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/* Debug switches, not documented */
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#define MASK_DEBUG 0 /* unused */
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@ -2661,7 +2661,7 @@ typedef struct mips_args {
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/* Specify the machine mode that this machine uses
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for the index in the tablejump instruction.
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??? Using HImode in mips16 mode can cause overflow. */
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??? Using HImode in mips16 mode can cause overflow. */
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#define CASE_VECTOR_MODE \
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(TARGET_MIPS16 ? HImode : ptr_mode)
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@ -2735,7 +2735,7 @@ typedef struct mips_args {
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that the constraints of the insn are met. Setting a cost of
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other than 2 will allow reload to verify that the constraints are
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met. You should do this if the `movM' pattern's constraints do
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not allow such copying. */
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not allow such copying. */
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#define REGISTER_MOVE_COST(MODE, FROM, TO) \
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mips_register_move_cost (MODE, FROM, TO)
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@ -3841,7 +3841,7 @@ dsrl\t%3,%3,1\n\
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real_2expN (&offset, 31);
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if (reg1) /* turn off complaints about unreached code */
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if (reg1) /* Turn off complaints about unreached code. */
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{
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emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
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do_pending_stack_adjust ();
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@ -3864,7 +3864,7 @@ dsrl\t%3,%3,1\n\
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emit_label (label2);
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/* allow REG_NOTES to be set on last insn (labels don't have enough
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/* Allow REG_NOTES to be set on last insn (labels don't have enough
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fields, and can't be used for REG_NOTES anyway). */
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emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
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DONE;
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@ -3907,7 +3907,7 @@ dsrl\t%3,%3,1\n\
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emit_label (label2);
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/* allow REG_NOTES to be set on last insn (labels don't have enough
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/* Allow REG_NOTES to be set on last insn (labels don't have enough
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fields, and can't be used for REG_NOTES anyway). */
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emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
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DONE;
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emit_label (label2);
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/* allow REG_NOTES to be set on last insn (labels don't have enough
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/* Allow REG_NOTES to be set on last insn (labels don't have enough
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fields, and can't be used for REG_NOTES anyway). */
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emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
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DONE;
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@ -3991,7 +3991,7 @@ dsrl\t%3,%3,1\n\
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emit_label (label2);
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/* allow REG_NOTES to be set on last insn (labels don't have enough
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/* Allow REG_NOTES to be set on last insn (labels don't have enough
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fields, and can't be used for REG_NOTES anyway). */
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emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
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DONE;
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@ -6868,7 +6868,7 @@ srl\t%M0,%M1,%2\n\
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if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
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FAIL;
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/* set up operands from compare. */
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/* Set up operands from compare. */
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operands[1] = branch_cmp[0];
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operands[2] = branch_cmp[1];
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@ -6881,7 +6881,7 @@ srl\t%M0,%M1,%2\n\
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if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
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operands[2] = force_reg (SImode, operands[2]);
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/* fall through and generate default code */
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/* Fall through and generate default code. */
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})
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@ -6985,7 +6985,7 @@ srl\t%M0,%M1,%2\n\
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if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
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FAIL;
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/* set up operands from compare. */
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/* Set up operands from compare. */
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operands[1] = branch_cmp[0];
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operands[2] = branch_cmp[1];
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@ -6998,7 +6998,7 @@ srl\t%M0,%M1,%2\n\
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if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
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operands[2] = force_reg (SImode, operands[2]);
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/* fall through and generate default code */
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/* Fall through and generate default code. */
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})
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(define_insn "sne_si_zero"
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if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
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FAIL;
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/* set up operands from compare. */
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/* Set up operands from compare. */
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operands[1] = branch_cmp[0];
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operands[2] = branch_cmp[1];
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if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
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operands[2] = force_reg (SImode, operands[2]);
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/* fall through and generate default code */
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/* Fall through and generate default code. */
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})
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(define_insn "sgt_si"
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if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
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FAIL;
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/* set up operands from compare. */
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/* Set up operands from compare. */
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operands[1] = branch_cmp[0];
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operands[2] = branch_cmp[1];
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DONE;
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}
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/* fall through and generate default code */
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/* Fall through and generate default code. */
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})
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(define_insn "sge_si"
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if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
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FAIL;
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/* set up operands from compare. */
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/* Set up operands from compare. */
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operands[1] = branch_cmp[0];
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operands[2] = branch_cmp[1];
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DONE;
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}
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/* fall through and generate default code */
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/* Fall through and generate default code. */
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})
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(define_insn "slt_si"
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if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
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FAIL;
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/* set up operands from compare. */
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/* Set up operands from compare. */
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operands[1] = branch_cmp[0];
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operands[2] = branch_cmp[1];
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if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767)
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operands[2] = force_reg (SImode, operands[2]);
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/* fall through and generate default code */
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/* Fall through and generate default code. */
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})
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(define_insn "sle_si_const"
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if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
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FAIL;
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/* set up operands from compare. */
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/* Set up operands from compare. */
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operands[1] = branch_cmp[0];
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operands[2] = branch_cmp[1];
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@ -7418,7 +7418,7 @@ srl\t%M0,%M1,%2\n\
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if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
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operands[2] = force_reg (SImode, operands[2]);
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/* fall through and generate default code */
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/* Fall through and generate default code. */
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})
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(define_insn "sgtu_si"
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if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
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FAIL;
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/* set up operands from compare. */
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/* Set up operands from compare. */
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operands[1] = branch_cmp[0];
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operands[2] = branch_cmp[1];
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DONE;
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}
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/* fall through and generate default code */
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/* Fall through and generate default code. */
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})
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(define_insn "sgeu_si"
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if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
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FAIL;
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/* set up operands from compare. */
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/* Set up operands from compare. */
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operands[1] = branch_cmp[0];
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operands[2] = branch_cmp[1];
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@ -7545,7 +7545,7 @@ srl\t%M0,%M1,%2\n\
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DONE;
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}
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/* fall through and generate default code */
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/* Fall through and generate default code. */
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})
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(define_insn "sltu_si"
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@ -7603,7 +7603,7 @@ srl\t%M0,%M1,%2\n\
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if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
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FAIL;
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/* set up operands from compare. */
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/* Set up operands from compare. */
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operands[1] = branch_cmp[0];
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operands[2] = branch_cmp[1];
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@ -7616,7 +7616,7 @@ srl\t%M0,%M1,%2\n\
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if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767)
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operands[2] = force_reg (SImode, operands[2]);
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/* fall through and generate default code */
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/* Fall through and generate default code. */
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})
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(define_insn "sleu_si_const"
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@ -20,7 +20,7 @@ the Free Software Foundation, 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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/* Define default target values. */
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/* Define default target values. */
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#undef MACHINE_TYPE
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#if TARGET_ENDIAN_DEFAULT != 0
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@ -89,7 +89,7 @@ Boston, MA 02111-1307, USA. */
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#undef ENDFILE_SPEC
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#define ENDFILE_SPEC "crtend.o%s"
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/* We have no shared libraries. These two shouldn't be necessary. */
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/* We have no shared libraries. These two shouldn't be necessary. */
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#undef LINK_SHLIB_SPEC
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#define LINK_SHLIB_SPEC ""
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#undef LINK_EH_SPEC
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