[ARC] Improve code gen when compiling for size
When optimizing for size, try to avoid using long immediate by
employing alternative instructions.
gcc/
xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc-protos.h (arc_check_ior_const): Declare.
(arc_split_ior): Likewise.
(arc_check_mov_const): Likewise.
(arc_split_mov_const): Likewise.
* config/arc/arc.c (arc_print_operand): Fix 'z' letter.
(arc_rtx_costs): Replace check Crr with Cax constraint.
(prepare_move_operands): Cleanup, remove unused code.
(arc_split_ior): New function.
(arc_check_ior_const): Likewise.
(arc_split_mov_const): Likewise.
(arc_check_mov_const): Likewise.
* config/arc/arc.md (movsi_insn): Restructure it, and convert it
in define_insn_and_split pattern.
(iorsi3): Likewise.
(mulsi3_v2): Add new matching variant.
(andsi3_i): Cleanup pattern.
(rotrsi3_cnt1): Update pattern.
(rotrsi3_cnt8): New pattern.
(ashlsi2_cnt8): Likewise.
(ashlsi2_cnt16): Likewise.
* config/arc/constraints.md (C0p): Update constraint.
(Crr): Remove it.
(C0x): New pattern.
(Cax): New pattern.
testsuite/
xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com>
* gcc.target/arc/and-cnst-size.c: New test.
* gcc.target/arc/mov-cnst-size.c: Likewise.
* gcc.target/arc/or-cnst-size.c: Likewise.
* gcc.target/arc/store-merge-1.c: Update test.
* gcc.target/arc/arc700-stld-hazard.c: Likewise.
* gcc.target/arc/cmem-1.c: Likewise.
* gcc.target/arc/cmem-2.c: Likewise.
* gcc.target/arc/cmem-3.c: Likewise.
* gcc.target/arc/cmem-4.c: Likewise.
* gcc.target/arc/cmem-5.c: Likewise.
* gcc.target/arc/cmem-6.c: Likewise.
* gcc.target/arc/loop-4.c: Likewise.
* gcc.target/arc/movh_cl-1.c: Likewise.
* gcc.target/arc/sdata-3.c: Likewise.
From-SVN: r272112
This commit is contained in:
Claudiu Zissulescu
Claudiu Zissulescu
parent
07b8d0afe8
commit
03301dcc84
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@ -1,3 +1,30 @@
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2019-06-10 Claudiu Zissulescu <claziss@synopsys.com>
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* config/arc/arc-protos.h (arc_check_ior_const): Declare.
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(arc_split_ior): Likewise.
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(arc_check_mov_const): Likewise.
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(arc_split_mov_const): Likewise.
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* config/arc/arc.c (arc_print_operand): Fix 'z' letter.
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(arc_rtx_costs): Replace check Crr with Cax constraint.
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(prepare_move_operands): Cleanup, remove unused code.
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(arc_split_ior): New function.
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(arc_check_ior_const): Likewise.
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(arc_split_mov_const): Likewise.
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(arc_check_mov_const): Likewise.
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* config/arc/arc.md (movsi_insn): Restructure it, and convert it
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in define_insn_and_split pattern.
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(iorsi3): Likewise.
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(mulsi3_v2): Add new matching variant.
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(andsi3_i): Cleanup pattern.
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(rotrsi3_cnt1): Update pattern.
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(rotrsi3_cnt8): New pattern.
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(ashlsi2_cnt8): Likewise.
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(ashlsi2_cnt16): Likewise.
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* config/arc/constraints.md (C0p): Update constraint.
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(Crr): Remove it.
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(C0x): New pattern.
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(Cax): New pattern.
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2019-06-10 Martin Liska <mliska@suse.cz>
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* ipa-icf.c (sem_item_optimizer::parse_nonsingleton_classes):
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@ -48,6 +48,10 @@ extern bool arc_is_uncached_mem_p (rtx);
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extern bool gen_operands_ldd_std (rtx *operands, bool load, bool commute);
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extern bool arc_check_multi (rtx, bool);
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extern void arc_adjust_reg_alloc_order (void);
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extern bool arc_check_ior_const (HOST_WIDE_INT );
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extern void arc_split_ior (rtx *);
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extern bool arc_check_mov_const (HOST_WIDE_INT );
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extern bool arc_split_mov_const (rtx *);
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#endif /* RTX_CODE */
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extern unsigned int arc_compute_frame_size (int);
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@ -4223,7 +4223,7 @@ arc_print_operand (FILE *file, rtx x, int code)
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case 'z':
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if (GET_CODE (x) == CONST_INT)
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fprintf (file, "%d",exact_log2(INTVAL (x)) );
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fprintf (file, "%d",exact_log2 (INTVAL (x) & 0xffffffff));
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else
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output_operand_lossage ("invalid operand to %%z code");
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@ -5588,9 +5588,6 @@ arc_rtx_costs (rtx x, machine_mode mode, int outer_code,
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if (satisfies_constraint_C0p (x)) /* bxor */
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nolimm = fast = condexec = true;
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break;
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case SET:
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if (satisfies_constraint_Crr (x)) /* ror b,u6 */
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nolimm = true;
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default:
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break;
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}
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@ -9079,31 +9076,6 @@ prepare_move_operands (rtx *operands, machine_mode mode)
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MEM_COPY_ATTRIBUTES (pat, operands[0]);
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operands[0] = pat;
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}
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if (!cse_not_expected)
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{
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rtx pat = XEXP (operands[0], 0);
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pat = arc_legitimize_address_0 (pat, pat, mode);
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if (pat)
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{
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pat = change_address (operands[0], mode, pat);
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MEM_COPY_ATTRIBUTES (pat, operands[0]);
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operands[0] = pat;
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}
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}
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}
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if (MEM_P (operands[1]) && !cse_not_expected)
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{
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rtx pat = XEXP (operands[1], 0);
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pat = arc_legitimize_address_0 (pat, pat, mode);
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if (pat)
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{
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pat = change_address (operands[1], mode, pat);
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MEM_COPY_ATTRIBUTES (pat, operands[1]);
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operands[1] = pat;
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}
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}
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return false;
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@ -11448,6 +11420,198 @@ arc_memory_move_cost (machine_mode mode,
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return (2 * GET_MODE_SIZE (mode));
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}
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/* Split an OR instruction into multiple BSET/OR instructions in a
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attempt to avoid long immediate constants. The next strategies are
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employed when destination is 'q' reg.
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1. if there are up to three bits set in the mask, a succession of
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three bset instruction will be emitted:
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OR rA, rB, mask ->
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BSET(_S) rA,rB,mask1/BSET_S rA,rA,mask2/BSET_S rA,rA,mask3
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2. if the lower 6 bits of the mask is set and there is only one
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bit set in the upper remaining bits then we will emit one bset and
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one OR instruction:
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OR rA, rB, mask -> OR rA,rB,mask1/BSET_S rA,mask2
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3. otherwise an OR with limm will be emmitted. */
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void
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arc_split_ior (rtx *operands)
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{
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unsigned HOST_WIDE_INT mask, maskx;
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rtx op1 = operands[1];
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gcc_assert (CONST_INT_P (operands[2]));
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mask = INTVAL (operands[2]) & 0xffffffff;
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if (__builtin_popcount (mask) > 3 || (mask & 0x3f))
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{
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maskx = mask & 0x3f;
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emit_insn (gen_rtx_SET (operands[0],
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gen_rtx_IOR (SImode, op1, GEN_INT (maskx))));
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op1 = operands[0];
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mask &= ~maskx;
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}
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switch (__builtin_popcount (mask))
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{
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case 3:
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maskx = 1 << (__builtin_ffs (mask) - 1);
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emit_insn (gen_rtx_SET (operands[0],
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gen_rtx_IOR (SImode, op1, GEN_INT (maskx))));
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mask &= ~maskx;
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op1 = operands[0];
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/* FALLTHRU */
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case 2:
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maskx = 1 << (__builtin_ffs (mask) - 1);
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emit_insn (gen_rtx_SET (operands[0],
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gen_rtx_IOR (SImode, op1, GEN_INT (maskx))));
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mask &= ~maskx;
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op1 = operands[0];
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/* FALLTHRU */
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case 1:
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maskx = 1 << (__builtin_ffs (mask) - 1);
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emit_insn (gen_rtx_SET (operands[0],
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gen_rtx_IOR (SImode, op1, GEN_INT (maskx))));
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break;
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default:
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break;
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}
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}
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/* Helper to check C0x constraint. */
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bool
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arc_check_ior_const (HOST_WIDE_INT ival)
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{
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unsigned int mask = (unsigned int) (ival & 0xffffffff);
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if (__builtin_popcount (mask) <= 3)
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return true;
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if (__builtin_popcount (mask & ~0x3f) <= 1)
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return true;
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return false;
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}
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/* Split a mov with long immediate instruction into smaller, size
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friendly instructions. */
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bool
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arc_split_mov_const (rtx *operands)
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{
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unsigned HOST_WIDE_INT ival;
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HOST_WIDE_INT shimm;
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machine_mode mode = GET_MODE (operands[0]);
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/* Manage a constant. */
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gcc_assert (CONST_INT_P (operands[1]));
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ival = INTVAL (operands[1]) & 0xffffffff;
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if (SIGNED_INT12 (ival))
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return false;
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/* 1. Check if we can just rotate limm by 8 but using ROR8. */
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if (TARGET_BARREL_SHIFTER && TARGET_V2
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&& ((ival & ~0x3f000000) == 0))
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{
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shimm = (ival >> 24) & 0x3f;
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emit_insn (gen_rtx_SET (operands[0],
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gen_rtx_ROTATERT (mode, GEN_INT (shimm),
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GEN_INT (8))));
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return true;
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}
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/* 2. Check if we can just shift by 8 to fit into the u6 of LSL8. */
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if (TARGET_BARREL_SHIFTER && TARGET_V2
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&& ((ival & ~0x3f00) == 0))
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{
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shimm = (ival >> 8) & 0x3f;
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emit_insn (gen_rtx_SET (operands[0],
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gen_rtx_ASHIFT (mode, GEN_INT (shimm),
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GEN_INT (8))));
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return true;
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}
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/* 3. Check if we can just shift by 16 to fit into the u6 of LSL16. */
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if (TARGET_BARREL_SHIFTER && TARGET_V2
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&& ((ival & ~0x3f0000) == 0))
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{
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shimm = (ival >> 16) & 0x3f;
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emit_insn (gen_rtx_SET (operands[0],
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gen_rtx_ASHIFT (mode, GEN_INT (shimm),
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GEN_INT (16))));
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return true;
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}
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/* 4. Check if we can do something like mov_s h,u8 / asl_s ra,h,#nb. */
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if (((ival >> (__builtin_ffs (ival) - 1)) & 0xffffff00) == 0
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&& TARGET_BARREL_SHIFTER)
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{
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HOST_WIDE_INT shift = __builtin_ffs (ival);
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shimm = (ival >> (shift - 1)) & 0xff;
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emit_insn (gen_rtx_SET (operands[0], GEN_INT (shimm)));
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emit_insn (gen_rtx_SET (operands[0],
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gen_rtx_ASHIFT (mode, operands[0],
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GEN_INT (shift - 1))));
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return true;
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}
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/* 5. Check if we can just rotate the limm, useful when no barrel
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shifter is present. */
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if ((ival & ~0x8000001f) == 0)
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{
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shimm = (ival * 2 + 1) & 0x3f;
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emit_insn (gen_rtx_SET (operands[0],
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gen_rtx_ROTATERT (mode, GEN_INT (shimm),
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const1_rtx)));
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return true;
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}
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/* 6. Check if we can do something with bmask. */
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if (IS_POWEROF2_P (ival + 1))
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{
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emit_insn (gen_rtx_SET (operands[0], constm1_rtx));
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emit_insn (gen_rtx_SET (operands[0],
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gen_rtx_AND (mode, operands[0],
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GEN_INT (ival))));
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return true;
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}
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return false;
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}
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/* Helper to check Cax constraint. */
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bool
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arc_check_mov_const (HOST_WIDE_INT ival)
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{
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ival = ival & 0xffffffff;
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if ((ival & ~0x8000001f) == 0)
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return true;
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if (IS_POWEROF2_P (ival + 1))
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return true;
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/* The next rules requires a barrel shifter. */
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if (!TARGET_BARREL_SHIFTER)
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return false;
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if (((ival >> (__builtin_ffs (ival) - 1)) & 0xffffff00) == 0)
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return true;
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if ((ival & ~0x3f00) == 0)
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return true;
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if ((ival & ~0x3f0000) == 0)
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return true;
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if ((ival & ~0x3f000000) == 0)
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return true;
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return false;
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}
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#undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
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#define TARGET_USE_ANCHORS_FOR_SYMBOL_P arc_use_anchors_for_symbol_p
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@ -749,66 +749,63 @@ core_3, archs4x, archs4xd, archs4xd_slow"
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; In order to allow the ccfsm machinery to do its work, the leading compact
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; alternatives say 'canuse' - there is another alternative that will match
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; when the condition codes are used.
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; Rcq won't match if the condition is actually used; to avoid a spurious match
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; via q, q is inactivated as constraint there.
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; Likewise, the length of an alternative that might be shifted to conditional
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; The length of an alternative that might be shifted to conditional
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; execution must reflect this, lest out-of-range branches are created.
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; the iscompact attribute allows the epilogue expander to know for which
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; insns it should lengthen the return insn.
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; N.B. operand 1 of alternative 7 expands into pcl,symbol@gotpc .
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(define_insn "*movsi_insn" ; 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
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[(set (match_operand:SI 0 "move_dest_operand" "=Rcq,Rcq#q, w,Rcq#q, h,wl, w, w, w, w, w,???w, ?w, w,Rcq#q, h, wl,Rcq, S, Us<,RcqRck,!*x, r,!*Rsd,!*Rcd,r,Ucm, Usd,m,???m, m,VUsc")
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(match_operand:SI 1 "move_src_operand" " cL, cP,Rcq#q, P,hCm1,cL, I,Crr,Clo,Chi,Cbi,?Rac,Cpc,Clb, ?Cal,Cal,?Cal,Uts,Rcq,RcqRck, Us>,Usd,Ucm, Usd, Ucd,m, w,!*Rzd,c,?Rac,Cm3, C32"))]
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(define_insn_and_split "*movsi_insn" ; 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
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[(set (match_operand:SI 0 "move_dest_operand" "=q, q,r,q, h,rl, r, r, r, r, ?r, r, q, h, rl, q, S, Us<,RcqRck,!*x, r,!*Rsd,!*Rcd,r,Ucm, Usd,m, m,VUsc")
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(match_operand:SI 1 "move_src_operand" "rL,rP,q,P,hCm1,rL, I,Clo,Chi,Cbi,Cpc,Clb,Cax,Cal,Cal,Uts,Rcq,RcqRck, Us>,Usd,Ucm, Usd, Ucd,m, r,!*Rzd,r,Cm3, C32"))]
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"register_operand (operands[0], SImode)
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|| register_operand (operands[1], SImode)
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|| (CONSTANT_P (operands[1])
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/* Don't use a LIMM that we could load with a single insn - we loose
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delay-slot filling opportunities. */
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&& !satisfies_constraint_I (operands[1])
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&& (!satisfies_constraint_I (operands[1]) || !optimize_size)
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&& satisfies_constraint_Usc (operands[0]))
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|| (satisfies_constraint_Cm3 (operands[1])
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&& memory_operand (operands[0], SImode))"
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"@
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mov%? %0,%1%& ;0
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mov%? %0,%1%& ;1
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mov%? %0,%1%& ;2
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mov%? %0,%1%& ;3
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mov%? %0,%1%& ;4
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mov%? %0,%1 ;5
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mov%? %0,%1 ;6
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ror %0,((%1*2+1) & 0x3f) ;7
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movl.cl %0,%1 ;8
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movh.cl %0,%L1>>16 ;9
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* return INTVAL (operands[1]) & 0xffffff ? \"movbi.cl %0,%1 >> %p1,%p1,8;10\" : \"movbi.cl %0,%L1 >> 24,24,8;10\";
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mov%? %0,%1 ;11
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add %0,%1 ;12
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add %0,pcl,%1@pcl ;13
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mov%? %0,%j1 ;14
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mov%? %0,%j1 ;15
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mov%? %0,%j1 ;16
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ld%? %0,%1 ;17
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st%? %1,%0%& ;18
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* return arc_short_long (insn, \"push%? %1%&\", \"st%U0 %1,%0%&\");
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* return arc_short_long (insn, \"pop%? %0%&\", \"ld%U1 %0,%1%&\");
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ld%? %0,%1%& ;21
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xld%U1 %0,%1 ;22
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ld%? %0,%1%& ;23
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ld%? %0,%1%& ;24
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ld%U1%V1 %0,%1 ;25
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xst%U0 %1,%0 ;26
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st%? %1,%0%& ;27
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st%U0%V0 %1,%0 ;28
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st%U0%V0 %1,%0 ;29
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st%U0%V0 %1,%0 ;30
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st%U0%V0 %1,%0 ;31"
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; 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
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[(set_attr "type" "move, move, move,move,move, move, move,two_cycle_core,shift,shift,shift, move,binary,binary, move, move, move,load,store,store,load,load, load,load,load, load,store,store,store,store,store,store")
|
||||
(set_attr "iscompact" "maybe,maybe,maybe,true,true,false,false, false,false,false,false,false, false, false,maybe_limm,maybe_limm,false,true, true, true,true,true,false,true,true,false,false, true,false,false,false,false")
|
||||
; Use default length for iscompact to allow for COND_EXEC. But set length
|
||||
; of Crr to 4.
|
||||
(set_attr "length" "*,*,*,*,*,4,4,4,4,4,4,4,8,8,*,*,*,*,*,*,*,*,4,*,4,*,*,*,*,*,*,8")
|
||||
(set_attr "predicable" "yes,no,yes,no,no,yes,no,no,no,no,no,yes,no,no,yes,yes,yes,no,no,no,no,no,no,no,no,no,no,no,no,no,no,no")
|
||||
(set_attr "cpu_facility" "av1,av1,av1,av2,av2,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,av2,av2,*,*,av2,*,*,av2,*")])
|
||||
mov%?\\t%0,%1 ;0
|
||||
mov%?\\t%0,%1 ;1
|
||||
mov%?\\t%0,%1 ;2
|
||||
mov%?\\t%0,%1 ;3
|
||||
mov%?\\t%0,%1 ;4
|
||||
mov%?\\t%0,%1 ;5
|
||||
mov%?\\t%0,%1 ;6
|
||||
movl.cl\\t %0,%1 ;7
|
||||
movh.cl\\t %0,%L1>>16 ;8
|
||||
* return INTVAL (operands[1]) & 0xffffff ? \"movbi.cl\\t%0,%1 >> %p1,%p1,8;9\" : \"movbi.cl\\t%0,%L1 >> 24,24,8;9\";
|
||||
add\\t%0,%1 ;10
|
||||
add\\t%0,pcl,%1@pcl ;11
|
||||
#
|
||||
mov%?\\t%0,%j1 ;13
|
||||
mov%?\\t%0,%j1 ;14
|
||||
ld%?\\t%0,%1 ;15
|
||||
st%?\\t %1,%0 ;16
|
||||
* return arc_short_long (insn, \"push%?\\t%1%&\", \"st%U0\\t%1,%0%&\");
|
||||
* return arc_short_long (insn, \"pop%?\\t%0%&\", \"ld%U1\\t%0,%1%&\");
|
||||
ld%?\\t%0,%1 ;19
|
||||
xld%U1\\t%0,%1 ;20
|
||||
ld%?\\t%0,%1 ;21
|
||||
ld%?\\t%0,%1 ;22
|
||||
ld%U1%V1\\t%0,%1 ;23
|
||||
xst%U0\\t%1,%0 ;24
|
||||
st%?\\t%1,%0%& ;25
|
||||
st%U0%V0\\t%1,%0 ;26
|
||||
st%U0%V0\\t%1,%0 ;37
|
||||
st%U0%V0\\t%1,%0 ;28"
|
||||
"reload_completed && satisfies_constraint_Cax (operands[1])
|
||||
&& register_operand (operands[0], SImode)"
|
||||
[(const_int 0)]
|
||||
"
|
||||
arc_split_mov_const (operands);
|
||||
DONE;
|
||||
"
|
||||
; 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
|
||||
[(set_attr "type" "move, move, move,move,move, move, move,shift,shift,shift,binary,binary,multi,move, move,load,store,store,load,load, load,load,load, load,store,store,store,store,store")
|
||||
(set_attr "iscompact" "maybe,maybe,maybe,true,true,false,false,false,false,false, false, false,false,true,false,true, true, true,true,true,false,true,true,false,false, true,false,false,false")
|
||||
(set_attr "length" "*,*,*,*,*,4,4,4,4,4,8,8,*,6,*,*,*,*,*,*,4,*,4,*,*,*,*,*,8")
|
||||
(set_attr "predicable" "yes,no,yes,no,no,yes,no,no,no,yes,no,no,no,yes,yes,no,no,no,no,no,no,no,no,no,no,no,no,no,no")
|
||||
(set_attr "cpu_facility" "av1,av1,av1,av2,av2,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,av2,av2,*,*,av2,*,av2,*")])
|
||||
|
||||
;; Sometimes generated by the epilogue code. We don't want to
|
||||
;; recognize these addresses in general, because the limm is costly,
|
||||
|
|
@ -2303,16 +2300,23 @@ core_3, archs4x, archs4xd, archs4xd_slow"
|
|||
; ARCv2 has no penalties between mpy and mpyu. So, we use mpy because of its
|
||||
; short variant. LP_COUNT constraints are still valid.
|
||||
(define_insn "mulsi3_v2"
|
||||
[(set (match_operand:SI 0 "mpy_dest_reg_operand" "=Rcqq,Rcr, r,r,Rcr, r")
|
||||
(mult:SI (match_operand:SI 1 "register_operand" "%0, 0, c,0, 0, c")
|
||||
(match_operand:SI 2 "nonmemory_operand" " Rcqq, cL,cL,I,Cal,Cal")))]
|
||||
[(set (match_operand:SI 0 "mpy_dest_reg_operand" "=q,q, r, r,r, r, r")
|
||||
(mult:SI (match_operand:SI 1 "register_operand" "%0,q, 0, r,0, 0, c")
|
||||
(match_operand:SI 2 "nonmemory_operand" "q,0,rL,rL,I,Cal,Cal")))]
|
||||
"TARGET_MULTI"
|
||||
"mpy%? %0,%1,%2"
|
||||
[(set_attr "length" "*,4,4,4,8,8")
|
||||
(set_attr "iscompact" "maybe,false,false,false,false,false")
|
||||
"@
|
||||
mpy%?\\t%0,%1,%2
|
||||
mpy%?\\t%0,%2,%1
|
||||
mpy%?\\t%0,%1,%2
|
||||
mpy%?\\t%0,%1,%2
|
||||
mpy%?\\t%0,%1,%2
|
||||
mpy%?\\t%0,%1,%2
|
||||
mpy%?\\t%0,%1,%2"
|
||||
[(set_attr "length" "*,*,4,4,4,8,8")
|
||||
(set_attr "iscompact" "maybe,maybe,false,false,false,false,false")
|
||||
(set_attr "type" "umulti")
|
||||
(set_attr "predicable" "no,yes,no,no,yes,no")
|
||||
(set_attr "cond" "nocond,canuse,nocond,canuse_limm,canuse,nocond")])
|
||||
(set_attr "predicable" "no,no,yes,no,no,yes,no")
|
||||
(set_attr "cond" "nocond,nocond,canuse,nocond,canuse_limm,canuse,nocond")])
|
||||
|
||||
(define_expand "mulsidi3"
|
||||
[(set (match_operand:DI 0 "register_operand" "")
|
||||
|
|
@ -3216,10 +3220,10 @@ core_3, archs4x, archs4xd, archs4xd_slow"
|
|||
operands[1] = force_reg (SImode, operands[1]);
|
||||
")
|
||||
|
||||
(define_insn "andsi3_i"
|
||||
[(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,Rcq,Rcqq,Rcqq,Rcqq,Rcw,Rcw, Rcw,Rcw,Rcw,Rcw, w, w, w, w,Rrq,w,Rcw, w,W")
|
||||
(and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,Rcq, 0, 0,Rcqq, 0, c, 0, 0, 0, 0, c, c, c, c,Rrq,0, 0, c,o")
|
||||
(match_operand:SI 2 "nonmemory_operand" "Rcqq, 0, C1p, Ccp, Cux, cL, 0,C2pC1p,Ccp,CnL, I,Lc,C2pC1p,Ccp,CnL,Cbf,I,Cal,Cal,Cux")))]
|
||||
(define_insn "andsi3_i" ;0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
|
||||
[(set (match_operand:SI 0 "dest_reg_operand" "=q,q, q, q, q, r,r, r, r, r,r, r, r, r, r, q,r, r, r, W")
|
||||
(and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,q, 0, 0, q, 0,r, 0, 0, 0,0, r, r, r, r, q,0, 0, r, o")
|
||||
(match_operand:SI 2 "nonmemory_operand" "q,0,C1p,Ccp,Cux,rL,0,C2pC1p,Ccp,CnL,I,rL,C2pC1p,Ccp,CnL,Cbf,I,Cal,Cal,Cux")))]
|
||||
"(register_operand (operands[1], SImode)
|
||||
&& nonmemory_operand (operands[2], SImode))
|
||||
|| (memory_operand (operands[1], SImode)
|
||||
|
|
@ -3317,27 +3321,35 @@ core_3, archs4x, archs4xd, archs4xd_slow"
|
|||
(set_attr "predicable" "no,yes,no,yes,no,no,no")
|
||||
(set_attr "cond" "canuse,canuse,canuse_limm,canuse,nocond,nocond,nocond")])
|
||||
|
||||
(define_insn "iorsi3"
|
||||
[(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,Rcq,Rcqq,Rcw,Rcw,Rcw,Rcw,w, w,w,Rcw, w")
|
||||
(ior:SI (match_operand:SI 1 "nonmemory_operand" "% 0,Rcq, 0, 0, c, 0, 0, c, c,0, 0, c")
|
||||
(match_operand:SI 2 "nonmemory_operand" "Rcqq, 0, C0p, cL, 0,C0p, I,cL,C0p,I,Cal,Cal")))]
|
||||
(define_insn_and_split "iorsi3"
|
||||
[(set (match_operand:SI 0 "dest_reg_operand" "=q,q, q, r,r, r,r, r, r,r, q, r, r")
|
||||
(ior:SI (match_operand:SI 1 "register_operand" "%0,q, 0, 0,r, 0,0, r, r,0, r, 0, r")
|
||||
(match_operand:SI 2 "nonmemory_operand" "q,0,C0p,rL,0,C0p,I,rL,C0p,I,C0x,Cal,Cal")))]
|
||||
""
|
||||
"*
|
||||
switch (which_alternative)
|
||||
{
|
||||
case 0: case 3: case 6: case 7: case 9: case 10: case 11:
|
||||
return \"or%? %0,%1,%2%&\";
|
||||
case 1: case 4:
|
||||
return \"or%? %0,%2,%1%&\";
|
||||
case 2: case 5: case 8:
|
||||
return \"bset%? %0,%1,%z2%&\";
|
||||
default:
|
||||
gcc_unreachable ();
|
||||
}"
|
||||
[(set_attr "iscompact" "maybe,maybe,maybe,false,false,false,false,false,false,false,false,false")
|
||||
(set_attr "length" "*,*,*,4,4,4,4,4,4,4,8,8")
|
||||
(set_attr "predicable" "no,no,no,yes,yes,yes,no,no,no,no,yes,no")
|
||||
(set_attr "cond" "canuse,canuse,canuse,canuse,canuse,canuse,canuse_limm,nocond,nocond,canuse_limm,canuse,nocond")])
|
||||
"@
|
||||
or%?\\t%0,%1,%2
|
||||
or%?\\t%0,%2,%1
|
||||
bset%?\\t%0,%1,%z2
|
||||
or%?\\t%0,%1,%2
|
||||
or%?\\t%0,%2,%1
|
||||
bset%?\\t%0,%1,%z2
|
||||
or%?\\t%0,%1,%2
|
||||
or%?\\t%0,%1,%2
|
||||
bset%?\\t%0,%1,%z2
|
||||
or%?\\t%0,%1,%2
|
||||
#
|
||||
or%?\\t%0,%1,%2
|
||||
or%?\\t%0,%1,%2"
|
||||
"reload_completed && satisfies_constraint_C0x (operands[2])"
|
||||
[(const_int 0)]
|
||||
"
|
||||
arc_split_ior (operands);
|
||||
DONE;
|
||||
"
|
||||
[(set_attr "iscompact" "maybe,maybe,maybe,false,false,false,false,false,false,false,false,false,false")
|
||||
(set_attr "length" "*,*,*,4,4,4,4,4,4,4,*,8,8")
|
||||
(set_attr "predicable" "no,no,no,yes,yes,yes,no,no,no,no,no,yes,no")
|
||||
(set_attr "cond" "canuse,canuse,canuse,canuse,canuse,canuse,canuse_limm,nocond,nocond,canuse_limm,nocond,canuse,nocond")])
|
||||
|
||||
(define_insn "xorsi3"
|
||||
[(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,Rcq,Rcw,Rcw,Rcw,Rcw, w, w,w, w, w")
|
||||
|
|
@ -5972,11 +5984,21 @@ core_3, archs4x, archs4xd, archs4xd_slow"
|
|||
(match_dup 1)])
|
||||
|
||||
(define_insn "*rotrsi3_cnt1"
|
||||
[(set (match_operand:SI 0 "dest_reg_operand" "=w")
|
||||
(rotatert:SI (match_operand:SI 1 "register_operand" "c")
|
||||
[(set (match_operand:SI 0 "dest_reg_operand" "=r")
|
||||
(rotatert:SI (match_operand:SI 1 "nonmemory_operand" "rL")
|
||||
(const_int 1)))]
|
||||
""
|
||||
"ror %0,%1%&"
|
||||
"ror\\t%0,%1"
|
||||
[(set_attr "type" "shift")
|
||||
(set_attr "predicable" "no")
|
||||
(set_attr "length" "4")])
|
||||
|
||||
(define_insn "*rotrsi3_cnt8"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(rotatert:SI (match_operand:SI 1 "nonmemory_operand" "rL")
|
||||
(const_int 8)))]
|
||||
"TARGET_BARREL_SHIFTER && TARGET_V2"
|
||||
"ror8\\t%0,%1"
|
||||
[(set_attr "type" "shift")
|
||||
(set_attr "predicable" "no")
|
||||
(set_attr "length" "4")])
|
||||
|
|
@ -5989,8 +6011,31 @@ core_3, archs4x, archs4xd, archs4xd_slow"
|
|||
"asl%? %0,%1%&"
|
||||
[(set_attr "type" "shift")
|
||||
(set_attr "iscompact" "maybe,false")
|
||||
(set_attr "length" "4")
|
||||
(set_attr "predicable" "no,no")])
|
||||
|
||||
(define_insn "*ashlsi2_cnt8"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(ashift:SI (match_operand:SI 1 "nonmemory_operand" "rL")
|
||||
(const_int 8)))]
|
||||
"TARGET_BARREL_SHIFTER && TARGET_V2"
|
||||
"lsl8\\t%0,%1"
|
||||
[(set_attr "type" "shift")
|
||||
(set_attr "iscompact" "false")
|
||||
(set_attr "length" "4")
|
||||
(set_attr "predicable" "no")])
|
||||
|
||||
(define_insn "*ashlsi2_cnt16"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(ashift:SI (match_operand:SI 1 "nonmemory_operand" "rL")
|
||||
(const_int 16)))]
|
||||
"TARGET_BARREL_SHIFTER && TARGET_V2"
|
||||
"lsl16\\t%0,%1"
|
||||
[(set_attr "type" "shift")
|
||||
(set_attr "iscompact" "false")
|
||||
(set_attr "length" "4")
|
||||
(set_attr "predicable" "no")])
|
||||
|
||||
(define_insn "*lshrsi3_cnt1"
|
||||
[(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,w")
|
||||
(lshiftrt:SI (match_operand:SI 1 "register_operand" "Rcqq,c")
|
||||
|
|
|
|||
|
|
@ -201,7 +201,7 @@
|
|||
"@internal
|
||||
power of two"
|
||||
(and (match_code "const_int")
|
||||
(match_test "IS_POWEROF2_P (ival)")))
|
||||
(match_test "IS_POWEROF2_P (ival & 0xffffffff)")))
|
||||
|
||||
(define_constraint "C1p"
|
||||
"@internal
|
||||
|
|
@ -275,12 +275,6 @@
|
|||
(and (match_code "const_int")
|
||||
(match_test "ival == 1 || ival == 2 || ival == 4 || ival == 8")))
|
||||
|
||||
(define_constraint "Crr"
|
||||
"@internal
|
||||
constant that can be loaded with ror b,u6"
|
||||
(and (match_code "const_int")
|
||||
(match_test "(ival & ~0x8000001f) == 0 && !arc_ccfsm_cond_exec_p ()")))
|
||||
|
||||
(define_constraint "Cbi"
|
||||
"@internal
|
||||
constant that can be loaded with movbi.cl"
|
||||
|
|
@ -290,6 +284,20 @@
|
|||
|| ((ival & 0xffffffffUL) >> exact_log2 (ival & -ival)
|
||||
<= 0xff)")))
|
||||
|
||||
(define_constraint "C0x"
|
||||
"@internal
|
||||
special const_int pattern used to split ior insns"
|
||||
(and (match_code "const_int")
|
||||
(match_test "optimize_size")
|
||||
(match_test "arc_check_ior_const (ival)")))
|
||||
|
||||
(define_constraint "Cax"
|
||||
"@internal
|
||||
special const_int pattern used to split mov insns"
|
||||
(and (match_code "const_int")
|
||||
(match_test "optimize_size")
|
||||
(match_test "arc_check_mov_const (ival)")))
|
||||
|
||||
;; Floating-point constraints
|
||||
|
||||
(define_constraint "G"
|
||||
|
|
|
|||
|
|
@ -1,3 +1,20 @@
|
|||
2019-06-10 Claudiu Zissulescu <claziss@synopsys.com>
|
||||
|
||||
* gcc.target/arc/and-cnst-size.c: New test.
|
||||
* gcc.target/arc/mov-cnst-size.c: Likewise.
|
||||
* gcc.target/arc/or-cnst-size.c: Likewise.
|
||||
* gcc.target/arc/store-merge-1.c: Update test.
|
||||
* gcc.target/arc/arc700-stld-hazard.c: Likewise.
|
||||
* gcc.target/arc/cmem-1.c: Likewise.
|
||||
* gcc.target/arc/cmem-2.c: Likewise.
|
||||
* gcc.target/arc/cmem-3.c: Likewise.
|
||||
* gcc.target/arc/cmem-4.c: Likewise.
|
||||
* gcc.target/arc/cmem-5.c: Likewise.
|
||||
* gcc.target/arc/cmem-6.c: Likewise.
|
||||
* gcc.target/arc/loop-4.c: Likewise.
|
||||
* gcc.target/arc/movh_cl-1.c: Likewise.
|
||||
* gcc.target/arc/sdata-3.c: Likewise.
|
||||
|
||||
2019-06-10 Martin Liska <mliska@suse.cz>
|
||||
|
||||
* gcc.dg/ipa/pr68035.c: Update scanned pattern.
|
||||
|
|
|
|||
|
|
@ -0,0 +1,16 @@
|
|||
/* Tests to check if and instructions are emitted efficiently. */
|
||||
/* { dg-require-effective-target codedensity } */
|
||||
/* { dg-options "-Os" } */
|
||||
|
||||
int check_bclr (int a)
|
||||
{
|
||||
return a & (~0x40);
|
||||
}
|
||||
|
||||
int check_bmskn (int a)
|
||||
{
|
||||
return a & (-128);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "bclr_s" } } */
|
||||
/* { dg-final { scan-assembler "bmskn" } } */
|
||||
|
|
@ -1,5 +1,6 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-mcpu=arc700 -mno-sdata" } */
|
||||
/* { dg-skip-if "" { ! { clmcpu } } } */
|
||||
/* { dg-options "-mcpu=arc700 -mno-sdata -O2" } */
|
||||
|
||||
volatile int a;
|
||||
volatile int b;
|
||||
|
|
@ -11,4 +12,4 @@ foo ()
|
|||
b = a;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "st r\[0-9\]+,\\\[@a\\\]\[^\n\]*\n\[ \t\]+nop_s\[^\n\]*\n\[ \t\]+nop_s\[^\n\]*\n\[ \t\]+ld r\[0-9\]+,\\\[@a\\\]" } } */
|
||||
/* { dg-final { scan-assembler "st\\s+r\[0-9\]+,\\\[@a\\\]\\.*\[^\n\]*\n\[ \t\]+nop_s\[^\n\]*\n\[ \t\]+nop_s\[^\n\]*\n\[ \t\]+ld\\s+r\[0-9\]+,\\\[@a\\\]" } } */
|
||||
|
|
|
|||
|
|
@ -6,6 +6,6 @@
|
|||
|
||||
#include "cmem-st.inc"
|
||||
|
||||
/* { dg-final { scan-assembler "xst " } } */
|
||||
/* { dg-final { scan-assembler "xstw " } } */
|
||||
/* { dg-final { scan-assembler "xstb " } } */
|
||||
/* { dg-final { scan-assembler "xst\\s" } } */
|
||||
/* { dg-final { scan-assembler "xstw\\s" } } */
|
||||
/* { dg-final { scan-assembler "xstb\\s" } } */
|
||||
|
|
|
|||
|
|
@ -6,6 +6,6 @@
|
|||
|
||||
#include "cmem-ld.inc"
|
||||
|
||||
/* { dg-final { scan-assembler "xld " } } */
|
||||
/* { dg-final { scan-assembler "xldw " } } */
|
||||
/* { dg-final { scan-assembler "xldb " } } */
|
||||
/* { dg-final { scan-assembler "xld\\s" } } */
|
||||
/* { dg-final { scan-assembler "xldw\\s" } } */
|
||||
/* { dg-final { scan-assembler "xldb\\s" } } */
|
||||
|
|
|
|||
|
|
@ -6,6 +6,6 @@
|
|||
|
||||
#include "cmem-st.inc"
|
||||
|
||||
/* { dg-final { scan-assembler "xst " } } */
|
||||
/* { dg-final { scan-assembler "xstw " } } */
|
||||
/* { dg-final { scan-assembler "xstb " } } */
|
||||
/* { dg-final { scan-assembler "xst\\s" } } */
|
||||
/* { dg-final { scan-assembler "xstw\\s" } } */
|
||||
/* { dg-final { scan-assembler "xstb\\s" } } */
|
||||
|
|
|
|||
|
|
@ -6,6 +6,6 @@
|
|||
|
||||
#include "cmem-ld.inc"
|
||||
|
||||
/* { dg-final { scan-assembler "xld " } } */
|
||||
/* { dg-final { scan-assembler "xldw " } } */
|
||||
/* { dg-final { scan-assembler "xldb " } } */
|
||||
/* { dg-final { scan-assembler "xld\\s" } } */
|
||||
/* { dg-final { scan-assembler "xldw\\s" } } */
|
||||
/* { dg-final { scan-assembler "xldb\\s" } } */
|
||||
|
|
|
|||
|
|
@ -6,6 +6,6 @@
|
|||
|
||||
#include "cmem-st.inc"
|
||||
|
||||
/* { dg-final { scan-assembler "xst " } } */
|
||||
/* { dg-final { scan-assembler "xstw " } } */
|
||||
/* { dg-final { scan-assembler "xstb " } } */
|
||||
/* { dg-final { scan-assembler "xst\\s" } } */
|
||||
/* { dg-final { scan-assembler "xstw\\s" } } */
|
||||
/* { dg-final { scan-assembler "xstb\\s" } } */
|
||||
|
|
|
|||
|
|
@ -6,6 +6,6 @@
|
|||
|
||||
#include "cmem-ld.inc"
|
||||
|
||||
/* { dg-final { scan-assembler "xld " } } */
|
||||
/* { dg-final { scan-assembler "xldw " } } */
|
||||
/* { dg-final { scan-assembler "xldb " } } */
|
||||
/* { dg-final { scan-assembler "xld\\s" } } */
|
||||
/* { dg-final { scan-assembler "xldw\\s" } } */
|
||||
/* { dg-final { scan-assembler "xldb\\s" } } */
|
||||
|
|
|
|||
|
|
@ -3,12 +3,13 @@
|
|||
/* { dg-options "-Os -fbranch-count-reg" } */
|
||||
|
||||
|
||||
void fn1(void *p1, int p2, int p3)
|
||||
int fn1(void *p1, int p2, int p3)
|
||||
{
|
||||
char *d = p1;
|
||||
do
|
||||
*d++ = p2;
|
||||
while (--p3);
|
||||
return *d;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "lp_count" } } */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,42 @@
|
|||
/* Tests to check if mov instructions are emitted efficiently. */
|
||||
/* { dg-require-effective-target codedensity } */
|
||||
/* { dg-options "-Os" } */
|
||||
|
||||
int rule1 (void)
|
||||
{
|
||||
return 0x3f000000;
|
||||
}
|
||||
|
||||
int rule2 (void)
|
||||
{
|
||||
return 0x3f00;
|
||||
}
|
||||
|
||||
int rule3 (void)
|
||||
{
|
||||
return 0x3f0000;
|
||||
}
|
||||
|
||||
int rule4 (void)
|
||||
{
|
||||
return 0x22000;
|
||||
}
|
||||
|
||||
int rule5 (void)
|
||||
{
|
||||
return 0x8000001f;
|
||||
}
|
||||
|
||||
int rule6 (void)
|
||||
{
|
||||
return 0x3fffff;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "ror8\\s+r0,63" } } */
|
||||
/* { dg-final { scan-assembler "lsl8\\s+r0,63" } } */
|
||||
/* { dg-final { scan-assembler "lsl16\\s+r0,63" } } */
|
||||
/* { dg-final { scan-assembler "ror\\s+r0,63" } } */
|
||||
/* { dg-final { scan-assembler "mov_s\\s+r0,17" } } */
|
||||
/* { dg-final { scan-assembler "asl_s\\s+r0,r0,13" } } */
|
||||
/* { dg-final { scan-assembler "mov_s\\s+r0,-1" } } */
|
||||
/* { dg-final { scan-assembler "bmsk_s\\s+r0,r0,21" } } */
|
||||
|
|
@ -36,4 +36,4 @@ woof ()
|
|||
func (xx.raw);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "movh\.cl r\[0-9\]+,0xc0000000>>16" } } */
|
||||
/* { dg-final { scan-assembler "movh\.cl\\s+r\[0-9\]+,0xc0000000>>16" } } */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,16 @@
|
|||
/* Tests to check if or instructions are emitted efficiently. */
|
||||
/* { dg-require-effective-target codedensity } */
|
||||
/* { dg-options "-Os" } */
|
||||
|
||||
int check_bset1 (int a)
|
||||
{
|
||||
return a | 0x80000000;
|
||||
}
|
||||
|
||||
int check_bset2(int a)
|
||||
{
|
||||
return a | 0x2022;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "bset_s" 2 } } */
|
||||
/* { dg-final { scan-assembler "or" } } */
|
||||
|
|
@ -2,7 +2,7 @@
|
|||
for variables which are having a different alignment
|
||||
than the default data type indicates. */
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2" } */
|
||||
/* { dg-options "-O2 -msdata" } */
|
||||
|
||||
int g_a __attribute__ ((aligned (1)));
|
||||
int g_b;
|
||||
|
|
@ -24,13 +24,13 @@ TEST (b, int)
|
|||
TEST (c, short)
|
||||
TEST (d, char)
|
||||
|
||||
/* { dg-final { scan-assembler "ld r2,\\\[gp,@g_a@sda\\\]" } } */
|
||||
/* { dg-final { scan-assembler "ld.as r2,\\\[gp,@g_b@sda\\\]" } } */
|
||||
/* { dg-final { scan-assembler "ld\[hw\]\\\.as r2,\\\[gp,@g_c@sda\\\]" } } */
|
||||
/* { dg-final { scan-assembler "ldb r2,\\\[gp,@g_d@sda\\\]" } } */
|
||||
/* { dg-final { scan-assembler "ld\\s+r2,\\\[gp,@g_a@sda\\\]" } } */
|
||||
/* { dg-final { scan-assembler "ld.as\\s+r2,\\\[gp,@g_b@sda\\\]" } } */
|
||||
/* { dg-final { scan-assembler "ld\[hw\]\\\.as\\s+r2,\\\[gp,@g_c@sda\\\]" } } */
|
||||
/* { dg-final { scan-assembler "ldb\\s+r2,\\\[gp,@g_d@sda\\\]" } } */
|
||||
|
||||
/* { dg-final { scan-assembler "st r0,\\\[gp,@g_a@sda\\\]" } } */
|
||||
/* { dg-final { scan-assembler "st_s r0,\\\[gp,@g_b@sda\\\]" { target { arcem || archs } } } } */
|
||||
/* { dg-final { scan-assembler "st\\\.as r0,\\\[gp,@g_b@sda\\\]" { target { arc700 || arc6xx } } } } */
|
||||
/* { dg-final { scan-assembler "st\[hw\]\\\.as r0,\\\[gp,@g_c@sda\\\]" } } */
|
||||
/* { dg-final { scan-assembler "stb r0,\\\[gp,@g_d@sda\\\]" } } */
|
||||
/* { dg-final { scan-assembler "st\\s+r0,\\\[gp,@g_a@sda\\\]" } } */
|
||||
/* { dg-final { scan-assembler "st_s\\s+r0,\\\[gp,@g_b@sda\\\]" { target { codedensity } } } } */
|
||||
/* { dg-final { scan-assembler "st\\\.as\\s+r0,\\\[gp,@g_b@sda\\\]" { target { ! { codedensity } } } } } */
|
||||
/* { dg-final { scan-assembler "st\[hw\]\\\.as\\s+r0,\\\[gp,@g_c@sda\\\]" } } */
|
||||
/* { dg-final { scan-assembler "stb\\s+r0,\\\[gp,@g_d@sda\\\]" } } */
|
||||
|
|
|
|||
|
|
@ -14,4 +14,4 @@ int sigemptyset2 (sigset_t *set)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "st 0,\\\[r" 2 } } */
|
||||
/* { dg-final { scan-assembler-times "std\\s*0,\\\[r" 1 } } */
|
||||
|
|
|
|||
Loading…
Reference in New Issue