Do not do insv/extz on 1/2 byte structures
From-SVN: r9758
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@ -1929,7 +1929,23 @@
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;; Rotate and shift insns, in all their variants. These support shifts,
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;; Rotate and shift insns, in all their variants. These support shifts,
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;; field inserts and extracts, and various combinations thereof.
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;; field inserts and extracts, and various combinations thereof.
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(define_insn "insv"
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(define_expand "insv"
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[(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
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(match_operand:SI 1 "const_int_operand" "i")
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(match_operand:SI 2 "const_int_operand" "i"))
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(match_operand:SI 3 "gpc_reg_operand" "r"))]
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""
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"
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{
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/* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
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the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
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compiler if the address of the structure is taken later. */
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if (GET_CODE (operands[0]) == SUBREG
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&& (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
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FAIL;
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}")
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(define_insn ""
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[(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
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[(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
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(match_operand:SI 1 "const_int_operand" "i")
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(match_operand:SI 1 "const_int_operand" "i")
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(match_operand:SI 2 "const_int_operand" "i"))
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(match_operand:SI 2 "const_int_operand" "i"))
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@ -2021,7 +2037,23 @@
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return \"{rlimi|rlwimi} %0,%3,%5,%h2,%h1\";
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return \"{rlimi|rlwimi} %0,%3,%5,%h2,%h1\";
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}")
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}")
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(define_insn "extzv"
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(define_expand "extzv"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
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(match_operand:SI 2 "const_int_operand" "i")
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(match_operand:SI 3 "const_int_operand" "i")))]
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""
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"
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{
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/* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
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the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
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compiler if the address of the structure is taken later. */
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if (GET_CODE (operands[0]) == SUBREG
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&& (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
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FAIL;
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}")
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(define_insn ""
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
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(zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
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(match_operand:SI 2 "const_int_operand" "i")
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(match_operand:SI 2 "const_int_operand" "i")
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