rs6000.md (P): Use TARGET_*BIT rather than comparing Pmode.
* config/rs6000/rs6000.md (P): Use TARGET_*BIT rather than comparing Pmode. (SDI): New. (cmp): Delete. (wd): New. (add<mode>3, add<mode>3_internal1, add<mode>3_internal2, add<mode>3_internal3, one_cmpl<mode>2, sub<mode>3, neg<mode>2, clz<mode>2, ctz<mode>2, ffs<mode>2): New. (addsi3, addsi3_internal1, addsi3_internal2, addsi3_internal3, (one_cmplsi2, subsi3, negsi2, clzsi2, ctzsi2, ffssi2): Remove. (adddi3, adddi3_internal1, adddi3_internal2, adddi3_internal3, (one_cmpldi2, subdi3, negdi2, clzdi2, ctzdi2, ffsdi2): Remove. (sync_compare_and_swap<mode>): Use <wd> rather than <cmp>. From-SVN: r99262
This commit is contained in:
Geoffrey Keating
Geoffrey Keating
parent
1df5d87d8c
commit
0354e5d8b6
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@ -1,3 +1,19 @@
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2005-05-04 Geoffrey Keating <geoffk@apple.com>
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* config/rs6000/rs6000.md (P): Use TARGET_*BIT rather than
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comparing Pmode.
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(SDI): New.
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(cmp): Delete.
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(wd): New.
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(add<mode>3, add<mode>3_internal1, add<mode>3_internal2,
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add<mode>3_internal3, one_cmpl<mode>2, sub<mode>3, neg<mode>2,
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clz<mode>2, ctz<mode>2, ffs<mode>2): New.
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(addsi3, addsi3_internal1, addsi3_internal2, addsi3_internal3,
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(one_cmplsi2, subsi3, negsi2, clzsi2, ctzsi2, ffssi2): Remove.
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(adddi3, adddi3_internal1, adddi3_internal2, adddi3_internal3,
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(one_cmpldi2, subdi3, negdi2, clzdi2, ctzdi2, ffsdi2): Remove.
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(sync_compare_and_swap<mode>): Use <wd> rather than <cmp>.
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2005-05-05 Paul Brook <paul@codesourcery.com>
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* Makefile.in: Replace dependencies on basic-block.h, c-pragma.h,
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@ -119,20 +119,24 @@
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; of whole values in GPRs.
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(define_mode_macro GPR [SI (DI "TARGET_POWERPC64")])
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; Any supported integer mode
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; Any supported integer mode.
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(define_mode_macro INT [QI HI SI DI TI])
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; Any supported integer mode that fits in one register
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; Any supported integer mode that fits in one register.
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(define_mode_macro INT1 [QI HI SI (DI "TARGET_POWERPC64")])
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; This mode macro allows :P to be used for patterns that operate on
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; pointer-sized quantities. Exactly one of the two alternatives will match.
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(define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
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; SImode or DImode, even if DImode doesn't fit in GPRs.
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(define_mode_macro SDI [SI DI])
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; The size of a pointer. Also, the size of the value that a record-condition
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; (one with a '.') will compare.
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(define_mode_macro P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
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; Various instructions that come in SI and DI forms.
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(define_mode_attr larx [(SI "lwarx") (DI "ldarx")])
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(define_mode_attr stcx [(SI "stwcx.") (DI "stdcx.")])
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(define_mode_attr cmp [(SI "cmpw") (DI "cmpd")])
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; A generic w/d attribute, for things like cmpw/cmpd.
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(define_mode_attr wd [(SI "w") (DI "d")])
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;; Start with fixed-point load and store insns. Here we put only the more
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@ -1001,38 +1005,46 @@
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;; Fixed-point arithmetic insns.
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;; Discourage ai/addic because of carry but provide it in an alternative
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;; allowing register zero as source.
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(define_expand "addsi3"
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[(set (match_operand:SI 0 "gpc_reg_operand" "")
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(plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
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(match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
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(define_expand "add<mode>3"
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[(set (match_operand:SDI 0 "gpc_reg_operand" "")
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(plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
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(match_operand:SDI 2 "reg_or_arith_cint_operand" "")))]
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""
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"
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{
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if (GET_CODE (operands[2]) == CONST_INT
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&& ! add_operand (operands[2], SImode))
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if (<MODE>mode == DImode && ! TARGET_POWERPC64)
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{
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if (non_short_cint_operand (operands[2], DImode))
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FAIL;
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}
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else if (GET_CODE (operands[2]) == CONST_INT
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&& ! add_operand (operands[2], <MODE>mode))
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{
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rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
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? operands[0] : gen_reg_rtx (SImode));
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? operands[0] : gen_reg_rtx (<MODE>mode));
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HOST_WIDE_INT val = INTVAL (operands[2]);
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HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
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HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
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HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
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if (<MODE>mode == DImode && !CONST_OK_FOR_LETTER_P (rest, 'L'))
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FAIL;
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/* The ordering here is important for the prolog expander.
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When space is allocated from the stack, adding 'low' first may
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produce a temporary deallocation (which would be bad). */
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emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (rest)));
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emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low)));
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emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
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emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
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DONE;
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}
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}")
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(define_insn "*addsi3_internal1"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r")
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(plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b")
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(match_operand:SI 2 "add_operand" "r,I,I,L")))]
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;; Discourage ai/addic because of carry but provide it in an alternative
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;; allowing register zero as source.
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(define_insn "*add<mode>3_internal1"
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[(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
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(plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
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(match_operand:GPR 2 "add_operand" "r,I,I,L")))]
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""
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"@
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{cax|add} %0,%1,%2
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@ -1049,13 +1061,13 @@
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"{cau|addis} %0,%1,ha16(%2)"
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[(set_attr "length" "4")])
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(define_insn "*addsi3_internal2"
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(define_insn "*add<mode>3_internal2"
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[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
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(compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
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(match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
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(compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
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(match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
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(const_int 0)))
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(clobber (match_scratch:SI 3 "=r,r,r,r"))]
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"TARGET_32BIT"
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(clobber (match_scratch:P 3 "=r,r,r,r"))]
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""
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"@
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{cax.|add.} %3,%1,%2
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{ai.|addic.} %3,%1,%2
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@ -1066,28 +1078,28 @@
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(define_split
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[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
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(compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
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(match_operand:SI 2 "reg_or_short_operand" ""))
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(compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
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(match_operand:GPR 2 "reg_or_short_operand" ""))
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(const_int 0)))
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(clobber (match_scratch:SI 3 ""))]
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"TARGET_32BIT && reload_completed"
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(clobber (match_scratch:GPR 3 ""))]
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"reload_completed"
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[(set (match_dup 3)
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(plus:SI (match_dup 1)
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(plus:GPR (match_dup 1)
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(match_dup 2)))
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(set (match_dup 0)
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(compare:CC (match_dup 3)
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(const_int 0)))]
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"")
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(define_insn "*addsi3_internal3"
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(define_insn "*add<mode>3_internal3"
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[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
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(compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
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(match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
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(compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
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(match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
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(plus:SI (match_dup 1)
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(match_dup 2)))]
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"TARGET_32BIT"
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(set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
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(plus:P (match_dup 1)
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(match_dup 2)))]
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""
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"@
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{cax.|add.} %0,%1,%2
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{ai.|addic.} %0,%1,%2
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@ -1098,15 +1110,15 @@
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(define_split
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[(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
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(compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
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(match_operand:SI 2 "reg_or_short_operand" ""))
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(compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
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(match_operand:P 2 "reg_or_short_operand" ""))
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "")
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(plus:SI (match_dup 1) (match_dup 2)))]
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"TARGET_32BIT && reload_completed"
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(set (match_operand:P 0 "gpc_reg_operand" "")
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(plus:P (match_dup 1) (match_dup 2)))]
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"reload_completed"
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[(set (match_dup 0)
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(plus:SI (match_dup 1)
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(match_dup 2)))
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(plus:P (match_dup 1)
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(match_dup 2)))
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(set (match_dup 3)
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(compare:CC (match_dup 0)
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(const_int 0)))]
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@ -1117,34 +1129,44 @@
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;; add should be last in case the result gets used in an address.
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(define_split
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[(set (match_operand:SI 0 "gpc_reg_operand" "")
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(plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
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(match_operand:SI 2 "non_add_cint_operand" "")))]
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[(set (match_operand:GPR 0 "gpc_reg_operand" "")
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(plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
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(match_operand:GPR 2 "non_add_cint_operand" "")))]
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""
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[(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
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(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
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[(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
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(set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
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"
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{
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HOST_WIDE_INT val = INTVAL (operands[2]);
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HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
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HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
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HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
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operands[3] = GEN_INT (rest);
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operands[4] = GEN_INT (low);
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if (<MODE>mode == SImode || CONST_OK_FOR_LETTER_P (rest, 'L'))
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operands[3] = GEN_INT (rest);
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else if (! no_new_pseudos)
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{
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operands[3] = gen_reg_rtx (DImode);
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emit_move_insn (operands[3], operands[2]);
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emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
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DONE;
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}
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else
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FAIL;
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}")
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(define_insn "one_cmplsi2"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
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(define_insn "one_cmpl<mode>2"
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[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
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(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
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""
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"nor %0,%1,%1")
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(define_insn ""
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[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
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(compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
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(compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
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(const_int 0)))
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(clobber (match_scratch:SI 2 "=r,r"))]
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"TARGET_32BIT"
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(clobber (match_scratch:P 2 "=r,r"))]
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""
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"@
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nor. %2,%1,%1
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#"
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|
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@ -1153,12 +1175,12 @@
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(define_split
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[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
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(compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
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(compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
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(const_int 0)))
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(clobber (match_scratch:SI 2 ""))]
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"TARGET_32BIT && reload_completed"
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(clobber (match_scratch:P 2 ""))]
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"reload_completed"
|
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[(set (match_dup 2)
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(not:SI (match_dup 1)))
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(not:P (match_dup 1)))
|
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(set (match_dup 0)
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(compare:CC (match_dup 2)
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(const_int 0)))]
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|
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@ -1166,11 +1188,11 @@
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|
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(define_insn ""
|
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[(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
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(compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
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(compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
|
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(const_int 0)))
|
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(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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(not:SI (match_dup 1)))]
|
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"TARGET_32BIT"
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(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
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(not:P (match_dup 1)))]
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""
|
||||
"@
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nor. %0,%1,%1
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#"
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|
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@ -1179,13 +1201,13 @@
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|
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(define_split
|
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[(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
|
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(compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
|
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(compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
|
||||
(const_int 0)))
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "")
|
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(not:SI (match_dup 1)))]
|
||||
"TARGET_32BIT && reload_completed"
|
||||
(set (match_operand:P 0 "gpc_reg_operand" "")
|
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(not:P (match_dup 1)))]
|
||||
"reload_completed"
|
||||
[(set (match_dup 0)
|
||||
(not:SI (match_dup 1)))
|
||||
(not:P (match_dup 1)))
|
||||
(set (match_dup 2)
|
||||
(compare:CC (match_dup 0)
|
||||
(const_int 0)))]
|
||||
|
|
@ -1199,9 +1221,9 @@
|
|||
"{sf%I1|subf%I1c} %0,%2,%1")
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
|
||||
(minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
|
||||
(match_operand:SI 2 "gpc_reg_operand" "r,r")))]
|
||||
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
|
||||
(minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
|
||||
(match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
|
||||
"TARGET_POWERPC"
|
||||
"@
|
||||
subf %0,%2,%1
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||||
|
|
@ -1222,11 +1244,11 @@
|
|||
|
||||
(define_insn ""
|
||||
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
|
||||
(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
|
||||
(match_operand:SI 2 "gpc_reg_operand" "r,r"))
|
||||
(compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
|
||||
(match_operand:P 2 "gpc_reg_operand" "r,r"))
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:SI 3 "=r,r"))]
|
||||
"TARGET_POWERPC && TARGET_32BIT"
|
||||
(clobber (match_scratch:P 3 "=r,r"))]
|
||||
"TARGET_POWERPC"
|
||||
"@
|
||||
subf. %3,%2,%1
|
||||
#"
|
||||
|
|
@ -1235,13 +1257,13 @@
|
|||
|
||||
(define_split
|
||||
[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
|
||||
(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
|
||||
(match_operand:SI 2 "gpc_reg_operand" ""))
|
||||
(compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
|
||||
(match_operand:P 2 "gpc_reg_operand" ""))
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:SI 3 ""))]
|
||||
"TARGET_32BIT && reload_completed"
|
||||
(clobber (match_scratch:P 3 ""))]
|
||||
"reload_completed"
|
||||
[(set (match_dup 3)
|
||||
(minus:SI (match_dup 1)
|
||||
(minus:P (match_dup 1)
|
||||
(match_dup 2)))
|
||||
(set (match_dup 0)
|
||||
(compare:CC (match_dup 3)
|
||||
|
|
@ -1264,13 +1286,13 @@
|
|||
|
||||
(define_insn ""
|
||||
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
|
||||
(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
|
||||
(match_operand:SI 2 "gpc_reg_operand" "r,r"))
|
||||
(compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
|
||||
(match_operand:P 2 "gpc_reg_operand" "r,r"))
|
||||
(const_int 0)))
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
|
||||
(minus:SI (match_dup 1)
|
||||
(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
|
||||
(minus:P (match_dup 1)
|
||||
(match_dup 2)))]
|
||||
"TARGET_POWERPC && TARGET_32BIT"
|
||||
"TARGET_POWERPC"
|
||||
"@
|
||||
subf. %0,%2,%1
|
||||
#"
|
||||
|
|
@ -1279,32 +1301,35 @@
|
|||
|
||||
(define_split
|
||||
[(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
|
||||
(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
|
||||
(match_operand:SI 2 "gpc_reg_operand" ""))
|
||||
(compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
|
||||
(match_operand:P 2 "gpc_reg_operand" ""))
|
||||
(const_int 0)))
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "")
|
||||
(minus:SI (match_dup 1)
|
||||
(set (match_operand:P 0 "gpc_reg_operand" "")
|
||||
(minus:P (match_dup 1)
|
||||
(match_dup 2)))]
|
||||
"TARGET_32BIT && reload_completed"
|
||||
"reload_completed"
|
||||
[(set (match_dup 0)
|
||||
(minus:SI (match_dup 1)
|
||||
(minus:P (match_dup 1)
|
||||
(match_dup 2)))
|
||||
(set (match_dup 3)
|
||||
(compare:CC (match_dup 0)
|
||||
(const_int 0)))]
|
||||
"")
|
||||
|
||||
(define_expand "subsi3"
|
||||
[(set (match_operand:SI 0 "gpc_reg_operand" "")
|
||||
(minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
|
||||
(match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
|
||||
(define_mode_attr sub_op2 [(SI "reg_or_arith_cint_operand")
|
||||
(DI "reg_or_sub_cint64_operand")])
|
||||
|
||||
(define_expand "sub<mode>3"
|
||||
[(set (match_operand:SDI 0 "gpc_reg_operand" "")
|
||||
(minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
|
||||
(match_operand:SDI 2 "<sub_op2>" "")))]
|
||||
""
|
||||
"
|
||||
{
|
||||
if (GET_CODE (operands[2]) == CONST_INT)
|
||||
{
|
||||
emit_insn (gen_addsi3 (operands[0], operands[1],
|
||||
negate_rtx (SImode, operands[2])));
|
||||
emit_insn (gen_add<mode>3 (operands[0], operands[1],
|
||||
negate_rtx (<MODE>mode, operands[2])));
|
||||
DONE;
|
||||
}
|
||||
}")
|
||||
|
|
@ -1587,18 +1612,24 @@
|
|||
(set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
|
||||
"")
|
||||
|
||||
(define_insn "negsi2"
|
||||
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
|
||||
(neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
|
||||
(define_expand "neg<mode>2"
|
||||
[(set (match_operand:SDI 0 "gpc_reg_operand" "")
|
||||
(neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
|
||||
""
|
||||
"")
|
||||
|
||||
(define_insn "*neg<mode>2_internal"
|
||||
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
|
||||
(neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
|
||||
""
|
||||
"neg %0,%1")
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
|
||||
(compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
|
||||
(compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:SI 2 "=r,r"))]
|
||||
"TARGET_32BIT"
|
||||
(clobber (match_scratch:P 2 "=r,r"))]
|
||||
""
|
||||
"@
|
||||
neg. %2,%1
|
||||
#"
|
||||
|
|
@ -1607,12 +1638,12 @@
|
|||
|
||||
(define_split
|
||||
[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
|
||||
(compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
|
||||
(compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:SI 2 ""))]
|
||||
"TARGET_32BIT && reload_completed"
|
||||
(clobber (match_scratch:P 2 ""))]
|
||||
"reload_completed"
|
||||
[(set (match_dup 2)
|
||||
(neg:SI (match_dup 1)))
|
||||
(neg:P (match_dup 1)))
|
||||
(set (match_dup 0)
|
||||
(compare:CC (match_dup 2)
|
||||
(const_int 0)))]
|
||||
|
|
@ -1620,11 +1651,11 @@
|
|||
|
||||
(define_insn ""
|
||||
[(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
|
||||
(compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
|
||||
(compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
|
||||
(const_int 0)))
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
|
||||
(neg:SI (match_dup 1)))]
|
||||
"TARGET_32BIT"
|
||||
(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
|
||||
(neg:P (match_dup 1)))]
|
||||
""
|
||||
"@
|
||||
neg. %0,%1
|
||||
#"
|
||||
|
|
@ -1633,54 +1664,56 @@
|
|||
|
||||
(define_split
|
||||
[(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
|
||||
(compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
|
||||
(compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
|
||||
(const_int 0)))
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "")
|
||||
(neg:SI (match_dup 1)))]
|
||||
(set (match_operand:P 0 "gpc_reg_operand" "")
|
||||
(neg:P (match_dup 1)))]
|
||||
"TARGET_32BIT && reload_completed"
|
||||
[(set (match_dup 0)
|
||||
(neg:SI (match_dup 1)))
|
||||
(neg:P (match_dup 1)))
|
||||
(set (match_dup 2)
|
||||
(compare:CC (match_dup 0)
|
||||
(const_int 0)))]
|
||||
"")
|
||||
|
||||
(define_insn "clzsi2"
|
||||
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
|
||||
(clz:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
|
||||
(define_insn "clz<mode>2"
|
||||
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
|
||||
(clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
|
||||
""
|
||||
"{cntlz|cntlzw} %0,%1")
|
||||
"{cntlz|cntlz<wd>} %0,%1")
|
||||
|
||||
(define_expand "ctzsi2"
|
||||
(define_expand "ctz<mode>2"
|
||||
[(set (match_dup 2)
|
||||
(neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
|
||||
(parallel [(set (match_dup 3) (and:SI (match_dup 1)
|
||||
(match_dup 2)))
|
||||
(neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
|
||||
(parallel [(set (match_dup 3) (and:GPR (match_dup 1)
|
||||
(match_dup 2)))
|
||||
(clobber (scratch:CC))])
|
||||
(set (match_dup 4) (clz:SI (match_dup 3)))
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "=r")
|
||||
(minus:SI (const_int 31) (match_dup 4)))]
|
||||
(set (match_dup 4) (clz:GPR (match_dup 3)))
|
||||
(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
|
||||
(minus:GPR (match_dup 5) (match_dup 4)))]
|
||||
""
|
||||
{
|
||||
operands[2] = gen_reg_rtx (SImode);
|
||||
operands[3] = gen_reg_rtx (SImode);
|
||||
operands[4] = gen_reg_rtx (SImode);
|
||||
operands[2] = gen_reg_rtx (<MODE>mode);
|
||||
operands[3] = gen_reg_rtx (<MODE>mode);
|
||||
operands[4] = gen_reg_rtx (<MODE>mode);
|
||||
operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
|
||||
})
|
||||
|
||||
(define_expand "ffssi2"
|
||||
(define_expand "ffs<mode>2"
|
||||
[(set (match_dup 2)
|
||||
(neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
|
||||
(parallel [(set (match_dup 3) (and:SI (match_dup 1)
|
||||
(match_dup 2)))
|
||||
(neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
|
||||
(parallel [(set (match_dup 3) (and:GPR (match_dup 1)
|
||||
(match_dup 2)))
|
||||
(clobber (scratch:CC))])
|
||||
(set (match_dup 4) (clz:SI (match_dup 3)))
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "=r")
|
||||
(minus:SI (const_int 32) (match_dup 4)))]
|
||||
(set (match_dup 4) (clz:GPR (match_dup 3)))
|
||||
(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
|
||||
(minus:GPR (match_dup 5) (match_dup 4)))]
|
||||
""
|
||||
{
|
||||
operands[2] = gen_reg_rtx (SImode);
|
||||
operands[3] = gen_reg_rtx (SImode);
|
||||
operands[4] = gen_reg_rtx (SImode);
|
||||
operands[2] = gen_reg_rtx (<MODE>mode);
|
||||
operands[3] = gen_reg_rtx (<MODE>mode);
|
||||
operands[4] = gen_reg_rtx (<MODE>mode);
|
||||
operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
|
||||
})
|
||||
|
||||
(define_expand "mulsi3"
|
||||
|
|
@ -5830,284 +5863,6 @@
|
|||
|
||||
;; PowerPC64 DImode operations.
|
||||
|
||||
(define_expand "adddi3"
|
||||
[(set (match_operand:DI 0 "gpc_reg_operand" "")
|
||||
(plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
|
||||
(match_operand:DI 2 "reg_or_add_cint64_operand" "")))]
|
||||
""
|
||||
"
|
||||
{
|
||||
if (! TARGET_POWERPC64)
|
||||
{
|
||||
if (non_short_cint_operand (operands[2], DImode))
|
||||
FAIL;
|
||||
}
|
||||
else
|
||||
if (GET_CODE (operands[2]) == CONST_INT
|
||||
&& ! add_operand (operands[2], DImode))
|
||||
{
|
||||
rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
|
||||
? operands[0] : gen_reg_rtx (DImode));
|
||||
|
||||
HOST_WIDE_INT val = INTVAL (operands[2]);
|
||||
HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
|
||||
HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
|
||||
|
||||
if (!CONST_OK_FOR_LETTER_P (rest, 'L'))
|
||||
FAIL;
|
||||
|
||||
/* The ordering here is important for the prolog expander.
|
||||
When space is allocated from the stack, adding 'low' first may
|
||||
produce a temporary deallocation (which would be bad). */
|
||||
emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (rest)));
|
||||
emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low)));
|
||||
DONE;
|
||||
}
|
||||
}")
|
||||
|
||||
;; Discourage ai/addic because of carry but provide it in an alternative
|
||||
;; allowing register zero as source.
|
||||
|
||||
(define_insn "*adddi3_internal1"
|
||||
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r")
|
||||
(plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b")
|
||||
(match_operand:DI 2 "add_operand" "r,I,I,L")))]
|
||||
"TARGET_POWERPC64"
|
||||
"@
|
||||
add %0,%1,%2
|
||||
addi %0,%1,%2
|
||||
addic %0,%1,%2
|
||||
addis %0,%1,%v2")
|
||||
|
||||
(define_insn "*adddi3_internal2"
|
||||
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
|
||||
(compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
|
||||
(match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:DI 3 "=r,r,r,r"))]
|
||||
"TARGET_64BIT"
|
||||
"@
|
||||
add. %3,%1,%2
|
||||
addic. %3,%1,%2
|
||||
#
|
||||
#"
|
||||
[(set_attr "type" "fast_compare,compare,compare,compare")
|
||||
(set_attr "length" "4,4,8,8")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
|
||||
(compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
|
||||
(match_operand:DI 2 "reg_or_short_operand" ""))
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:DI 3 ""))]
|
||||
"TARGET_POWERPC64 && reload_completed"
|
||||
[(set (match_dup 3)
|
||||
(plus:DI (match_dup 1) (match_dup 2)))
|
||||
(set (match_dup 0)
|
||||
(compare:CC (match_dup 3)
|
||||
(const_int 0)))]
|
||||
"")
|
||||
|
||||
(define_insn "*adddi3_internal3"
|
||||
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
|
||||
(compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
|
||||
(match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
|
||||
(const_int 0)))
|
||||
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
|
||||
(plus:DI (match_dup 1) (match_dup 2)))]
|
||||
"TARGET_64BIT"
|
||||
"@
|
||||
add. %0,%1,%2
|
||||
addic. %0,%1,%2
|
||||
#
|
||||
#"
|
||||
[(set_attr "type" "fast_compare,compare,compare,compare")
|
||||
(set_attr "length" "4,4,8,8")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
|
||||
(compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
|
||||
(match_operand:DI 2 "reg_or_short_operand" ""))
|
||||
(const_int 0)))
|
||||
(set (match_operand:DI 0 "gpc_reg_operand" "")
|
||||
(plus:DI (match_dup 1) (match_dup 2)))]
|
||||
"TARGET_POWERPC64 && reload_completed"
|
||||
[(set (match_dup 0)
|
||||
(plus:DI (match_dup 1) (match_dup 2)))
|
||||
(set (match_dup 3)
|
||||
(compare:CC (match_dup 0)
|
||||
(const_int 0)))]
|
||||
"")
|
||||
|
||||
;; Split an add that we can't do in one insn into two insns, each of which
|
||||
;; does one 16-bit part. This is used by combine. Note that the low-order
|
||||
;; add should be last in case the result gets used in an address.
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:DI 0 "gpc_reg_operand" "")
|
||||
(plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
|
||||
(match_operand:DI 2 "non_add_cint_operand" "")))]
|
||||
"TARGET_POWERPC64"
|
||||
[(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
|
||||
(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
|
||||
"
|
||||
{
|
||||
HOST_WIDE_INT val = INTVAL (operands[2]);
|
||||
HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
|
||||
HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
|
||||
|
||||
operands[4] = GEN_INT (low);
|
||||
if (CONST_OK_FOR_LETTER_P (rest, 'L'))
|
||||
operands[3] = GEN_INT (rest);
|
||||
else if (! no_new_pseudos)
|
||||
{
|
||||
operands[3] = gen_reg_rtx (DImode);
|
||||
emit_move_insn (operands[3], operands[2]);
|
||||
emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
|
||||
DONE;
|
||||
}
|
||||
else
|
||||
FAIL;
|
||||
}")
|
||||
|
||||
(define_insn "one_cmpldi2"
|
||||
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
|
||||
(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
|
||||
"TARGET_POWERPC64"
|
||||
"nor %0,%1,%1")
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
|
||||
(compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:DI 2 "=r,r"))]
|
||||
"TARGET_64BIT"
|
||||
"@
|
||||
nor. %2,%1,%1
|
||||
#"
|
||||
[(set_attr "type" "compare")
|
||||
(set_attr "length" "4,8")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
|
||||
(compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:DI 2 ""))]
|
||||
"TARGET_POWERPC64 && reload_completed"
|
||||
[(set (match_dup 2)
|
||||
(not:DI (match_dup 1)))
|
||||
(set (match_dup 0)
|
||||
(compare:CC (match_dup 2)
|
||||
(const_int 0)))]
|
||||
"")
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
|
||||
(compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
|
||||
(const_int 0)))
|
||||
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
|
||||
(not:DI (match_dup 1)))]
|
||||
"TARGET_64BIT"
|
||||
"@
|
||||
nor. %0,%1,%1
|
||||
#"
|
||||
[(set_attr "type" "compare")
|
||||
(set_attr "length" "4,8")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
|
||||
(compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
|
||||
(const_int 0)))
|
||||
(set (match_operand:DI 0 "gpc_reg_operand" "")
|
||||
(not:DI (match_dup 1)))]
|
||||
"TARGET_POWERPC64 && reload_completed"
|
||||
[(set (match_dup 0)
|
||||
(not:DI (match_dup 1)))
|
||||
(set (match_dup 2)
|
||||
(compare:CC (match_dup 0)
|
||||
(const_int 0)))]
|
||||
"")
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
|
||||
(minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
|
||||
(match_operand:DI 2 "gpc_reg_operand" "r,r")))]
|
||||
"TARGET_POWERPC64"
|
||||
"@
|
||||
subf %0,%2,%1
|
||||
subfic %0,%2,%1")
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
|
||||
(compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
|
||||
(match_operand:DI 2 "gpc_reg_operand" "r,r"))
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:DI 3 "=r,r"))]
|
||||
"TARGET_64BIT"
|
||||
"@
|
||||
subf. %3,%2,%1
|
||||
#"
|
||||
[(set_attr "type" "fast_compare")
|
||||
(set_attr "length" "4,8")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
|
||||
(compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
|
||||
(match_operand:DI 2 "gpc_reg_operand" ""))
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:DI 3 ""))]
|
||||
"TARGET_POWERPC64 && reload_completed"
|
||||
[(set (match_dup 3)
|
||||
(minus:DI (match_dup 1) (match_dup 2)))
|
||||
(set (match_dup 0)
|
||||
(compare:CC (match_dup 3)
|
||||
(const_int 0)))]
|
||||
"")
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
|
||||
(compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
|
||||
(match_operand:DI 2 "gpc_reg_operand" "r,r"))
|
||||
(const_int 0)))
|
||||
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
|
||||
(minus:DI (match_dup 1) (match_dup 2)))]
|
||||
"TARGET_64BIT"
|
||||
"@
|
||||
subf. %0,%2,%1
|
||||
#"
|
||||
[(set_attr "type" "fast_compare")
|
||||
(set_attr "length" "4,8")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
|
||||
(compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
|
||||
(match_operand:DI 2 "gpc_reg_operand" ""))
|
||||
(const_int 0)))
|
||||
(set (match_operand:DI 0 "gpc_reg_operand" "")
|
||||
(minus:DI (match_dup 1) (match_dup 2)))]
|
||||
"TARGET_POWERPC64 && reload_completed"
|
||||
[(set (match_dup 0)
|
||||
(minus:DI (match_dup 1) (match_dup 2)))
|
||||
(set (match_dup 3)
|
||||
(compare:CC (match_dup 0)
|
||||
(const_int 0)))]
|
||||
"")
|
||||
|
||||
(define_expand "subdi3"
|
||||
[(set (match_operand:DI 0 "gpc_reg_operand" "")
|
||||
(minus:DI (match_operand:DI 1 "reg_or_short_operand" "")
|
||||
(match_operand:DI 2 "reg_or_sub_cint64_operand" "")))]
|
||||
""
|
||||
"
|
||||
{
|
||||
if (GET_CODE (operands[2]) == CONST_INT)
|
||||
{
|
||||
emit_insn (gen_adddi3 (operands[0], operands[1],
|
||||
negate_rtx (DImode, operands[2])));
|
||||
DONE;
|
||||
}
|
||||
}")
|
||||
|
||||
(define_insn_and_split "absdi2"
|
||||
[(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
|
||||
(abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
|
||||
|
|
@ -6132,108 +5887,6 @@
|
|||
(set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
|
||||
"")
|
||||
|
||||
(define_expand "negdi2"
|
||||
[(set (match_operand:DI 0 "gpc_reg_operand" "")
|
||||
(neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
|
||||
""
|
||||
"")
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
|
||||
(neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
|
||||
"TARGET_POWERPC64"
|
||||
"neg %0,%1")
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
|
||||
(compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:DI 2 "=r,r"))]
|
||||
"TARGET_64BIT"
|
||||
"@
|
||||
neg. %2,%1
|
||||
#"
|
||||
[(set_attr "type" "fast_compare")
|
||||
(set_attr "length" "4,8")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
|
||||
(compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:DI 2 ""))]
|
||||
"TARGET_POWERPC64 && reload_completed"
|
||||
[(set (match_dup 2)
|
||||
(neg:DI (match_dup 1)))
|
||||
(set (match_dup 0)
|
||||
(compare:CC (match_dup 2)
|
||||
(const_int 0)))]
|
||||
"")
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
|
||||
(compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
|
||||
(const_int 0)))
|
||||
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
|
||||
(neg:DI (match_dup 1)))]
|
||||
"TARGET_64BIT"
|
||||
"@
|
||||
neg. %0,%1
|
||||
#"
|
||||
[(set_attr "type" "fast_compare")
|
||||
(set_attr "length" "4,8")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
|
||||
(compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
|
||||
(const_int 0)))
|
||||
(set (match_operand:DI 0 "gpc_reg_operand" "")
|
||||
(neg:DI (match_dup 1)))]
|
||||
"TARGET_POWERPC64 && reload_completed"
|
||||
[(set (match_dup 0)
|
||||
(neg:DI (match_dup 1)))
|
||||
(set (match_dup 2)
|
||||
(compare:CC (match_dup 0)
|
||||
(const_int 0)))]
|
||||
"")
|
||||
|
||||
(define_insn "clzdi2"
|
||||
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
|
||||
(clz:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
|
||||
"TARGET_POWERPC64"
|
||||
"cntlzd %0,%1")
|
||||
|
||||
(define_expand "ctzdi2"
|
||||
[(set (match_dup 2)
|
||||
(neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
|
||||
(parallel [(set (match_dup 3) (and:DI (match_dup 1)
|
||||
(match_dup 2)))
|
||||
(clobber (scratch:CC))])
|
||||
(set (match_dup 4) (clz:DI (match_dup 3)))
|
||||
(set (match_operand:DI 0 "gpc_reg_operand" "=r")
|
||||
(minus:DI (const_int 63) (match_dup 4)))]
|
||||
"TARGET_POWERPC64"
|
||||
{
|
||||
operands[2] = gen_reg_rtx (DImode);
|
||||
operands[3] = gen_reg_rtx (DImode);
|
||||
operands[4] = gen_reg_rtx (DImode);
|
||||
})
|
||||
|
||||
(define_expand "ffsdi2"
|
||||
[(set (match_dup 2)
|
||||
(neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
|
||||
(parallel [(set (match_dup 3) (and:DI (match_dup 1)
|
||||
(match_dup 2)))
|
||||
(clobber (scratch:CC))])
|
||||
(set (match_dup 4) (clz:DI (match_dup 3)))
|
||||
(set (match_operand:DI 0 "gpc_reg_operand" "=r")
|
||||
(minus:DI (const_int 64) (match_dup 4)))]
|
||||
"TARGET_POWERPC64"
|
||||
{
|
||||
operands[2] = gen_reg_rtx (DImode);
|
||||
operands[3] = gen_reg_rtx (DImode);
|
||||
operands[4] = gen_reg_rtx (DImode);
|
||||
})
|
||||
|
||||
(define_insn "muldi3"
|
||||
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
|
||||
(mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
|
||||
|
|
@ -14746,7 +14399,7 @@
|
|||
(unspec:BLK [(mem:BLK (match_scratch 6 "X"))] UNSPEC_SYNC))
|
||||
(clobber (match_scratch:CC 4 "=&x"))]
|
||||
"TARGET_POWERPC"
|
||||
"sync\n\t<larx> %0,%y1\n\t<cmp>%I2 %0,%2\n\tbne- $+12\n\t<stcx> %3,%y1\n\tbne- $-16\n\tisync"
|
||||
"sync\n\t<larx> %0,%y1\n\tcmp<wd>%I2 %0,%2\n\tbne- $+12\n\t<stcx> %3,%y1\n\tbne- $-16\n\tisync"
|
||||
[(set_attr "length" "28")])
|
||||
|
||||
(define_expand "sync_add<mode>"
|
||||
|
|
|
|||
Loading…
Reference in New Issue