predicates.md (addsubx_operand): New.
* config/xtensa/predicates.md (addsubx_operand): New. * config/xtensa/xtensa.c (xtensa_emit_branch): New. (xtensa_emit_bit_branch): New. (xtensa_emit_movcc): New. * config/xtensa/xtensa.md (any_minmax): New code macro. (minmax): New code attribute. (any_cond, any_scc, any_scc_sf): New code macros. (*addx2, *addx4, *addx8): Delete. (*addx): New. (*subx2, *subx4, *subx8): Delete. (*subx): New. (sminsi3, uminsi3, smaxsi3, umaxsi3): Use any_minmax macro. (beq, bne, bgt, bge, blt, ble, bgtu, bgeu, bltu, bleu): Use any_cond. (*btrue, *bfalse, *ubtrue, *ubfalse): Use xtensa_emit_branch. (*bittrue, *bitfalse): Use xtensa_emit_bit_branch. (seq, sne, sgt, sge, slt, sle): Use any_scc macro. (movsicc_internal0, movsicc_internal1): Use xtensa_emit_movcc. (movsfcc_internal0, movsfcc_internal1): Likewise. (seq_sf, slt_sf, sle_sf): Use any_scc_sf macro. * config/xtensa/xtensa-protos.h: (xtensa_emit_branch): New. (xtensa_emit_bit_branch): New. (xtensa_emit_movcc): New. (function_arg_boundary): Add missing prototype. From-SVN: r118952
This commit is contained in:
Bob Wilson
Bob Wilson
parent
3e98014384
commit
036a2b7a60
@ -1,3 +1,29 @@
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2006-11-17 Bob Wilson <bob.wilson@acm.org>
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* config/xtensa/predicates.md (addsubx_operand): New.
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* config/xtensa/xtensa.c (xtensa_emit_branch): New.
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(xtensa_emit_bit_branch): New.
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(xtensa_emit_movcc): New.
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* config/xtensa/xtensa.md (any_minmax): New code macro.
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(minmax): New code attribute.
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(any_cond, any_scc, any_scc_sf): New code macros.
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(*addx2, *addx4, *addx8): Delete.
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(*addx): New.
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(*subx2, *subx4, *subx8): Delete.
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(*subx): New.
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(sminsi3, uminsi3, smaxsi3, umaxsi3): Use any_minmax macro.
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(beq, bne, bgt, bge, blt, ble, bgtu, bgeu, bltu, bleu): Use any_cond.
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(*btrue, *bfalse, *ubtrue, *ubfalse): Use xtensa_emit_branch.
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(*bittrue, *bitfalse): Use xtensa_emit_bit_branch.
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(seq, sne, sgt, sge, slt, sle): Use any_scc macro.
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(movsicc_internal0, movsicc_internal1): Use xtensa_emit_movcc.
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(movsfcc_internal0, movsfcc_internal1): Likewise.
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(seq_sf, slt_sf, sle_sf): Use any_scc_sf macro.
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* config/xtensa/xtensa-protos.h: (xtensa_emit_branch): New.
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(xtensa_emit_bit_branch): New.
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(xtensa_emit_movcc): New.
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(function_arg_boundary): Add missing prototype.
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2006-11-17 Bob Wilson <bob.wilson@acm.org>
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2006-11-17 Bob Wilson <bob.wilson@acm.org>
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* config/xtensa/xtensa.md (tstsi): Delete
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* config/xtensa/xtensa.md (tstsi): Delete
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@ -1,5 +1,5 @@
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;; Predicate definitions for Xtensa.
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;; Predicate definitions for Xtensa.
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;; Copyright (C) 2005 Free Software Foundation, Inc.
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;; Copyright (C) 2005, 2006 Free Software Foundation, Inc.
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;;
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;;
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;; This file is part of GCC.
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;; This file is part of GCC.
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;;
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;;
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@ -24,6 +24,12 @@
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|| xtensa_simm8x256 (INTVAL (op))"))
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|| xtensa_simm8x256 (INTVAL (op))"))
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(match_operand 0 "register_operand")))
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(match_operand 0 "register_operand")))
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(define_predicate "addsubx_operand"
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(and (match_code "const_int")
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(match_test "INTVAL (op) == 2
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|| INTVAL (op) == 4
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|| INTVAL (op) == 8")))
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(define_predicate "arith_operand"
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(define_predicate "arith_operand"
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(ior (and (match_code "const_int")
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(ior (and (match_code "const_int")
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(match_test "xtensa_simm8 (INTVAL (op))"))
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(match_test "xtensa_simm8 (INTVAL (op))"))
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@ -50,6 +50,9 @@ extern int xtensa_emit_move_sequence (rtx *, enum machine_mode);
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extern rtx xtensa_copy_incoming_a7 (rtx);
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extern rtx xtensa_copy_incoming_a7 (rtx);
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extern void xtensa_expand_nonlocal_goto (rtx *);
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extern void xtensa_expand_nonlocal_goto (rtx *);
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extern void xtensa_emit_loop_end (rtx, rtx *);
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extern void xtensa_emit_loop_end (rtx, rtx *);
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extern char *xtensa_emit_branch (bool, bool, rtx *);
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extern char *xtensa_emit_bit_branch (bool, bool, rtx *);
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extern char *xtensa_emit_movcc (bool, bool, bool, rtx *);
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extern char *xtensa_emit_call (int, rtx *);
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extern char *xtensa_emit_call (int, rtx *);
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#ifdef TREE_CODE
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#ifdef TREE_CODE
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@ -71,6 +74,7 @@ extern enum reg_class xtensa_secondary_reload_class (enum reg_class,
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extern void function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode, tree);
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extern void function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode, tree);
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extern struct rtx_def *function_arg (CUMULATIVE_ARGS *, enum machine_mode,
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extern struct rtx_def *function_arg (CUMULATIVE_ARGS *, enum machine_mode,
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tree, int);
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tree, int);
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extern int function_arg_boundary (enum machine_mode, tree);
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#endif /* TREE_CODE */
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#endif /* TREE_CODE */
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extern void xtensa_setup_frame_addresses (void);
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extern void xtensa_setup_frame_addresses (void);
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@ -1368,6 +1368,101 @@ xtensa_emit_loop_end (rtx insn, rtx *operands)
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}
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}
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char *
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xtensa_emit_branch (bool inverted, bool immed, rtx *operands)
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{
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static char result[64];
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enum rtx_code code;
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const char *op;
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code = GET_CODE (operands[3]);
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switch (code)
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{
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case EQ: op = inverted ? "ne" : "eq"; break;
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case NE: op = inverted ? "eq" : "ne"; break;
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case LT: op = inverted ? "ge" : "lt"; break;
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case GE: op = inverted ? "lt" : "ge"; break;
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case LTU: op = inverted ? "geu" : "ltu"; break;
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case GEU: op = inverted ? "ltu" : "geu"; break;
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default: gcc_unreachable ();
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}
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if (immed)
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{
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if (INTVAL (operands[1]) == 0)
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sprintf (result, "b%sz%s\t%%0, %%2", op,
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(TARGET_DENSITY && (code == EQ || code == NE)) ? ".n" : "");
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else
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sprintf (result, "b%si\t%%0, %%d1, %%2", op);
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}
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else
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sprintf (result, "b%s\t%%0, %%1, %%2", op);
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return result;
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}
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char *
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xtensa_emit_bit_branch (bool inverted, bool immed, rtx *operands)
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{
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static char result[64];
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const char *op;
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switch (GET_CODE (operands[3]))
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{
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case EQ: op = inverted ? "bs" : "bc"; break;
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case NE: op = inverted ? "bc" : "bs"; break;
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default: gcc_unreachable ();
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}
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if (immed)
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{
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unsigned bitnum = INTVAL (operands[1]) & 0x1f;
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operands[1] = GEN_INT (bitnum);
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sprintf (result, "b%si\t%%0, %%d1, %%2", op);
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}
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else
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sprintf (result, "b%s\t%%0, %%1, %%2", op);
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return result;
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}
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char *
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xtensa_emit_movcc (bool inverted, bool isfp, bool isbool, rtx *operands)
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{
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static char result[64];
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enum rtx_code code;
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const char *op;
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code = GET_CODE (operands[4]);
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if (isbool)
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{
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switch (code)
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{
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case EQ: op = inverted ? "t" : "f"; break;
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case NE: op = inverted ? "f" : "t"; break;
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default: gcc_unreachable ();
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}
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}
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else
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{
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switch (code)
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{
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case EQ: op = inverted ? "nez" : "eqz"; break;
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case NE: op = inverted ? "eqz" : "nez"; break;
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case LT: op = inverted ? "gez" : "ltz"; break;
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case GE: op = inverted ? "ltz" : "gez"; break;
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default: gcc_unreachable ();
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}
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}
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sprintf (result, "mov%s%s\t%%0, %%%d, %%1",
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op, isfp ? ".s" : "", inverted ? 3 : 2);
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return result;
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}
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char *
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char *
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xtensa_emit_call (int callop, rtx *operands)
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xtensa_emit_call (int callop, rtx *operands)
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{
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{
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@ -45,6 +45,24 @@
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;; <su> is like <u>, but the signed form expands to "s" rather than "".
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;; <su> is like <u>, but the signed form expands to "s" rather than "".
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(define_code_attr su [(sign_extend "s") (zero_extend "u")])
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(define_code_attr su [(sign_extend "s") (zero_extend "u")])
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;; This code macro allows four integer min/max operations to be
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;; generated from one template.
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(define_code_macro any_minmax [smin umin smax umax])
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;; <minmax> expands to the opcode name for any_minmax operations.
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(define_code_attr minmax [(smin "min") (umin "minu")
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(smax "max") (umax "maxu")])
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;; This code macro allows all branch instructions to be generated from
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;; a single define_expand template.
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(define_code_macro any_cond [eq ne gt ge lt le gtu geu ltu leu])
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;; This code macro is for setting a register from a comparison.
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(define_code_macro any_scc [eq ne gt ge lt le])
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;; This code macro is for floating-point comparisons.
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(define_code_macro any_scc_sf [eq lt le])
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;; Attributes.
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;; Attributes.
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@ -170,35 +188,13 @@
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(set_attr "mode" "SI")
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(set_attr "mode" "SI")
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(set_attr "length" "2,2,3,3,3")])
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(set_attr "length" "2,2,3,3,3")])
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(define_insn "*addx2"
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(define_insn "*addx"
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[(set (match_operand:SI 0 "register_operand" "=a")
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[(set (match_operand:SI 0 "register_operand" "=a")
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(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
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(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
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(const_int 2))
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(match_operand:SI 3 "addsubx_operand" "i"))
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(match_operand:SI 2 "register_operand" "r")))]
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(match_operand:SI 2 "register_operand" "r")))]
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"TARGET_ADDX"
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"TARGET_ADDX"
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"addx2\t%0, %1, %2"
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"addx%3\t%0, %1, %2"
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")
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(set_attr "length" "3")])
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(define_insn "*addx4"
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[(set (match_operand:SI 0 "register_operand" "=a")
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(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
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(const_int 4))
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(match_operand:SI 2 "register_operand" "r")))]
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"TARGET_ADDX"
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"addx4\t%0, %1, %2"
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")
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(set_attr "length" "3")])
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(define_insn "*addx8"
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[(set (match_operand:SI 0 "register_operand" "=a")
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(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
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(const_int 8))
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(match_operand:SI 2 "register_operand" "r")))]
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"TARGET_ADDX"
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"addx8\t%0, %1, %2"
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[(set_attr "type" "arith")
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")
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(set_attr "mode" "SI")
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(set_attr "length" "3")])
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(set_attr "length" "3")])
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@ -257,35 +253,13 @@
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(set_attr "mode" "SI")
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(set_attr "mode" "SI")
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(set_attr "length" "3")])
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(set_attr "length" "3")])
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(define_insn "*subx2"
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(define_insn "*subx"
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[(set (match_operand:SI 0 "register_operand" "=a")
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[(set (match_operand:SI 0 "register_operand" "=a")
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(minus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
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(minus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
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(const_int 2))
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(match_operand:SI 3 "addsubx_operand" "i"))
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(match_operand:SI 2 "register_operand" "r")))]
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(match_operand:SI 2 "register_operand" "r")))]
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"TARGET_ADDX"
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"TARGET_ADDX"
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"subx2\t%0, %1, %2"
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"subx%3\t%0, %1, %2"
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")
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(set_attr "length" "3")])
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(define_insn "*subx4"
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[(set (match_operand:SI 0 "register_operand" "=a")
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(minus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
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(const_int 4))
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(match_operand:SI 2 "register_operand" "r")))]
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"TARGET_ADDX"
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"subx4\t%0, %1, %2"
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")
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(set_attr "length" "3")])
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(define_insn "*subx8"
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[(set (match_operand:SI 0 "register_operand" "=a")
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(minus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
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(const_int 8))
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(match_operand:SI 2 "register_operand" "r")))]
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"TARGET_ADDX"
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"subx8\t%0, %1, %2"
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[(set_attr "type" "arith")
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")
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(set_attr "mode" "SI")
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(set_attr "length" "3")])
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(set_attr "length" "3")])
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@ -537,42 +511,12 @@
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;; Min and max.
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;; Min and max.
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(define_insn "sminsi3"
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(define_insn "<code>si3"
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[(set (match_operand:SI 0 "register_operand" "=a")
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[(set (match_operand:SI 0 "register_operand" "=a")
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(smin:SI (match_operand:SI 1 "register_operand" "%r")
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(any_minmax:SI (match_operand:SI 1 "register_operand" "%r")
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(match_operand:SI 2 "register_operand" "r")))]
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(match_operand:SI 2 "register_operand" "r")))]
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"TARGET_MINMAX"
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"TARGET_MINMAX"
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"min\t%0, %1, %2"
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"<minmax>\t%0, %1, %2"
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")
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(set_attr "length" "3")])
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(define_insn "uminsi3"
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[(set (match_operand:SI 0 "register_operand" "=a")
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(umin:SI (match_operand:SI 1 "register_operand" "%r")
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(match_operand:SI 2 "register_operand" "r")))]
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"TARGET_MINMAX"
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"minu\t%0, %1, %2"
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")
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(set_attr "length" "3")])
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|
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(define_insn "smaxsi3"
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|
||||||
[(set (match_operand:SI 0 "register_operand" "=a")
|
|
||||||
(smax:SI (match_operand:SI 1 "register_operand" "%r")
|
|
||||||
(match_operand:SI 2 "register_operand" "r")))]
|
|
||||||
"TARGET_MINMAX"
|
|
||||||
"max\t%0, %1, %2"
|
|
||||||
[(set_attr "type" "arith")
|
|
||||||
(set_attr "mode" "SI")
|
|
||||||
(set_attr "length" "3")])
|
|
||||||
|
|
||||||
(define_insn "umaxsi3"
|
|
||||||
[(set (match_operand:SI 0 "register_operand" "=a")
|
|
||||||
(umax:SI (match_operand:SI 1 "register_operand" "%r")
|
|
||||||
(match_operand:SI 2 "register_operand" "r")))]
|
|
||||||
"TARGET_MINMAX"
|
|
||||||
"maxu\t%0, %1, %2"
|
|
||||||
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
||||||
(set_attr "mode" "SI")
|
(set_attr "mode" "SI")
|
||||||
(set_attr "length" "3")])
|
(set_attr "length" "3")])
|
||||||
@ -1236,113 +1180,14 @@
|
|||||||
|
|
||||||
;; Conditional branches.
|
;; Conditional branches.
|
||||||
|
|
||||||
(define_expand "beq"
|
(define_expand "b<code>"
|
||||||
[(set (pc)
|
[(set (pc)
|
||||||
(if_then_else (eq (cc0) (const_int 0))
|
(if_then_else (any_cond (cc0) (const_int 0))
|
||||||
(label_ref (match_operand 0 "" ""))
|
(label_ref (match_operand 0 "" ""))
|
||||||
(pc)))]
|
(pc)))]
|
||||||
""
|
""
|
||||||
{
|
{
|
||||||
xtensa_expand_conditional_branch (operands, EQ);
|
xtensa_expand_conditional_branch (operands, <CODE>);
|
||||||
DONE;
|
|
||||||
})
|
|
||||||
|
|
||||||
(define_expand "bne"
|
|
||||||
[(set (pc)
|
|
||||||
(if_then_else (ne (cc0) (const_int 0))
|
|
||||||
(label_ref (match_operand 0 "" ""))
|
|
||||||
(pc)))]
|
|
||||||
""
|
|
||||||
{
|
|
||||||
xtensa_expand_conditional_branch (operands, NE);
|
|
||||||
DONE;
|
|
||||||
})
|
|
||||||
|
|
||||||
(define_expand "bgt"
|
|
||||||
[(set (pc)
|
|
||||||
(if_then_else (gt (cc0) (const_int 0))
|
|
||||||
(label_ref (match_operand 0 "" ""))
|
|
||||||
(pc)))]
|
|
||||||
""
|
|
||||||
{
|
|
||||||
xtensa_expand_conditional_branch (operands, GT);
|
|
||||||
DONE;
|
|
||||||
})
|
|
||||||
|
|
||||||
(define_expand "bge"
|
|
||||||
[(set (pc)
|
|
||||||
(if_then_else (ge (cc0) (const_int 0))
|
|
||||||
(label_ref (match_operand 0 "" ""))
|
|
||||||
(pc)))]
|
|
||||||
""
|
|
||||||
{
|
|
||||||
xtensa_expand_conditional_branch (operands, GE);
|
|
||||||
DONE;
|
|
||||||
})
|
|
||||||
|
|
||||||
(define_expand "blt"
|
|
||||||
[(set (pc)
|
|
||||||
(if_then_else (lt (cc0) (const_int 0))
|
|
||||||
(label_ref (match_operand 0 "" ""))
|
|
||||||
(pc)))]
|
|
||||||
""
|
|
||||||
{
|
|
||||||
xtensa_expand_conditional_branch (operands, LT);
|
|
||||||
DONE;
|
|
||||||
})
|
|
||||||
|
|
||||||
(define_expand "ble"
|
|
||||||
[(set (pc)
|
|
||||||
(if_then_else (le (cc0) (const_int 0))
|
|
||||||
(label_ref (match_operand 0 "" ""))
|
|
||||||
(pc)))]
|
|
||||||
""
|
|
||||||
{
|
|
||||||
xtensa_expand_conditional_branch (operands, LE);
|
|
||||||
DONE;
|
|
||||||
})
|
|
||||||
|
|
||||||
(define_expand "bgtu"
|
|
||||||
[(set (pc)
|
|
||||||
(if_then_else (gtu (cc0) (const_int 0))
|
|
||||||
(label_ref (match_operand 0 "" ""))
|
|
||||||
(pc)))]
|
|
||||||
""
|
|
||||||
{
|
|
||||||
xtensa_expand_conditional_branch (operands, GTU);
|
|
||||||
DONE;
|
|
||||||
})
|
|
||||||
|
|
||||||
(define_expand "bgeu"
|
|
||||||
[(set (pc)
|
|
||||||
(if_then_else (geu (cc0) (const_int 0))
|
|
||||||
(label_ref (match_operand 0 "" ""))
|
|
||||||
(pc)))]
|
|
||||||
""
|
|
||||||
{
|
|
||||||
xtensa_expand_conditional_branch (operands, GEU);
|
|
||||||
DONE;
|
|
||||||
})
|
|
||||||
|
|
||||||
(define_expand "bltu"
|
|
||||||
[(set (pc)
|
|
||||||
(if_then_else (ltu (cc0) (const_int 0))
|
|
||||||
(label_ref (match_operand 0 "" ""))
|
|
||||||
(pc)))]
|
|
||||||
""
|
|
||||||
{
|
|
||||||
xtensa_expand_conditional_branch (operands, LTU);
|
|
||||||
DONE;
|
|
||||||
})
|
|
||||||
|
|
||||||
(define_expand "bleu"
|
|
||||||
[(set (pc)
|
|
||||||
(if_then_else (leu (cc0) (const_int 0))
|
|
||||||
(label_ref (match_operand 0 "" ""))
|
|
||||||
(pc)))]
|
|
||||||
""
|
|
||||||
{
|
|
||||||
xtensa_expand_conditional_branch (operands, LEU);
|
|
||||||
DONE;
|
DONE;
|
||||||
})
|
})
|
||||||
|
|
||||||
@ -1351,50 +1196,13 @@
|
|||||||
(define_insn "*btrue"
|
(define_insn "*btrue"
|
||||||
[(set (pc)
|
[(set (pc)
|
||||||
(if_then_else (match_operator 3 "branch_operator"
|
(if_then_else (match_operator 3 "branch_operator"
|
||||||
[(match_operand:SI 0 "register_operand" "r,r")
|
[(match_operand:SI 0 "register_operand" "r,r")
|
||||||
(match_operand:SI 1 "branch_operand" "K,r")])
|
(match_operand:SI 1 "branch_operand" "K,r")])
|
||||||
(label_ref (match_operand 2 "" ""))
|
(label_ref (match_operand 2 "" ""))
|
||||||
(pc)))]
|
(pc)))]
|
||||||
""
|
""
|
||||||
{
|
{
|
||||||
if (which_alternative == 1)
|
return xtensa_emit_branch (false, which_alternative == 0, operands);
|
||||||
{
|
|
||||||
switch (GET_CODE (operands[3]))
|
|
||||||
{
|
|
||||||
case EQ: return "beq\t%0, %1, %2";
|
|
||||||
case NE: return "bne\t%0, %1, %2";
|
|
||||||
case LT: return "blt\t%0, %1, %2";
|
|
||||||
case GE: return "bge\t%0, %1, %2";
|
|
||||||
default: gcc_unreachable ();
|
|
||||||
}
|
|
||||||
}
|
|
||||||
else if (INTVAL (operands[1]) == 0)
|
|
||||||
{
|
|
||||||
switch (GET_CODE (operands[3]))
|
|
||||||
{
|
|
||||||
case EQ: return (TARGET_DENSITY
|
|
||||||
? "beqz.n\t%0, %2"
|
|
||||||
: "beqz\t%0, %2");
|
|
||||||
case NE: return (TARGET_DENSITY
|
|
||||||
? "bnez.n\t%0, %2"
|
|
||||||
: "bnez\t%0, %2");
|
|
||||||
case LT: return "bltz\t%0, %2";
|
|
||||||
case GE: return "bgez\t%0, %2";
|
|
||||||
default: gcc_unreachable ();
|
|
||||||
}
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
switch (GET_CODE (operands[3]))
|
|
||||||
{
|
|
||||||
case EQ: return "beqi\t%0, %d1, %2";
|
|
||||||
case NE: return "bnei\t%0, %d1, %2";
|
|
||||||
case LT: return "blti\t%0, %d1, %2";
|
|
||||||
case GE: return "bgei\t%0, %d1, %2";
|
|
||||||
default: gcc_unreachable ();
|
|
||||||
}
|
|
||||||
}
|
|
||||||
gcc_unreachable ();
|
|
||||||
}
|
}
|
||||||
[(set_attr "type" "jump,jump")
|
[(set_attr "type" "jump,jump")
|
||||||
(set_attr "mode" "none")
|
(set_attr "mode" "none")
|
||||||
@ -1403,50 +1211,13 @@
|
|||||||
(define_insn "*bfalse"
|
(define_insn "*bfalse"
|
||||||
[(set (pc)
|
[(set (pc)
|
||||||
(if_then_else (match_operator 3 "branch_operator"
|
(if_then_else (match_operator 3 "branch_operator"
|
||||||
[(match_operand:SI 0 "register_operand" "r,r")
|
[(match_operand:SI 0 "register_operand" "r,r")
|
||||||
(match_operand:SI 1 "branch_operand" "K,r")])
|
(match_operand:SI 1 "branch_operand" "K,r")])
|
||||||
(pc)
|
(pc)
|
||||||
(label_ref (match_operand 2 "" ""))))]
|
(label_ref (match_operand 2 "" ""))))]
|
||||||
""
|
""
|
||||||
{
|
{
|
||||||
if (which_alternative == 1)
|
return xtensa_emit_branch (true, which_alternative == 0, operands);
|
||||||
{
|
|
||||||
switch (GET_CODE (operands[3]))
|
|
||||||
{
|
|
||||||
case EQ: return "bne\t%0, %1, %2";
|
|
||||||
case NE: return "beq\t%0, %1, %2";
|
|
||||||
case LT: return "bge\t%0, %1, %2";
|
|
||||||
case GE: return "blt\t%0, %1, %2";
|
|
||||||
default: gcc_unreachable ();
|
|
||||||
}
|
|
||||||
}
|
|
||||||
else if (INTVAL (operands[1]) == 0)
|
|
||||||
{
|
|
||||||
switch (GET_CODE (operands[3]))
|
|
||||||
{
|
|
||||||
case EQ: return (TARGET_DENSITY
|
|
||||||
? "bnez.n\t%0, %2"
|
|
||||||
: "bnez\t%0, %2");
|
|
||||||
case NE: return (TARGET_DENSITY
|
|
||||||
? "beqz.n\t%0, %2"
|
|
||||||
: "beqz\t%0, %2");
|
|
||||||
case LT: return "bgez\t%0, %2";
|
|
||||||
case GE: return "bltz\t%0, %2";
|
|
||||||
default: gcc_unreachable ();
|
|
||||||
}
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
switch (GET_CODE (operands[3]))
|
|
||||||
{
|
|
||||||
case EQ: return "bnei\t%0, %d1, %2";
|
|
||||||
case NE: return "beqi\t%0, %d1, %2";
|
|
||||||
case LT: return "bgei\t%0, %d1, %2";
|
|
||||||
case GE: return "blti\t%0, %d1, %2";
|
|
||||||
default: gcc_unreachable ();
|
|
||||||
}
|
|
||||||
}
|
|
||||||
gcc_unreachable ();
|
|
||||||
}
|
}
|
||||||
[(set_attr "type" "jump,jump")
|
[(set_attr "type" "jump,jump")
|
||||||
(set_attr "mode" "none")
|
(set_attr "mode" "none")
|
||||||
@ -1455,31 +1226,13 @@
|
|||||||
(define_insn "*ubtrue"
|
(define_insn "*ubtrue"
|
||||||
[(set (pc)
|
[(set (pc)
|
||||||
(if_then_else (match_operator 3 "ubranch_operator"
|
(if_then_else (match_operator 3 "ubranch_operator"
|
||||||
[(match_operand:SI 0 "register_operand" "r,r")
|
[(match_operand:SI 0 "register_operand" "r,r")
|
||||||
(match_operand:SI 1 "ubranch_operand" "L,r")])
|
(match_operand:SI 1 "ubranch_operand" "L,r")])
|
||||||
(label_ref (match_operand 2 "" ""))
|
(label_ref (match_operand 2 "" ""))
|
||||||
(pc)))]
|
(pc)))]
|
||||||
""
|
""
|
||||||
{
|
{
|
||||||
if (which_alternative == 1)
|
return xtensa_emit_branch (false, which_alternative == 0, operands);
|
||||||
{
|
|
||||||
switch (GET_CODE (operands[3]))
|
|
||||||
{
|
|
||||||
case LTU: return "bltu\t%0, %1, %2";
|
|
||||||
case GEU: return "bgeu\t%0, %1, %2";
|
|
||||||
default: gcc_unreachable ();
|
|
||||||
}
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
switch (GET_CODE (operands[3]))
|
|
||||||
{
|
|
||||||
case LTU: return "bltui\t%0, %d1, %2";
|
|
||||||
case GEU: return "bgeui\t%0, %d1, %2";
|
|
||||||
default: gcc_unreachable ();
|
|
||||||
}
|
|
||||||
}
|
|
||||||
gcc_unreachable ();
|
|
||||||
}
|
}
|
||||||
[(set_attr "type" "jump,jump")
|
[(set_attr "type" "jump,jump")
|
||||||
(set_attr "mode" "none")
|
(set_attr "mode" "none")
|
||||||
@ -1494,25 +1247,7 @@
|
|||||||
(label_ref (match_operand 2 "" ""))))]
|
(label_ref (match_operand 2 "" ""))))]
|
||||||
""
|
""
|
||||||
{
|
{
|
||||||
if (which_alternative == 1)
|
return xtensa_emit_branch (true, which_alternative == 0, operands);
|
||||||
{
|
|
||||||
switch (GET_CODE (operands[3]))
|
|
||||||
{
|
|
||||||
case LTU: return "bgeu\t%0, %1, %2";
|
|
||||||
case GEU: return "bltu\t%0, %1, %2";
|
|
||||||
default: gcc_unreachable ();
|
|
||||||
}
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
switch (GET_CODE (operands[3]))
|
|
||||||
{
|
|
||||||
case LTU: return "bgeui\t%0, %d1, %2";
|
|
||||||
case GEU: return "bltui\t%0, %d1, %2";
|
|
||||||
default: gcc_unreachable ();
|
|
||||||
}
|
|
||||||
}
|
|
||||||
gcc_unreachable ();
|
|
||||||
}
|
}
|
||||||
[(set_attr "type" "jump,jump")
|
[(set_attr "type" "jump,jump")
|
||||||
(set_attr "mode" "none")
|
(set_attr "mode" "none")
|
||||||
@ -1532,27 +1267,7 @@
|
|||||||
(pc)))]
|
(pc)))]
|
||||||
""
|
""
|
||||||
{
|
{
|
||||||
if (which_alternative == 0)
|
return xtensa_emit_bit_branch (false, which_alternative == 0, operands);
|
||||||
{
|
|
||||||
unsigned bitnum = INTVAL(operands[1]) & 0x1f;
|
|
||||||
operands[1] = GEN_INT(bitnum);
|
|
||||||
switch (GET_CODE (operands[3]))
|
|
||||||
{
|
|
||||||
case EQ: return "bbci\t%0, %d1, %2";
|
|
||||||
case NE: return "bbsi\t%0, %d1, %2";
|
|
||||||
default: gcc_unreachable ();
|
|
||||||
}
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
switch (GET_CODE (operands[3]))
|
|
||||||
{
|
|
||||||
case EQ: return "bbc\t%0, %1, %2";
|
|
||||||
case NE: return "bbs\t%0, %1, %2";
|
|
||||||
default: gcc_unreachable ();
|
|
||||||
}
|
|
||||||
}
|
|
||||||
gcc_unreachable ();
|
|
||||||
}
|
}
|
||||||
[(set_attr "type" "jump")
|
[(set_attr "type" "jump")
|
||||||
(set_attr "mode" "none")
|
(set_attr "mode" "none")
|
||||||
@ -1570,27 +1285,7 @@
|
|||||||
(label_ref (match_operand 2 "" ""))))]
|
(label_ref (match_operand 2 "" ""))))]
|
||||||
""
|
""
|
||||||
{
|
{
|
||||||
if (which_alternative == 0)
|
return xtensa_emit_bit_branch (true, which_alternative == 0, operands);
|
||||||
{
|
|
||||||
unsigned bitnum = INTVAL (operands[1]) & 0x1f;
|
|
||||||
operands[1] = GEN_INT (bitnum);
|
|
||||||
switch (GET_CODE (operands[3]))
|
|
||||||
{
|
|
||||||
case EQ: return "bbsi\t%0, %d1, %2";
|
|
||||||
case NE: return "bbci\t%0, %d1, %2";
|
|
||||||
default: gcc_unreachable ();
|
|
||||||
}
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
switch (GET_CODE (operands[3]))
|
|
||||||
{
|
|
||||||
case EQ: return "bbs\t%0, %1, %2";
|
|
||||||
case NE: return "bbc\t%0, %1, %2";
|
|
||||||
default: gcc_unreachable ();
|
|
||||||
}
|
|
||||||
}
|
|
||||||
gcc_unreachable ();
|
|
||||||
}
|
}
|
||||||
[(set_attr "type" "jump")
|
[(set_attr "type" "jump")
|
||||||
(set_attr "mode" "none")
|
(set_attr "mode" "none")
|
||||||
@ -1677,67 +1372,13 @@
|
|||||||
|
|
||||||
;; Setting a register from a comparison.
|
;; Setting a register from a comparison.
|
||||||
|
|
||||||
(define_expand "seq"
|
(define_expand "s<code>"
|
||||||
[(set (match_operand:SI 0 "register_operand" "")
|
[(set (match_operand:SI 0 "register_operand" "")
|
||||||
(match_dup 1))]
|
(any_scc:SI (match_dup 1)
|
||||||
|
(match_dup 2)))]
|
||||||
""
|
""
|
||||||
{
|
{
|
||||||
operands[1] = gen_rtx_EQ (SImode, branch_cmp[0], branch_cmp[1]);
|
operands[1] = gen_rtx_<CODE> (SImode, branch_cmp[0], branch_cmp[1]);
|
||||||
if (!xtensa_expand_scc (operands))
|
|
||||||
FAIL;
|
|
||||||
DONE;
|
|
||||||
})
|
|
||||||
|
|
||||||
(define_expand "sne"
|
|
||||||
[(set (match_operand:SI 0 "register_operand" "")
|
|
||||||
(match_dup 1))]
|
|
||||||
""
|
|
||||||
{
|
|
||||||
operands[1] = gen_rtx_NE (SImode, branch_cmp[0], branch_cmp[1]);
|
|
||||||
if (!xtensa_expand_scc (operands))
|
|
||||||
FAIL;
|
|
||||||
DONE;
|
|
||||||
})
|
|
||||||
|
|
||||||
(define_expand "sgt"
|
|
||||||
[(set (match_operand:SI 0 "register_operand" "")
|
|
||||||
(match_dup 1))]
|
|
||||||
""
|
|
||||||
{
|
|
||||||
operands[1] = gen_rtx_GT (SImode, branch_cmp[0], branch_cmp[1]);
|
|
||||||
if (!xtensa_expand_scc (operands))
|
|
||||||
FAIL;
|
|
||||||
DONE;
|
|
||||||
})
|
|
||||||
|
|
||||||
(define_expand "sge"
|
|
||||||
[(set (match_operand:SI 0 "register_operand" "")
|
|
||||||
(match_dup 1))]
|
|
||||||
""
|
|
||||||
{
|
|
||||||
operands[1] = gen_rtx_GE (SImode, branch_cmp[0], branch_cmp[1]);
|
|
||||||
if (!xtensa_expand_scc (operands))
|
|
||||||
FAIL;
|
|
||||||
DONE;
|
|
||||||
})
|
|
||||||
|
|
||||||
(define_expand "slt"
|
|
||||||
[(set (match_operand:SI 0 "register_operand" "")
|
|
||||||
(match_dup 1))]
|
|
||||||
""
|
|
||||||
{
|
|
||||||
operands[1] = gen_rtx_LT (SImode, branch_cmp[0], branch_cmp[1]);
|
|
||||||
if (!xtensa_expand_scc (operands))
|
|
||||||
FAIL;
|
|
||||||
DONE;
|
|
||||||
})
|
|
||||||
|
|
||||||
(define_expand "sle"
|
|
||||||
[(set (match_operand:SI 0 "register_operand" "")
|
|
||||||
(match_dup 1))]
|
|
||||||
""
|
|
||||||
{
|
|
||||||
operands[1] = gen_rtx_LE (SImode, branch_cmp[0], branch_cmp[1]);
|
|
||||||
if (!xtensa_expand_scc (operands))
|
if (!xtensa_expand_scc (operands))
|
||||||
FAIL;
|
FAIL;
|
||||||
DONE;
|
DONE;
|
||||||
@ -1779,29 +1420,7 @@
|
|||||||
(match_operand:SI 3 "register_operand" "0,r")))]
|
(match_operand:SI 3 "register_operand" "0,r")))]
|
||||||
""
|
""
|
||||||
{
|
{
|
||||||
if (which_alternative == 0)
|
return xtensa_emit_movcc (which_alternative == 1, false, false, operands);
|
||||||
{
|
|
||||||
switch (GET_CODE (operands[4]))
|
|
||||||
{
|
|
||||||
case EQ: return "moveqz\t%0, %2, %1";
|
|
||||||
case NE: return "movnez\t%0, %2, %1";
|
|
||||||
case LT: return "movltz\t%0, %2, %1";
|
|
||||||
case GE: return "movgez\t%0, %2, %1";
|
|
||||||
default: gcc_unreachable ();
|
|
||||||
}
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
switch (GET_CODE (operands[4]))
|
|
||||||
{
|
|
||||||
case EQ: return "movnez\t%0, %3, %1";
|
|
||||||
case NE: return "moveqz\t%0, %3, %1";
|
|
||||||
case LT: return "movgez\t%0, %3, %1";
|
|
||||||
case GE: return "movltz\t%0, %3, %1";
|
|
||||||
default: gcc_unreachable ();
|
|
||||||
}
|
|
||||||
}
|
|
||||||
gcc_unreachable ();
|
|
||||||
}
|
}
|
||||||
[(set_attr "type" "move,move")
|
[(set_attr "type" "move,move")
|
||||||
(set_attr "mode" "SI")
|
(set_attr "mode" "SI")
|
||||||
@ -1816,18 +1435,7 @@
|
|||||||
(match_operand:SI 3 "register_operand" "0,r")))]
|
(match_operand:SI 3 "register_operand" "0,r")))]
|
||||||
"TARGET_BOOLEANS"
|
"TARGET_BOOLEANS"
|
||||||
{
|
{
|
||||||
int isEq = (GET_CODE (operands[4]) == EQ);
|
return xtensa_emit_movcc (which_alternative == 1, false, true, operands);
|
||||||
switch (which_alternative)
|
|
||||||
{
|
|
||||||
case 0:
|
|
||||||
if (isEq) return "movf\t%0, %2, %1";
|
|
||||||
return "movt\t%0, %2, %1";
|
|
||||||
case 1:
|
|
||||||
if (isEq) return "movt\t%0, %3, %1";
|
|
||||||
return "movf\t%0, %3, %1";
|
|
||||||
default:
|
|
||||||
gcc_unreachable ();
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
[(set_attr "type" "move,move")
|
[(set_attr "type" "move,move")
|
||||||
(set_attr "mode" "SI")
|
(set_attr "mode" "SI")
|
||||||
@ -1842,52 +1450,8 @@
|
|||||||
(match_operand:SF 3 "register_operand" "0,r,0,f")))]
|
(match_operand:SF 3 "register_operand" "0,r,0,f")))]
|
||||||
""
|
""
|
||||||
{
|
{
|
||||||
switch (which_alternative)
|
return xtensa_emit_movcc ((which_alternative & 1) == 1,
|
||||||
{
|
which_alternative >= 2, false, operands);
|
||||||
case 0:
|
|
||||||
switch (GET_CODE (operands[4]))
|
|
||||||
{
|
|
||||||
case EQ: return "moveqz\t%0, %2, %1";
|
|
||||||
case NE: return "movnez\t%0, %2, %1";
|
|
||||||
case LT: return "movltz\t%0, %2, %1";
|
|
||||||
case GE: return "movgez\t%0, %2, %1";
|
|
||||||
default: gcc_unreachable ();
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
case 1:
|
|
||||||
switch (GET_CODE (operands[4]))
|
|
||||||
{
|
|
||||||
case EQ: return "movnez\t%0, %3, %1";
|
|
||||||
case NE: return "moveqz\t%0, %3, %1";
|
|
||||||
case LT: return "movgez\t%0, %3, %1";
|
|
||||||
case GE: return "movltz\t%0, %3, %1";
|
|
||||||
default: gcc_unreachable ();
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
case 2:
|
|
||||||
switch (GET_CODE (operands[4]))
|
|
||||||
{
|
|
||||||
case EQ: return "moveqz.s %0, %2, %1";
|
|
||||||
case NE: return "movnez.s %0, %2, %1";
|
|
||||||
case LT: return "movltz.s %0, %2, %1";
|
|
||||||
case GE: return "movgez.s %0, %2, %1";
|
|
||||||
default: gcc_unreachable ();
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
case 3:
|
|
||||||
switch (GET_CODE (operands[4]))
|
|
||||||
{
|
|
||||||
case EQ: return "movnez.s %0, %3, %1";
|
|
||||||
case NE: return "moveqz.s %0, %3, %1";
|
|
||||||
case LT: return "movgez.s %0, %3, %1";
|
|
||||||
case GE: return "movltz.s %0, %3, %1";
|
|
||||||
default: gcc_unreachable ();
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
gcc_unreachable ();
|
|
||||||
}
|
|
||||||
gcc_unreachable ();
|
|
||||||
}
|
}
|
||||||
[(set_attr "type" "move,move,move,move")
|
[(set_attr "type" "move,move,move,move")
|
||||||
(set_attr "mode" "SF")
|
(set_attr "mode" "SF")
|
||||||
@ -1902,24 +1466,8 @@
|
|||||||
(match_operand:SF 3 "register_operand" "0,r,0,f")))]
|
(match_operand:SF 3 "register_operand" "0,r,0,f")))]
|
||||||
"TARGET_BOOLEANS"
|
"TARGET_BOOLEANS"
|
||||||
{
|
{
|
||||||
int isEq = (GET_CODE (operands[4]) == EQ);
|
return xtensa_emit_movcc ((which_alternative & 1) == 1,
|
||||||
switch (which_alternative)
|
which_alternative >= 2, true, operands);
|
||||||
{
|
|
||||||
case 0:
|
|
||||||
if (isEq) return "movf\t%0, %2, %1";
|
|
||||||
return "movt\t%0, %2, %1";
|
|
||||||
case 1:
|
|
||||||
if (isEq) return "movt\t%0, %3, %1";
|
|
||||||
return "movf\t%0, %3, %1";
|
|
||||||
case 2:
|
|
||||||
if (isEq) return "movf.s\t%0, %2, %1";
|
|
||||||
return "movt.s\t%0, %2, %1";
|
|
||||||
case 3:
|
|
||||||
if (isEq) return "movt.s\t%0, %3, %1";
|
|
||||||
return "movf.s\t%0, %3, %1";
|
|
||||||
default:
|
|
||||||
gcc_unreachable ();
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
[(set_attr "type" "move,move,move,move")
|
[(set_attr "type" "move,move,move,move")
|
||||||
(set_attr "mode" "SF")
|
(set_attr "mode" "SF")
|
||||||
@ -1928,32 +1476,12 @@
|
|||||||
|
|
||||||
;; Floating-point comparisons.
|
;; Floating-point comparisons.
|
||||||
|
|
||||||
(define_insn "seq_sf"
|
(define_insn "s<code>_sf"
|
||||||
[(set (match_operand:CC 0 "register_operand" "=b")
|
[(set (match_operand:CC 0 "register_operand" "=b")
|
||||||
(eq:CC (match_operand:SF 1 "register_operand" "f")
|
(any_scc_sf:CC (match_operand:SF 1 "register_operand" "f")
|
||||||
(match_operand:SF 2 "register_operand" "f")))]
|
(match_operand:SF 2 "register_operand" "f")))]
|
||||||
"TARGET_HARD_FLOAT"
|
"TARGET_HARD_FLOAT"
|
||||||
"oeq.s\t%0, %1, %2"
|
"o<code>.s\t%0, %1, %2"
|
||||||
[(set_attr "type" "farith")
|
|
||||||
(set_attr "mode" "BL")
|
|
||||||
(set_attr "length" "3")])
|
|
||||||
|
|
||||||
(define_insn "slt_sf"
|
|
||||||
[(set (match_operand:CC 0 "register_operand" "=b")
|
|
||||||
(lt:CC (match_operand:SF 1 "register_operand" "f")
|
|
||||||
(match_operand:SF 2 "register_operand" "f")))]
|
|
||||||
"TARGET_HARD_FLOAT"
|
|
||||||
"olt.s\t%0, %1, %2"
|
|
||||||
[(set_attr "type" "farith")
|
|
||||||
(set_attr "mode" "BL")
|
|
||||||
(set_attr "length" "3")])
|
|
||||||
|
|
||||||
(define_insn "sle_sf"
|
|
||||||
[(set (match_operand:CC 0 "register_operand" "=b")
|
|
||||||
(le:CC (match_operand:SF 1 "register_operand" "f")
|
|
||||||
(match_operand:SF 2 "register_operand" "f")))]
|
|
||||||
"TARGET_HARD_FLOAT"
|
|
||||||
"ole.s\t%0, %1, %2"
|
|
||||||
[(set_attr "type" "farith")
|
[(set_attr "type" "farith")
|
||||||
(set_attr "mode" "BL")
|
(set_attr "mode" "BL")
|
||||||
(set_attr "length" "3")])
|
(set_attr "length" "3")])
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user