[AArch64] Add vcvt(_high)?_f32_f16 intrinsics, with BE RTL fix
gcc/: * config/aarch64/aarch64-simd.md (aarch64_simd_vec_unpacks_lo_<mode>, aarch64_simd_vec_unpacks_hi_<mode>): New insn. (vec_unpacks_lo_v4sf, vec_unpacks_hi_v4sf): Delete insn. (vec_unpacks_lo_<mode>, vec_unpacks_hi_<mode>): New expand. (aarch64_float_extend_lo_v2df): Rename to... (aarch64_float_extend_lo_<Vwide>): this, using VDF and so adding V4SF. * config/aarch64/aarch64-simd-builtins.def (vec_unpacks_hi): Add v8hf. (float_extend_lo): Add v4sf. * config/aarch64/arm_neon.h (vcvt_f32_f16, vcvt_high_f32_f16): New. * config/aarch64/iterators.md (VQ_HSF): New iterator. (VWIDE, Vwtype, Vhalftype): Add V8HF, V4SF. (Vwide): New mode_attr. From-SVN: r227551
This commit is contained in:
Alan Lawrence
Alan Lawrence
parent
862abc04be
commit
03873eb983
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@ -1,3 +1,20 @@
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2015-09-08 Alan Lawrence <alan.lawrence@arm.com>
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* config/aarch64/aarch64-simd.md (aarch64_simd_vec_unpacks_lo_<mode>,
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aarch64_simd_vec_unpacks_hi_<mode>): New insn.
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(vec_unpacks_lo_v4sf, vec_unpacks_hi_v4sf): Delete insn.
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(vec_unpacks_lo_<mode>, vec_unpacks_hi_<mode>): New expand.
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(aarch64_float_extend_lo_v2df): Rename to...
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(aarch64_float_extend_lo_<Vwide>): this, using VDF and so adding V4SF.
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* config/aarch64/aarch64-simd-builtins.def (vec_unpacks_hi): Add v8hf.
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(float_extend_lo): Add v4sf.
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* config/aarch64/arm_neon.h (vcvt_f32_f16, vcvt_high_f32_f16): New.
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* config/aarch64/iterators.md (VQ_HSF): New iterator.
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(VWIDE, Vwtype, Vhalftype): Add V8HF, V4SF.
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(Vwide): New mode_attr.
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2015-09-08 Alan Lawrence <alan.lawrence@arm.com>
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* config/aarch64/aarch64-simd.md (aarch64_simd_dup<mode>,
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@ -361,11 +361,12 @@
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BUILTIN_VSDQ_I_DI (UNOP, abs, 0)
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BUILTIN_VDQF (UNOP, abs, 2)
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VAR1 (UNOP, vec_unpacks_hi_, 10, v4sf)
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BUILTIN_VQ_HSF (UNOP, vec_unpacks_hi_, 10)
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VAR1 (BINOP, float_truncate_hi_, 0, v4sf)
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VAR1 (BINOP, float_truncate_hi_, 0, v8hf)
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VAR1 (UNOP, float_extend_lo_, 0, v2df)
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VAR1 (UNOP, float_extend_lo_, 0, v4sf)
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BUILTIN_VDF (UNOP, float_truncate_lo_, 0)
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/* Implemented by aarch64_ld1<VALL_F16:mode>. */
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@ -1692,36 +1692,57 @@
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;; Float widening operations.
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(define_insn "vec_unpacks_lo_v4sf"
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[(set (match_operand:V2DF 0 "register_operand" "=w")
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(float_extend:V2DF
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(vec_select:V2SF
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(match_operand:V4SF 1 "register_operand" "w")
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(parallel [(const_int 0) (const_int 1)])
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)))]
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(define_insn "aarch64_simd_vec_unpacks_lo_<mode>"
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[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
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(float_extend:<VWIDE> (vec_select:<VHALF>
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(match_operand:VQ_HSF 1 "register_operand" "w")
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(match_operand:VQ_HSF 2 "vect_par_cnst_lo_half" "")
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)))]
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"TARGET_SIMD"
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"fcvtl\\t%0.2d, %1.2s"
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"fcvtl\\t%0.<Vwtype>, %1.<Vhalftype>"
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[(set_attr "type" "neon_fp_cvt_widen_s")]
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)
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(define_insn "aarch64_float_extend_lo_v2df"
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[(set (match_operand:V2DF 0 "register_operand" "=w")
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(float_extend:V2DF
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(match_operand:V2SF 1 "register_operand" "w")))]
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(define_expand "vec_unpacks_lo_<mode>"
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[(match_operand:<VWIDE> 0 "register_operand" "")
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(match_operand:VQ_HSF 1 "register_operand" "")]
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"TARGET_SIMD"
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"fcvtl\\t%0.2d, %1.2s"
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{
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, false);
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emit_insn (gen_aarch64_simd_vec_unpacks_lo_<mode> (operands[0],
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operands[1], p));
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DONE;
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}
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)
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(define_insn "aarch64_simd_vec_unpacks_hi_<mode>"
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[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
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(float_extend:<VWIDE> (vec_select:<VHALF>
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(match_operand:VQ_HSF 1 "register_operand" "w")
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(match_operand:VQ_HSF 2 "vect_par_cnst_hi_half" "")
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)))]
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"TARGET_SIMD"
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"fcvtl2\\t%0.<Vwtype>, %1.<Vtype>"
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[(set_attr "type" "neon_fp_cvt_widen_s")]
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)
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(define_insn "vec_unpacks_hi_v4sf"
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[(set (match_operand:V2DF 0 "register_operand" "=w")
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(float_extend:V2DF
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(vec_select:V2SF
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(match_operand:V4SF 1 "register_operand" "w")
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(parallel [(const_int 2) (const_int 3)])
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)))]
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(define_expand "vec_unpacks_hi_<mode>"
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[(match_operand:<VWIDE> 0 "register_operand" "")
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(match_operand:VQ_HSF 1 "register_operand" "")]
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"TARGET_SIMD"
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"fcvtl2\\t%0.2d, %1.4s"
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{
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
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emit_insn (gen_aarch64_simd_vec_unpacks_lo_<mode> (operands[0],
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operands[1], p));
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DONE;
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}
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)
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(define_insn "aarch64_float_extend_lo_<Vwide>"
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[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
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(float_extend:<VWIDE>
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(match_operand:VDF 1 "register_operand" "w")))]
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"TARGET_SIMD"
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"fcvtl\\t%0<Vmwtype>, %1<Vmtype>"
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[(set_attr "type" "neon_fp_cvt_widen_s")]
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)
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@ -6025,10 +6025,6 @@ vaddlvq_u32 (uint32x4_t a)
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result; \
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})
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/* vcvt_f32_f16 not supported */
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/* vcvt_high_f32_f16 not supported */
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#define vcvt_n_f32_s32(a, b) \
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__extension__ \
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({ \
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@ -13436,6 +13432,12 @@ vcvt_high_f32_f64 (float32x2_t __a, float64x2_t __b)
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/* vcvt (float -> double). */
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__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
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vcvt_f32_f16 (float16x4_t __a)
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{
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return __builtin_aarch64_float_extend_lo_v4sf (__a);
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}
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__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
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vcvt_f64_f32 (float32x2_t __a)
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{
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@ -13443,6 +13445,12 @@ vcvt_f64_f32 (float32x2_t __a)
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return __builtin_aarch64_float_extend_lo_v2df (__a);
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}
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__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
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vcvt_high_f32_f16 (float16x8_t __a)
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{
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return __builtin_aarch64_vec_unpacks_hi_v8hf (__a);
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}
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__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
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vcvt_high_f64_f32 (float32x4_t __a)
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{
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@ -94,6 +94,9 @@
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;; Vector single Float modes.
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(define_mode_iterator VDQSF [V2SF V4SF])
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;; Quad vector Float modes with half/single elements.
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(define_mode_iterator VQ_HSF [V8HF V4SF])
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;; Modes suitable to use as the return type of a vcond expression.
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(define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI])
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@ -492,14 +495,18 @@
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(V2SI "V2DI") (V16QI "V8HI")
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(V8HI "V4SI") (V4SI "V2DI")
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(HI "SI") (SI "DI")
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(V8HF "V4SF") (V4SF "V2DF")
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(V4HF "V4SF") (V2SF "V2DF")]
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)
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;; Widened mode register suffixes for VD_BHSI/VQW.
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;; Widened modes of vector modes, lowercase
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(define_mode_attr Vwide [(V2SF "v2df") (V4HF "v4sf")])
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;; Widened mode register suffixes for VD_BHSI/VQW/VQ_HSF.
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(define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s")
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(V2SI "2d") (V16QI "8h")
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(V8HI "4s") (V4SI "2d")])
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(V8HI "4s") (V4SI "2d")
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(V8HF "4s") (V4SF "2d")])
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;; Widened mode register suffixes for VDW/VQW.
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(define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s")
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@ -508,9 +515,10 @@
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(V4HF ".4s") (V2SF ".2d")
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(SI "") (HI "")])
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;; Lower part register suffixes for VQW.
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;; Lower part register suffixes for VQW/VQ_HSF.
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(define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h")
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(V4SI "2s")])
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(V4SI "2s") (V8HF "4h")
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(V4SF "2s")])
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;; Define corresponding core/FP element mode for each vector mode.
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(define_mode_attr vw [(V8QI "w") (V16QI "w")
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