i386.md (*movti_internal): Substitute Ye constraint with Yd constraint.
* config/i386/i386.md (*movti_internal): Substitute Ye constraint with Yd constraint. Set "preferred_for_speed" attribute from TARGET_INTER_UNIT_MOVES_{FROM,TO}_VEC for alternatives with Yd constraint. (*movdi_internal): Ditto. (movti_interunit splitters): Remove TARGET_INTER_UNIT_MOVES_{FROM,TO}_VEC from insn condition. (movdi_interunit splitters): Ditto. * config/i386/constraints.md (Ye): Remove. (Yd): Do not depend on TARGET_INTER_UNIT_MOVES_{FROM,TO}_VEC. From-SVN: r259701
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@ -1,3 +1,16 @@
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2018-04-27 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.md (*movti_internal): Substitute Ye constraint
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with Yd constraint. Set "preferred_for_speed" attribute from
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TARGET_INTER_UNIT_MOVES_{FROM,TO}_VEC for alternatives
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with Yd constraint.
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(*movdi_internal): Ditto.
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(movti_interunit splitters): Remove
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TARGET_INTER_UNIT_MOVES_{FROM,TO}_VEC from insn condition.
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(movdi_interunit splitters): Ditto.
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* config/i386/constraints.md (Ye): Remove.
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(Yd): Do not depend on TARGET_INTER_UNIT_MOVES_{FROM,TO}_VEC.
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2018-04-27 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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PR target/85512
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@ -29,7 +42,7 @@
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2018-04-26 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.md ("isa" attribute): Add x64_sse2.
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("enabled" attribute): Handle "isa" attribute.
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("enabled" attribute): Handle x64_sse2 "isa" attribute.
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(*movdi_internal): Substitute Yi and Yj constraint with x
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and Ym and Yn constraint with y constraint. Update "isa"
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attribute and set "preferred_for_speed" attribute from
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@ -99,10 +99,8 @@
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;; We use the Y prefix to denote any number of conditional register sets:
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;; z First SSE register.
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;; d any EVEX encodable SSE register for AVX512BW target or any SSE register
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;; for SSE4_1 target, when inter-unit moves to SSE register are enabled
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;; e any EVEX encodable SSE register for AVX512BW target or any SSE register
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;; for SSE4_1 target, when inter-unit moves from SSE register are enabled
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;; d any EVEX encodable SSE register for AVX512BW target or
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;; any SSE register for SSE4_1 target.
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;; p Integer register when TARGET_PARTIAL_REG_STALL is disabled
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;; a Integer register when zero extensions with AND are disabled
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;; b Any register that can be used as the GOT base when calling
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@ -120,20 +118,8 @@
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"First SSE register (@code{%xmm0}).")
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(define_register_constraint "Yd"
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"TARGET_INTER_UNIT_MOVES_TO_VEC
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? (TARGET_AVX512DQ
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? ALL_SSE_REGS
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: (TARGET_SSE4_1 ? SSE_REGS : NO_REGS))
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: NO_REGS"
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"@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target, when inter-unit moves to vector registers are enabled.")
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(define_register_constraint "Ye"
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"TARGET_INTER_UNIT_MOVES_FROM_VEC
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? (TARGET_AVX512DQ
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? ALL_SSE_REGS
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: (TARGET_SSE4_1 ? SSE_REGS : NO_REGS))
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: NO_REGS"
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"@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target, when inter-unit moves from vector registers are enabled.")
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"TARGET_AVX512DQ ? ALL_SSE_REGS : TARGET_SSE4_1 ? SSE_REGS : NO_REGS"
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"@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target.")
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(define_register_constraint "Yp"
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"TARGET_PARTIAL_REG_STALL ? NO_REGS : GENERAL_REGS"
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@ -2123,7 +2123,7 @@
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(define_insn "*movti_internal"
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[(set (match_operand:TI 0 "nonimmediate_operand" "=!r ,o ,v,v ,v ,m,?r,?Yd")
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(match_operand:TI 1 "general_operand" "riFo,re,C,BC,vm,v,Ye,r"))]
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(match_operand:TI 1 "general_operand" "riFo,re,C,BC,vm,v,Yd,r"))]
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"(TARGET_64BIT
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&& !(MEM_P (operands[0]) && MEM_P (operands[1])))
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|| (TARGET_SSE
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@ -2203,12 +2203,19 @@
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(match_test "optimize_function_for_size_p (cfun)")
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(const_string "V4SF")
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]
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(const_string "TI")))])
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(const_string "TI")))
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(set (attr "preferred_for_speed")
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(cond [(eq_attr "alternative" "6")
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(symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
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(eq_attr "alternative" "7")
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(symbol_ref "TARGET_INTER_UNIT_MOVES_TO_VEC")
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]
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(symbol_ref "true")))])
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(define_split
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[(set (match_operand:TI 0 "sse_reg_operand")
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(match_operand:TI 1 "general_reg_operand"))]
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"TARGET_64BIT && TARGET_SSE4_1 && TARGET_INTER_UNIT_MOVES_TO_VEC
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"TARGET_64BIT && TARGET_SSE4_1
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&& reload_completed"
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[(set (match_dup 2)
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(vec_merge:V2DI
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@ -2227,7 +2234,7 @@
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[(set (match_operand:DI 0 "nonimmediate_operand"
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"=r ,o ,r,r ,r,m ,*y,*y,?*y,?m,?r,?*y,*v,*v,*v,m ,m,?r ,?*Yd,?r,?*v,?*y,?*x,*k,*k ,*r,*m")
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(match_operand:DI 1 "general_operand"
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"riFo,riF,Z,rem,i,re,C ,*y,m ,*y,*y,r ,C ,*v,m ,*v,v,*Ye,r ,*v,r ,*x ,*y ,*r,*km,*k,*k"))]
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"riFo,riF,Z,rem,i,re,C ,*y,m ,*y,*y,r ,C ,*v,m ,*v,v,*Yd,r ,*v,r ,*x ,*y ,*r,*km,*k,*k"))]
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"!(MEM_P (operands[0]) && MEM_P (operands[1]))"
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{
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switch (get_attr_type (insn))
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@ -2379,9 +2386,9 @@
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]
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(const_string "DI")))
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(set (attr "preferred_for_speed")
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(cond [(eq_attr "alternative" "10,19")
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(cond [(eq_attr "alternative" "10,17,19")
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(symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
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(eq_attr "alternative" "11,20")
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(eq_attr "alternative" "11,18,20")
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(symbol_ref "TARGET_INTER_UNIT_MOVES_TO_VEC")
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]
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(symbol_ref "true")))
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@ -2402,7 +2409,7 @@
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(define_split
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[(set (match_operand:<DWI> 0 "general_reg_operand")
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(match_operand:<DWI> 1 "sse_reg_operand"))]
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"TARGET_SSE4_1 && TARGET_INTER_UNIT_MOVES_FROM_VEC
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"TARGET_SSE4_1
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&& reload_completed"
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[(set (match_dup 2)
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(vec_select:DWIH
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(define_split
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[(set (match_operand:DI 0 "sse_reg_operand")
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(match_operand:DI 1 "general_reg_operand"))]
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"!TARGET_64BIT && TARGET_SSE4_1 && TARGET_INTER_UNIT_MOVES_TO_VEC
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"!TARGET_64BIT && TARGET_SSE4_1
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&& reload_completed"
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[(set (match_dup 2)
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(vec_merge:V4SI
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