predicates.md (input_operand): Do not consider TImode constants as 1-instruction integer constants.
* config/sparc/predicates.md (input_operand): Do not consider TImode constants as 1-instruction integer constants. Use register_or_zero_operand instead of register_operand and tidy up. * config/sparc/sparc.md (movti): New expander. (movti_insn_sp64): New instruction. (movti_insn_sp64_hq): Likewise. (TImode splitters): New splitters. * config/sparc/sparc.c (sparc_expand_move) <TImode>: New case. (sparc_legitimate_address_p): Return 0 for REG+REG in TImode. * config/sparc/sparc-protos.h (arith_double_4096_operand): Delete. (arith_4096_operand): Likewise. (zero_operand): Likewise. (fp_zero_operand): Likewise. (reg_or_0_operand): Likewise. From-SVN: r191283
This commit is contained in:
Eric Botcazou
Eric Botcazou
parent
12308bc61d
commit
03c432bd84
@ -1,3 +1,21 @@
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2012-09-13 Eric Botcazou <ebotcazou@adacore.com>
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* config/sparc/predicates.md (input_operand): Do not consider TImode
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constants as 1-instruction integer constants.
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Use register_or_zero_operand instead of register_operand and tidy up.
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* config/sparc/sparc.md (movti): New expander.
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(movti_insn_sp64): New instruction.
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(movti_insn_sp64_hq): Likewise.
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(TImode splitters): New splitters.
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* config/sparc/sparc.c (sparc_expand_move) <TImode>: New case.
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(sparc_legitimate_address_p): Return 0 for REG+REG in TImode.
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* config/sparc/sparc-protos.h (arith_double_4096_operand): Delete.
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(arith_4096_operand): Likewise.
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(zero_operand): Likewise.
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(fp_zero_operand): Likewise.
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(reg_or_0_operand): Likewise.
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2012-09-13 Jakub Jelinek <jakub@redhat.com>
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* configure.ac (CXXFLAGS): Remove -O2 when not bootstrapping.
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@ -357,7 +357,7 @@
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(define_predicate "arith_add_operand"
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(ior (match_operand 0 "arith_operand")
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(match_operand 0 "const_4096_operand")))
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;; Return true if OP is suitable as second double operand for add/sub.
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(define_predicate "arith_double_add_operand"
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(match_code "const_int,const_double,reg,subreg")
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@ -427,6 +427,7 @@
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/* Allow any 1-instruction integer constant. */
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if (mclass == MODE_INT
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&& mode != TImode
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&& (small_int_operand (op, mode) || const_high_operand (op, mode)))
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return true;
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@ -440,12 +441,10 @@
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if (mclass == MODE_FLOAT && GET_CODE (op) == CONST_DOUBLE)
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return true;
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if (mclass == MODE_VECTOR_INT && GET_CODE (op) == CONST_VECTOR
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&& (const_zero_operand (op, mode)
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|| const_all_ones_operand (op, mode)))
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if (mclass == MODE_VECTOR_INT && const_all_ones_operand (op, mode))
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return true;
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if (register_operand (op, mode))
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if (register_or_zero_operand (op, mode))
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return true;
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/* If this is a SUBREG, look inside so that we handle paradoxical ones. */
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@ -82,11 +82,6 @@ extern const char *output_probe_stack_range (rtx, rtx);
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extern bool emit_scc_insn (rtx []);
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extern void emit_conditional_branch_insn (rtx []);
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extern int mems_ok_for_ldd_peep (rtx, rtx, rtx);
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extern int arith_double_4096_operand (rtx, enum machine_mode);
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extern int arith_4096_operand (rtx, enum machine_mode);
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extern int zero_operand (rtx, enum machine_mode);
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extern int fp_zero_operand (rtx, enum machine_mode);
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extern int reg_or_0_operand (rtx, enum machine_mode);
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extern int empty_delay_slot (rtx);
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extern int eligible_for_return_delay (rtx);
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extern int eligible_for_sibcall_delay (rtx);
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@ -1465,6 +1465,18 @@ sparc_expand_move (enum machine_mode mode, rtx *operands)
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sparc_emit_set_const64 (operands[0], operands[1]);
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return true;
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case TImode:
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{
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rtx high, low;
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/* TImode isn't available in 32-bit mode. */
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split_double (operands[1], &high, &low);
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emit_insn (gen_movdi (operand_subword (operands[0], 0, 0, TImode),
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high));
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emit_insn (gen_movdi (operand_subword (operands[0], 1, 0, TImode),
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low));
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}
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return true;
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default:
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gcc_unreachable ();
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}
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@ -3492,6 +3504,10 @@ sparc_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
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&& ! (TARGET_ARCH64 && TARGET_HARD_QUAD))
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return 0;
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/* Likewise for TImode, but in all cases. */
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if (mode == TImode)
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return 0;
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/* We prohibit REG + REG on ARCH32 if not optimizing for
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DFmode/DImode because then mem_min_alignment is likely to be zero
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after reload and the forced split would lack a matching splitter
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@ -2034,6 +2034,164 @@
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DONE;
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})
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(define_expand "movti"
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[(set (match_operand:TI 0 "nonimmediate_operand" "")
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(match_operand:TI 1 "general_operand" ""))]
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"TARGET_ARCH64"
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{
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if (sparc_expand_move (TImode, operands))
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DONE;
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})
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;; We need to prevent reload from splitting TImode moves, because it
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;; might decide to overwrite a pointer with the value it points to.
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;; In that case we have to do the loads in the appropriate order so
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;; that the pointer is not destroyed too early.
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(define_insn "*movti_insn_sp64"
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[(set (match_operand:TI 0 "nonimmediate_operand" "=r , o,?*e,?o,b")
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(match_operand:TI 1 "input_operand" "roJ,rJ, eo, e,J"))]
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"TARGET_ARCH64
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&& ! TARGET_HARD_QUAD
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&& (register_operand (operands[0], TImode)
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|| register_or_zero_operand (operands[1], TImode))"
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"#"
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[(set_attr "length" "2,2,2,2,2")
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(set_attr "cpu_feature" "*,*,fpu,fpu,vis")])
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(define_insn "*movti_insn_sp64_hq"
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[(set (match_operand:TI 0 "nonimmediate_operand" "=r , o,?*e,?*e,?m,b")
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(match_operand:TI 1 "input_operand" "roJ,rJ, e, m, e,J"))]
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"TARGET_ARCH64
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&& TARGET_HARD_QUAD
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&& (register_operand (operands[0], TImode)
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|| register_or_zero_operand (operands[1], TImode))"
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"@
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#
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#
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fmovq\t%1, %0
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ldq\t%1, %0
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stq\t%1, %0
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#"
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[(set_attr "type" "*,*,fpmove,fpload,fpstore,*")
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(set_attr "length" "2,2,*,*,*,2")])
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;; Now all the splits to handle multi-insn TI mode moves.
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(define_split
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[(set (match_operand:TI 0 "register_operand" "")
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(match_operand:TI 1 "register_operand" ""))]
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"reload_completed
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&& ((TARGET_FPU
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&& ! TARGET_HARD_QUAD)
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|| (! fp_register_operand (operands[0], TImode)
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&& ! fp_register_operand (operands[1], TImode)))"
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[(clobber (const_int 0))]
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{
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rtx set_dest = operands[0];
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rtx set_src = operands[1];
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rtx dest1, dest2;
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rtx src1, src2;
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dest1 = gen_highpart (DImode, set_dest);
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dest2 = gen_lowpart (DImode, set_dest);
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src1 = gen_highpart (DImode, set_src);
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src2 = gen_lowpart (DImode, set_src);
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/* Now emit using the real source and destination we found, swapping
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the order if we detect overlap. */
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if (reg_overlap_mentioned_p (dest1, src2))
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{
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emit_insn (gen_movdi (dest2, src2));
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emit_insn (gen_movdi (dest1, src1));
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}
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else
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{
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emit_insn (gen_movdi (dest1, src1));
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emit_insn (gen_movdi (dest2, src2));
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}
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DONE;
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})
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(define_split
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[(set (match_operand:TI 0 "nonimmediate_operand" "")
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(match_operand:TI 1 "const_zero_operand" ""))]
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"reload_completed"
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[(clobber (const_int 0))]
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{
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rtx set_dest = operands[0];
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rtx dest1, dest2;
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switch (GET_CODE (set_dest))
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{
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case REG:
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dest1 = gen_highpart (DImode, set_dest);
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dest2 = gen_lowpart (DImode, set_dest);
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break;
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case MEM:
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dest1 = adjust_address (set_dest, DImode, 0);
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dest2 = adjust_address (set_dest, DImode, 8);
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break;
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default:
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gcc_unreachable ();
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}
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emit_insn (gen_movdi (dest1, const0_rtx));
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emit_insn (gen_movdi (dest2, const0_rtx));
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DONE;
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})
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(define_split
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[(set (match_operand:TI 0 "register_operand" "")
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(match_operand:TI 1 "memory_operand" ""))]
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"reload_completed
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&& offsettable_memref_p (operands[1])
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&& (! TARGET_HARD_QUAD
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|| ! fp_register_operand (operands[0], TImode))"
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[(clobber (const_int 0))]
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{
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rtx word0 = adjust_address (operands[1], DImode, 0);
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rtx word1 = adjust_address (operands[1], DImode, 8);
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rtx set_dest, dest1, dest2;
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set_dest = operands[0];
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dest1 = gen_highpart (DImode, set_dest);
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dest2 = gen_lowpart (DImode, set_dest);
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/* Now output, ordering such that we don't clobber any registers
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mentioned in the address. */
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if (reg_overlap_mentioned_p (dest1, word1))
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{
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emit_insn (gen_movdi (dest2, word1));
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emit_insn (gen_movdi (dest1, word0));
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}
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else
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{
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emit_insn (gen_movdi (dest1, word0));
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emit_insn (gen_movdi (dest2, word1));
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}
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DONE;
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})
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(define_split
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[(set (match_operand:TI 0 "memory_operand" "")
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(match_operand:TI 1 "register_operand" ""))]
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"reload_completed
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&& offsettable_memref_p (operands[0])
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&& (! TARGET_HARD_QUAD
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|| ! fp_register_operand (operands[1], TImode))"
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[(clobber (const_int 0))]
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{
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rtx set_src = operands[1];
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emit_insn (gen_movdi (adjust_address (operands[0], DImode, 0),
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gen_highpart (DImode, set_src)));
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emit_insn (gen_movdi (adjust_address (operands[0], DImode, 8),
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gen_lowpart (DImode, set_src)));
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DONE;
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})
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;; Floating point move instructions
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@ -2477,7 +2635,7 @@
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dest2 = adjust_address (set_dest, DFmode, 8);
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break;
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default:
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gcc_unreachable ();
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gcc_unreachable ();
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}
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emit_insn (gen_movdf (dest1, CONST0_RTX (DFmode)));
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