arm.md (negdi_extendsidi): New pattern.
2013-04-05 Greta Yorsh <Greta.Yorsh@arm.com> gcc/ * config/arm/arm.md (negdi_extendsidi): New pattern. (negdi_zero_extendsidi): Likewise. gcc/testsuite * gcc.target/arm/negdi-1.c: New test. * gcc.target/arm/negdi-2.c: Likewise. * gcc.target/arm/negdi-3.c: Likewise. * gcc.target/arm/negdi-4.c: Likewise. From-SVN: r197526
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Greta Yorsh
Greta Yorsh
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@ -1,3 +1,8 @@
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2013-04-05 Greta Yorsh <Greta.Yorsh@arm.com>
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* config/arm/arm.md (negdi_extendsidi): New pattern.
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(negdi_zero_extendsidi): Likewise.
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2013-04-05 Greta Yorsh <Greta.Yorsh@arm.com>
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2013-04-05 Greta Yorsh <Greta.Yorsh@arm.com>
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* config/arm/arm.md (andsi_iorsi3_notsi): Convert define_insn into
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* config/arm/arm.md (andsi_iorsi3_notsi): Convert define_insn into
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@ -4344,6 +4344,73 @@
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
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"")
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"")
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;; Negate an extended 32-bit value.
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(define_insn_and_split "*negdi_extendsidi"
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[(set (match_operand:DI 0 "s_register_operand" "=r,&r,l,&l")
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(neg:DI (sign_extend:DI (match_operand:SI 1 "s_register_operand" "0,r,0,l"))))
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(clobber (reg:CC CC_REGNUM))]
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"TARGET_32BIT"
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"#" ; rsb\\t%Q0, %1, #0\;asr\\t%R0, %Q0, #31
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"&& reload_completed"
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[(const_int 0)]
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{
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operands[2] = gen_highpart (SImode, operands[0]);
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operands[0] = gen_lowpart (SImode, operands[0]);
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rtx tmp = gen_rtx_SET (VOIDmode,
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operands[0],
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gen_rtx_MINUS (SImode,
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const0_rtx,
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operands[1]));
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if (TARGET_ARM)
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{
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emit_insn (tmp);
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}
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else
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{
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/* Set the flags, to emit the short encoding in Thumb2. */
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rtx flags = gen_rtx_SET (VOIDmode,
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gen_rtx_REG (CCmode, CC_REGNUM),
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gen_rtx_COMPARE (CCmode,
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const0_rtx,
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operands[1]));
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emit_insn (gen_rtx_PARALLEL (VOIDmode,
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gen_rtvec (2,
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flags,
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tmp)));
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}
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emit_insn (gen_rtx_SET (VOIDmode,
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operands[2],
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gen_rtx_ASHIFTRT (SImode,
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operands[0],
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GEN_INT (31))));
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DONE;
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}
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[(set_attr "length" "8,8,4,4")
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(set_attr "arch" "a,a,t2,t2")]
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)
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(define_insn_and_split "*negdi_zero_extendsidi"
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[(set (match_operand:DI 0 "s_register_operand" "=r,&r")
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(neg:DI (zero_extend:DI (match_operand:SI 1 "s_register_operand" "0,r"))))
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(clobber (reg:CC CC_REGNUM))]
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"TARGET_32BIT"
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"#" ; "rsbs\\t%Q0, %1, #0\;sbc\\t%R0,%R0,%R0"
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;; Don't care what register is input to sbc,
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;; since we just just need to propagate the carry.
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"&& reload_completed"
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[(parallel [(set (reg:CC CC_REGNUM)
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(compare:CC (const_int 0) (match_dup 1)))
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(set (match_dup 0) (minus:SI (const_int 0) (match_dup 1)))])
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(set (match_dup 2) (minus:SI (minus:SI (match_dup 2) (match_dup 2))
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(ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
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{
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operands[2] = gen_highpart (SImode, operands[0]);
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operands[0] = gen_lowpart (SImode, operands[0]);
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}
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[(set_attr "conds" "clob")
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(set_attr "length" "8")] ;; length in thumb is 4
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)
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;; abssi2 doesn't really clobber the condition codes if a different register
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;; abssi2 doesn't really clobber the condition codes if a different register
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;; is being set. To keep things simple, assume during rtl manipulations that
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;; is being set. To keep things simple, assume during rtl manipulations that
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;; it does, but tell the final scan operator the truth. Similarly for
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;; it does, but tell the final scan operator the truth. Similarly for
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@ -1,3 +1,10 @@
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2013-04-05 Greta Yorsh <Greta.Yorsh@arm.com>
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* gcc.target/arm/negdi-1.c: New test.
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* gcc.target/arm/negdi-2.c: Likewise.
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* gcc.target/arm/negdi-3.c: Likewise.
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* gcc.target/arm/negdi-4.c: Likewise.
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2013-04-05 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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2013-04-05 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* lib/target-supports.exp (add_options_for_arm_v8_neon):
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* lib/target-supports.exp (add_options_for_arm_v8_neon):
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17
gcc/testsuite/gcc.target/arm/negdi-1.c
Normal file
17
gcc/testsuite/gcc.target/arm/negdi-1.c
Normal file
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/* { dg-do compile } */
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/* { dg-require-effective-target arm32 } */
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/* { dg-options "-O2" } */
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signed long long extendsidi_negsi (signed int x)
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{
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return -x;
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}
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/*
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Expected output:
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rsb r0, r0, #0
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mov r1, r0, asr #31
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*/
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/* { dg-final { scan-assembler-times "rsb" 1 { target { arm_nothumb } } } } */
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/* { dg-final { scan-assembler-times "negs\\t" 1 { target { ! { arm_nothumb } } } } } */
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/* { dg-final { scan-assembler-times "asr" 1 } } */
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16
gcc/testsuite/gcc.target/arm/negdi-2.c
Normal file
16
gcc/testsuite/gcc.target/arm/negdi-2.c
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/* { dg-do compile } */
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/* { dg-require-effective-target arm32 } */
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/* { dg-options "-O2" } */
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signed long long zero_extendsidi_negsi (unsigned int x)
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{
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return -x;
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}
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/*
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Expected output:
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rsb r0, r0, #0
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mov r1, #0
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*/
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/* { dg-final { scan-assembler-times "rsb\\tr0, r0, #0" 1 { target { arm_nothumb } } } } */
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/* { dg-final { scan-assembler-times "negs\\tr0, r0" 1 { target { ! arm_nothumb } } } } */
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/* { dg-final { scan-assembler-times "mov" 1 } } */
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17
gcc/testsuite/gcc.target/arm/negdi-3.c
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17
gcc/testsuite/gcc.target/arm/negdi-3.c
Normal file
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/* { dg-do compile } */
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/* { dg-require-effective-target arm32 } */
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/* { dg-options "-O2" } */
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signed long long negdi_zero_extendsidi (unsigned int x)
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{
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return -((signed long long) x);
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}
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/*
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Expected output:
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rsbs r0, r0, #0
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sbc r1, r1, r1
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*/
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/* { dg-final { scan-assembler-times "rsb" 1 } } */
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/* { dg-final { scan-assembler-times "sbc" 1 } } */
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/* { dg-final { scan-assembler-times "mov" 0 } } */
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/* { dg-final { scan-assembler-times "rsc" 0 } } */
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16
gcc/testsuite/gcc.target/arm/negdi-4.c
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gcc/testsuite/gcc.target/arm/negdi-4.c
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/* { dg-do compile } */
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/* { dg-require-effective-target arm32 } */
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/* { dg-options "-O2" } */
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signed long long negdi_extendsidi (signed int x)
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{
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return -((signed long long) x);
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}
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/*
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Expected output:
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rsbs r0, r0, #0
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mov r1, r0, asr #31
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*/
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/* { dg-final { scan-assembler-times "rsb" 1 } } */
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/* { dg-final { scan-assembler-times "asr" 1 } } */
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/* { dg-final { scan-assembler-times "rsc" 0 } } */
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