Fix constraints.
2011-06-28 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org> * config/arm/vfp.md ("*divsf3_vfp"): Replace '+' constraint modifier with '=' constraint modifier. (*divdf3_vfp): Likewise. ("*mulsf3_vfp"): Likewise. ("*muldf3_vfp"): Likewise. ("*mulsf3negsf_vfp"): Likewise. ("*muldf3negdf_vfp"): Likewise. From-SVN: r175588
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@ -1,3 +1,13 @@
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2011-06-28 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
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* config/arm/vfp.md ("*divsf3_vfp"): Replace '+' constraint modifier
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with '=' constraint modifier.
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(*divdf3_vfp): Likewise.
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("*mulsf3_vfp"): Likewise.
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("*muldf3_vfp"): Likewise.
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("*mulsf3negsf_vfp"): Likewise.
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("*muldf3negdf_vfp"): Likewise.
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2011-06-28 Nick Clifton <nickc@redhat.com>
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* config/mn10300/mn10300.h (LINK_SPEC): Do not use linker
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@ -719,7 +719,7 @@
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;; Division insns
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(define_insn "*divsf3_vfp"
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[(set (match_operand:SF 0 "s_register_operand" "+t")
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[(set (match_operand:SF 0 "s_register_operand" "=t")
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(div:SF (match_operand:SF 1 "s_register_operand" "t")
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(match_operand:SF 2 "s_register_operand" "t")))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
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@ -729,7 +729,7 @@
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)
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(define_insn "*divdf3_vfp"
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[(set (match_operand:DF 0 "s_register_operand" "+w")
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[(set (match_operand:DF 0 "s_register_operand" "=w")
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(div:DF (match_operand:DF 1 "s_register_operand" "w")
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(match_operand:DF 2 "s_register_operand" "w")))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
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@ -742,7 +742,7 @@
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;; Multiplication insns
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(define_insn "*mulsf3_vfp"
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[(set (match_operand:SF 0 "s_register_operand" "+t")
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[(set (match_operand:SF 0 "s_register_operand" "=t")
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(mult:SF (match_operand:SF 1 "s_register_operand" "t")
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(match_operand:SF 2 "s_register_operand" "t")))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
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@ -752,7 +752,7 @@
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)
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(define_insn "*muldf3_vfp"
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[(set (match_operand:DF 0 "s_register_operand" "+w")
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[(set (match_operand:DF 0 "s_register_operand" "=w")
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(mult:DF (match_operand:DF 1 "s_register_operand" "w")
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(match_operand:DF 2 "s_register_operand" "w")))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
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@ -761,9 +761,8 @@
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(set_attr "type" "fmuld")]
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)
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(define_insn "*mulsf3negsf_vfp"
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[(set (match_operand:SF 0 "s_register_operand" "+t")
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[(set (match_operand:SF 0 "s_register_operand" "=t")
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(mult:SF (neg:SF (match_operand:SF 1 "s_register_operand" "t"))
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(match_operand:SF 2 "s_register_operand" "t")))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
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@ -773,7 +772,7 @@
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)
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(define_insn "*muldf3negdf_vfp"
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[(set (match_operand:DF 0 "s_register_operand" "+w")
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[(set (match_operand:DF 0 "s_register_operand" "=w")
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(mult:DF (neg:DF (match_operand:DF 1 "s_register_operand" "w"))
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(match_operand:DF 2 "s_register_operand" "w")))]
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"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
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