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Fix constraints.

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2011-06-28  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>

       * config/arm/vfp.md ("*divsf3_vfp"): Replace '+' constraint modifier
       with '=' constraint modifier.
       (*divdf3_vfp): Likewise.
       ("*mulsf3_vfp"): Likewise.
       ("*muldf3_vfp"): Likewise.
       ("*mulsf3negsf_vfp"): Likewise.
       ("*muldf3negdf_vfp"): Likewise.

From-SVN: r175588
This commit is contained in:
Ramana Radhakrishnan 2011-06-28 14:54:58 +00:00 committed by Ramana Radhakrishnan
parent 4a68b724cc
commit 0498a2be0d
2 changed files with 16 additions and 7 deletions
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10
gcc/ChangeLog
View File

@ -1,3 +1,13 @@
2011-06-28 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
* config/arm/vfp.md ("*divsf3_vfp"): Replace '+' constraint modifier
with '=' constraint modifier.
(*divdf3_vfp): Likewise.
("*mulsf3_vfp"): Likewise.
("*muldf3_vfp"): Likewise.
("*mulsf3negsf_vfp"): Likewise.
("*muldf3negdf_vfp"): Likewise.
2011-06-28 Nick Clifton <nickc@redhat.com> 2011-06-28 Nick Clifton <nickc@redhat.com>
* config/mn10300/mn10300.h (LINK_SPEC): Do not use linker * config/mn10300/mn10300.h (LINK_SPEC): Do not use linker

13
gcc/config/arm/vfp.md
View File

@ -719,7 +719,7 @@
;; Division insns ;; Division insns
(define_insn "*divsf3_vfp" (define_insn "*divsf3_vfp"
[(set (match_operand:SF 0 "s_register_operand" "+t") [(set (match_operand:SF 0 "s_register_operand" "=t")
(div:SF (match_operand:SF 1 "s_register_operand" "t") (div:SF (match_operand:SF 1 "s_register_operand" "t")
(match_operand:SF 2 "s_register_operand" "t")))] (match_operand:SF 2 "s_register_operand" "t")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
@ -729,7 +729,7 @@
) )
(define_insn "*divdf3_vfp" (define_insn "*divdf3_vfp"
[(set (match_operand:DF 0 "s_register_operand" "+w") [(set (match_operand:DF 0 "s_register_operand" "=w")
(div:DF (match_operand:DF 1 "s_register_operand" "w") (div:DF (match_operand:DF 1 "s_register_operand" "w")
(match_operand:DF 2 "s_register_operand" "w")))] (match_operand:DF 2 "s_register_operand" "w")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
@ -742,7 +742,7 @@
;; Multiplication insns ;; Multiplication insns
(define_insn "*mulsf3_vfp" (define_insn "*mulsf3_vfp"
[(set (match_operand:SF 0 "s_register_operand" "+t") [(set (match_operand:SF 0 "s_register_operand" "=t")
(mult:SF (match_operand:SF 1 "s_register_operand" "t") (mult:SF (match_operand:SF 1 "s_register_operand" "t")
(match_operand:SF 2 "s_register_operand" "t")))] (match_operand:SF 2 "s_register_operand" "t")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
@ -752,7 +752,7 @@
) )
(define_insn "*muldf3_vfp" (define_insn "*muldf3_vfp"
[(set (match_operand:DF 0 "s_register_operand" "+w") [(set (match_operand:DF 0 "s_register_operand" "=w")
(mult:DF (match_operand:DF 1 "s_register_operand" "w") (mult:DF (match_operand:DF 1 "s_register_operand" "w")
(match_operand:DF 2 "s_register_operand" "w")))] (match_operand:DF 2 "s_register_operand" "w")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
@ -761,9 +761,8 @@
(set_attr "type" "fmuld")] (set_attr "type" "fmuld")]
) )
(define_insn "*mulsf3negsf_vfp" (define_insn "*mulsf3negsf_vfp"
[(set (match_operand:SF 0 "s_register_operand" "+t") [(set (match_operand:SF 0 "s_register_operand" "=t")
(mult:SF (neg:SF (match_operand:SF 1 "s_register_operand" "t")) (mult:SF (neg:SF (match_operand:SF 1 "s_register_operand" "t"))
(match_operand:SF 2 "s_register_operand" "t")))] (match_operand:SF 2 "s_register_operand" "t")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
@ -773,7 +772,7 @@
) )
(define_insn "*muldf3negdf_vfp" (define_insn "*muldf3negdf_vfp"
[(set (match_operand:DF 0 "s_register_operand" "+w") [(set (match_operand:DF 0 "s_register_operand" "=w")
(mult:DF (neg:DF (match_operand:DF 1 "s_register_operand" "w")) (mult:DF (neg:DF (match_operand:DF 1 "s_register_operand" "w"))
(match_operand:DF 2 "s_register_operand" "w")))] (match_operand:DF 2 "s_register_operand" "w")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"