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i386: Introduce V2QImode vector compares [PR103861]

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Add V2QImode vector compares with SSE registers.

2022-01-10  Uroš Bizjak  <ubizjak@gmail.com>

gcc/ChangeLog:

	PR target/103861
	* config/i386/i386-expand.c (ix86_expand_int_sse_cmp):
	Handle V2QImode.
	* config/i386/mmx.md (<sat_plusminus:insn><mode>3):
	Use VI1_16_32 mode iterator.
	(*eq<mode>3): Ditto.
	(*gt<mode>3): Ditto.
	(*xop_maskcmp<mode>3): Ditto.
	(*xop_maskcmp_uns<mode>3): Ditto.
	(vec_cmp<mode><mode>): Ditto.
	(vec_cmpu<mode><mode>): Ditto.

gcc/testsuite/ChangeLog:

	PR target/103861
	* gcc.target/i386/pr103861-2.c: New test.
This commit is contained in:
Uros Bizjak 2022-01-10 20:59:02 +01:00
parent ab36b554bd
commit 04a7455560
3 changed files with 56 additions and 28 deletions
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7
gcc/config/i386/i386-expand.c
View File

@ -4444,6 +4444,12 @@ ix86_expand_int_sse_cmp (rtx dest, enum rtx_code code, rtx cop0, rtx cop1,
else if (code == GT && TARGET_SSE4_1)
gen = gen_sminv4qi3;
break;
case E_V2QImode:
if (code == GTU && TARGET_SSE2)
gen = gen_uminv2qi3;
else if (code == GT && TARGET_SSE4_1)
gen = gen_sminv2qi3;
break;
case E_V8HImode:
if (code == GTU && TARGET_SSE4_1)
gen = gen_uminv8hi3;
@ -4537,6 +4543,7 @@ ix86_expand_int_sse_cmp (rtx dest, enum rtx_code code, rtx cop0, rtx cop1,
case E_V16QImode:
case E_V8QImode:
case E_V4QImode:
case E_V2QImode:
case E_V8HImode:
case E_V4HImode:
case E_V2HImode:

56
gcc/config/i386/mmx.md
View File

@ -1824,10 +1824,10 @@
(set_attr "mode" "DI,TI,TI")])
(define_insn "*<insn><mode>3"
[(set (match_operand:VI_32 0 "register_operand" "=x,Yw")
(sat_plusminus:VI_32
(match_operand:VI_32 1 "register_operand" "<comm>0,Yw")
(match_operand:VI_32 2 "register_operand" "x,Yw")))]
[(set (match_operand:VI_16_32 0 "register_operand" "=x,Yw")
(sat_plusminus:VI_16_32
(match_operand:VI_16_32 1 "register_operand" "<comm>0,Yw")
(match_operand:VI_16_32 2 "register_operand" "x,Yw")))]
"TARGET_SSE2"
"@
p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}
@ -2418,10 +2418,10 @@
(set_attr "mode" "DI,TI,TI")])
(define_insn "*eq<mode>3"
[(set (match_operand:VI_32 0 "register_operand" "=x,x")
(eq:VI_32
(match_operand:VI_32 1 "register_operand" "%0,x")
(match_operand:VI_32 2 "register_operand" "x,x")))]
[(set (match_operand:VI_16_32 0 "register_operand" "=x,x")
(eq:VI_16_32
(match_operand:VI_16_32 1 "register_operand" "%0,x")
(match_operand:VI_16_32 2 "register_operand" "x,x")))]
"TARGET_SSE2"
"@
pcmpeq<mmxvecsize>\t{%2, %0|%0, %2}
@ -2446,10 +2446,10 @@
(set_attr "mode" "DI,TI,TI")])
(define_insn "*gt<mode>3"
[(set (match_operand:VI_32 0 "register_operand" "=x,x")
(gt:VI_32
(match_operand:VI_32 1 "register_operand" "0,x")
(match_operand:VI_32 2 "register_operand" "x,x")))]
[(set (match_operand:VI_16_32 0 "register_operand" "=x,x")
(gt:VI_16_32
(match_operand:VI_16_32 1 "register_operand" "0,x")
(match_operand:VI_16_32 2 "register_operand" "x,x")))]
"TARGET_SSE2"
"@
pcmpgt<mmxvecsize>\t{%2, %0|%0, %2}
@ -2473,10 +2473,10 @@
(set_attr "mode" "TI")])
(define_insn "*xop_maskcmp<mode>3"
[(set (match_operand:VI_32 0 "register_operand" "=x")
(match_operator:VI_32 1 "ix86_comparison_int_operator"
[(match_operand:VI_32 2 "register_operand" "x")
(match_operand:VI_32 3 "register_operand" "x")]))]
[(set (match_operand:VI_16_32 0 "register_operand" "=x")
(match_operator:VI_16_32 1 "ix86_comparison_int_operator"
[(match_operand:VI_16_32 2 "register_operand" "x")
(match_operand:VI_16_32 3 "register_operand" "x")]))]
"TARGET_XOP"
"vpcom%Y1<mmxvecsize>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "sse4arg")
@ -2501,10 +2501,10 @@
(set_attr "mode" "TI")])
(define_insn "*xop_maskcmp_uns<mode>3"
[(set (match_operand:VI_32 0 "register_operand" "=x")
(match_operator:VI_32 1 "ix86_comparison_uns_operator"
[(match_operand:VI_32 2 "register_operand" "x")
(match_operand:VI_32 3 "register_operand" "x")]))]
[(set (match_operand:VI_16_32 0 "register_operand" "=x")
(match_operator:VI_16_32 1 "ix86_comparison_uns_operator"
[(match_operand:VI_16_32 2 "register_operand" "x")
(match_operand:VI_16_32 3 "register_operand" "x")]))]
"TARGET_XOP"
"vpcom%Y1u<mmxvecsize>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "ssecmp")
@ -2527,10 +2527,10 @@
})
(define_expand "vec_cmp<mode><mode>"
[(set (match_operand:VI_32 0 "register_operand")
(match_operator:VI_32 1 ""
[(match_operand:VI_32 2 "register_operand")
(match_operand:VI_32 3 "register_operand")]))]
[(set (match_operand:VI_16_32 0 "register_operand")
(match_operator:VI_16_32 1 ""
[(match_operand:VI_16_32 2 "register_operand")
(match_operand:VI_16_32 3 "register_operand")]))]
"TARGET_SSE2"
{
bool ok = ix86_expand_int_vec_cmp (operands);
@ -2551,10 +2551,10 @@
})
(define_expand "vec_cmpu<mode><mode>"
[(set (match_operand:VI_32 0 "register_operand")
(match_operator:VI_32 1 ""
[(match_operand:VI_32 2 "register_operand")
(match_operand:VI_32 3 "register_operand")]))]
[(set (match_operand:VI_16_32 0 "register_operand")
(match_operator:VI_16_32 1 ""
[(match_operand:VI_16_32 2 "register_operand")
(match_operand:VI_16_32 3 "register_operand")]))]
"TARGET_SSE2"
{
bool ok = ix86_expand_int_vec_cmp (operands);

21
gcc/testsuite/gcc.target/i386/pr103861-2.c Normal file
View File

@ -0,0 +1,21 @@
/* PR target/103861 */
/* { dg-do compile } */
/* { dg-options "-O2 -msse2" } */
typedef char vec __attribute__((vector_size(2)));
vec lt (vec a, vec b) { return a < b; }
vec le (vec a, vec b) { return a <= b; }
vec eq (vec a, vec b) { return a == b; }
vec ne (vec a, vec b) { return a != b; }
vec ge (vec a, vec b) { return a >= b; }
vec gt (vec a, vec b) { return a > b; }
typedef unsigned char uvec __attribute__((vector_size(2)));
vec ltu (uvec a, uvec b) { return a < b; }
vec leu (uvec a, uvec b) { return a <= b; }
vec geu (uvec a, uvec b) { return a >= b; }
vec gtu (uvec a, uvec b) { return a > b; }
/* { dg-final { scan-assembler-not "cmpb" } } */