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[ARM] Handle clz, rbit types in arm pipeline descriptions.

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* config/arm/cortex-a15.md (cortex_a15_alu): Handle clz, rbit.
	* config/arm/cortex-a5.md (cortex_a5_alu): Likewise.
	* config/arm/cortex-a53.md (cortex_a53_alu): Likewise.
	* config/arm/cortex-a7.md (cortex_a7_alu_reg): Likewise.
	* config/arm/cortex-a9.md (cortex_a9_dp): Likewise.
	* config/arm/cortex-m4.md (cortex_m4_alu): Likewise.
	* config/arm/cortex-r4.md (cortex_r4_alu): Likewise.

From-SVN: r212512
This commit is contained in:
Kyrylo Tkachov 2014-07-14 10:19:52 +00:00 committed by Kyrylo Tkachov
parent 0241e486d5
commit 04ae06daaa
8 changed files with 17 additions and 7 deletions
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10
gcc/ChangeLog
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@ -1,3 +1,13 @@
2014-07-14 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/cortex-a15.md (cortex_a15_alu): Handle clz, rbit.
* config/arm/cortex-a5.md (cortex_a5_alu): Likewise.
* config/arm/cortex-a53.md (cortex_a53_alu): Likewise.
* config/arm/cortex-a7.md (cortex_a7_alu_reg): Likewise.
* config/arm/cortex-a9.md (cortex_a9_dp): Likewise.
* config/arm/cortex-m4.md (cortex_m4_alu): Likewise.
* config/arm/cortex-r4.md (cortex_r4_alu): Likewise.
2014-07-14 Richard Biener <rguenther@suse.de>
* cgraph.h (decl_in_symtab_p): Make inline.

2
gcc/config/arm/cortex-a15.md
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@ -64,7 +64,7 @@
(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_reg,alus_reg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\
adr,bfm,clz,rbit,rev,\
shift_imm,shift_reg,\
mov_imm,mov_reg,\
mvn_imm,mvn_reg,\

2
gcc/config/arm/cortex-a5.md
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@ -61,7 +61,7 @@
(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_reg,alus_reg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\
adr,bfm,clz,rbit,rev,\
shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg,\
mrs,multiple,no_insn"))

2
gcc/config/arm/cortex-a53.md
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@ -75,7 +75,7 @@
(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_reg,alus_reg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,csel,rev,\
adr,bfm,csel,clz,rbit,rev,\
shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg,\
mrs,multiple,no_insn"))

2
gcc/config/arm/cortex-a7.md
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@ -137,7 +137,7 @@
(and (eq_attr "tune" "cortexa7")
(eq_attr "type" "alu_reg,alus_reg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\
bfm,rev,\
bfm,clz,rbit,rev,\
shift_imm,shift_reg,mov_reg,mvn_reg"))
"cortex_a7_ex1")

2
gcc/config/arm/cortex-a9.md
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@ -83,7 +83,7 @@ cortex_a9_p1_e2 + cortex_a9_p0_e1 + cortex_a9_p1_e1")
(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_reg,alus_reg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\
adr,bfm,clz,rbit,rev,\
shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg,\
mov_shift_reg,mov_shift,\

2
gcc/config/arm/cortex-m4.md
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@ -34,7 +34,7 @@
(ior (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_reg,alus_reg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\
adr,bfm,clz,rbit,rev,\
shift_imm,shift_reg,extend,\
alu_shift_imm,alus_shift_imm,\
logic_shift_imm,logics_shift_imm,\

2
gcc/config/arm/cortex-r4.md
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@ -81,7 +81,7 @@
(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_reg,alus_reg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\
adr,bfm,clz,rbit,rev,\
shift_imm,shift_reg,mvn_imm,mvn_reg"))
"cortex_r4_alu")