re PR target/50447 ([avr] Better support of AND, OR, XOR and PLUS with constant integers for 16- and 32-bit values)
PR target/50447 * config/avr/avr.md (cc): Add out_plus attribute alternative. (addsi3): Use it. Adapt avr_out_plus to new prototype. Use avr_out_plus for all CONST_INT addends. * config/avr/avr-protos.h (avr_out_plus): Change prototype. * config/avr/avr.c (notice_update_cc): Call avr_out_plus on CC_OUT_PLUS. (avr_out_plus_1): Change prototype and report effect on cc0. (avr_out_plus): Ditto. (adjust_insn_length): Adapt call to avr_out_plus to new prototype. From-SVN: r179816
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Georg-Johann Lay
Georg-Johann Lay
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a4474a3854
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05058b6e31
@ -1,3 +1,16 @@
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2011-10-11 Georg-Johann Lay <avr@gjlay.de>
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PR target/50447
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* config/avr/avr.md (cc): Add out_plus attribute alternative.
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(addsi3): Use it. Adapt avr_out_plus to new prototype. Use
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avr_out_plus for all CONST_INT addends.
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* config/avr/avr-protos.h (avr_out_plus): Change prototype.
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* config/avr/avr.c (notice_update_cc): Call avr_out_plus on
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CC_OUT_PLUS.
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(avr_out_plus_1): Change prototype and report effect on cc0.
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(avr_out_plus): Ditto.
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(adjust_insn_length): Adapt call to avr_out_plus to new prototype.
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2011-10-11 H.J. Lu <hongjiu.lu@intel.com>
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* config/i386/i386.c (ix86_expand_special_args_builtin): Remove
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@ -82,7 +82,7 @@ extern void avr_output_bld (rtx operands[], int bit_nr);
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extern void avr_output_addr_vec_elt (FILE *stream, int value);
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extern const char *avr_out_sbxx_branch (rtx insn, rtx operands[]);
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extern const char* avr_out_bitop (rtx, rtx*, int*);
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extern const char* avr_out_plus (rtx*, int*);
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extern const char* avr_out_plus (rtx*, int*, int*);
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extern const char* avr_out_addto_sp (rtx*, int*);
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extern bool avr_popcount_each_byte (rtx, int, int);
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@ -1630,9 +1630,37 @@ void
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notice_update_cc (rtx body ATTRIBUTE_UNUSED, rtx insn)
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{
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rtx set;
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enum attr_cc cc = get_attr_cc (insn);
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switch (get_attr_cc (insn))
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switch (cc)
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{
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default:
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break;
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case CC_OUT_PLUS:
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{
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rtx *op = recog_data.operand;
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int len_dummy, icc;
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/* Extract insn's operands. */
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extract_constrain_insn_cached (insn);
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avr_out_plus (op, &len_dummy, &icc);
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cc = (enum attr_cc) icc;
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break;
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}
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}
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switch (cc)
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{
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default:
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/* Special values like CC_OUT_PLUS from above have been
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mapped to "standard" CC_* values so we never come here. */
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gcc_unreachable();
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break;
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case CC_NONE:
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/* Insn does not affect CC at all. */
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break;
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@ -4673,10 +4701,11 @@ lshrsi3_out (rtx insn, rtx operands[], int *len)
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addition; otherwise, set *PLEN to the length of the instruction sequence (in
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words) printed with PLEN == NULL. XOP[3] is an 8-bit scratch register.
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CODE == PLUS: perform addition by using ADD instructions.
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CODE == MINUS: perform addition by using SUB instructions. */
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CODE == MINUS: perform addition by using SUB instructions.
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Set *PCC to effect on cc0 according to respective CC_* insn attribute. */
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static void
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avr_out_plus_1 (rtx *xop, int *plen, enum rtx_code code)
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avr_out_plus_1 (rtx *xop, int *plen, enum rtx_code code, int *pcc)
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{
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/* MODE of the operation. */
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enum machine_mode mode = GET_MODE (xop[0]);
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@ -4700,6 +4729,10 @@ avr_out_plus_1 (rtx *xop, int *plen, enum rtx_code code)
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/* Value to add. There are two ways to add VAL: R += VAL and R -= -VAL. */
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rtx xval = xop[2];
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/* Addition does not set cc0 in a usable way. */
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*pcc = (MINUS == code) ? CC_SET_CZN : CC_CLOBBER;
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if (MINUS == code)
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xval = gen_int_mode (-UINTVAL (xval), mode);
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@ -4722,6 +4755,11 @@ avr_out_plus_1 (rtx *xop, int *plen, enum rtx_code code)
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op[0] = reg8;
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op[1] = GEN_INT (val8);
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/* To get usable cc0 no low-bytes must have been skipped. */
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if (i && !started)
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*pcc = CC_CLOBBER;
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if (!started && i % 2 == 0
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&& test_hard_reg_class (ADDW_REGS, reg8))
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@ -4794,6 +4832,11 @@ avr_out_plus_1 (rtx *xop, int *plen, enum rtx_code code)
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started = true;
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} /* for all sub-bytes */
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/* No output doesn't change cc0. */
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if (plen && *plen == 0)
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*pcc = CC_NONE;
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}
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@ -4803,24 +4846,35 @@ avr_out_plus_1 (rtx *xop, int *plen, enum rtx_code code)
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and return "". If PLEN == NULL, print assembler instructions to perform the
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addition; otherwise, set *PLEN to the length of the instruction sequence (in
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words) printed with PLEN == NULL. */
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words) printed with PLEN == NULL.
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If PCC != 0 then set *PCC to the the instruction sequence's effect on the
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condition code (with respect to XOP[0]). */
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const char*
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avr_out_plus (rtx *xop, int *plen)
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avr_out_plus (rtx *xop, int *plen, int *pcc)
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{
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int len_plus, len_minus;
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int cc_plus, cc_minus, cc_dummy;
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if (!pcc)
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pcc = &cc_dummy;
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/* Work out if XOP[0] += XOP[2] is better or XOP[0] -= -XOP[2]. */
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avr_out_plus_1 (xop, &len_plus, PLUS);
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avr_out_plus_1 (xop, &len_minus, MINUS);
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avr_out_plus_1 (xop, &len_plus, PLUS, &cc_plus);
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avr_out_plus_1 (xop, &len_minus, MINUS, &cc_minus);
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/* Prefer MINUS over PLUS if size is equal because it sets cc0. */
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if (plen)
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*plen = (len_minus <= len_plus) ? len_minus : len_plus;
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{
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*plen = (len_minus <= len_plus) ? len_minus : len_plus;
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*pcc = (len_minus <= len_plus) ? cc_minus : cc_plus;
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}
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else if (len_minus <= len_plus)
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avr_out_plus_1 (xop, NULL, MINUS);
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avr_out_plus_1 (xop, NULL, MINUS, pcc);
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else
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avr_out_plus_1 (xop, NULL, PLUS);
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avr_out_plus_1 (xop, NULL, PLUS, pcc);
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return "";
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}
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@ -5209,7 +5263,7 @@ adjust_insn_length (rtx insn, int len)
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case ADJUST_LEN_OUT_BITOP: avr_out_bitop (insn, op, &len); break;
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case ADJUST_LEN_OUT_PLUS: avr_out_plus (op, &len); break;
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case ADJUST_LEN_OUT_PLUS: avr_out_plus (op, &len, NULL); break;
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case ADJUST_LEN_ADDTO_SP: avr_out_addto_sp (op, &len); break;
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@ -77,7 +77,8 @@
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(include "constraints.md")
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;; Condition code settings.
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(define_attr "cc" "none,set_czn,set_zn,set_n,compare,clobber"
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(define_attr "cc" "none,set_czn,set_zn,set_n,compare,clobber,
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out_plus"
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(const_string "none"))
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(define_attr "type" "branch,branch1,arith,xcall"
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@ -786,30 +787,28 @@
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(set_attr "cc" "set_n,set_czn,set_czn,set_czn,set_n,set_n")])
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(define_insn "addsi3"
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[(set (match_operand:SI 0 "register_operand" "=r,!w,!w,d,l,l ,d,r")
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(plus:SI (match_operand:SI 1 "register_operand" "%0,0 ,0 ,0,0,0 ,0,0")
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(match_operand:SI 2 "nonmemory_operand" "r,I ,J ,s,P,N ,n,n")))
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(clobber (match_scratch:QI 3 "=X,X ,X ,X,X,X ,X,&d"))]
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[(set (match_operand:SI 0 "register_operand" "=r,d ,d,r")
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(plus:SI (match_operand:SI 1 "register_operand" "%0,0 ,0,0")
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(match_operand:SI 2 "nonmemory_operand" "r,s ,n,n")))
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(clobber (match_scratch:QI 3 "=X,X ,X,&d"))]
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""
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{
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static const char * const asm_code[] =
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{
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"add %A0,%A2\;adc %B0,%B2\;adc %C0,%C2\;adc %D0,%D2",
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"adiw %0,%2\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__",
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"sbiw %0,%n2\;sbc %C0,__zero_reg__\;sbc %D0,__zero_reg__",
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"subi %0,lo8(-(%2))\;sbci %B0,hi8(-(%2))\;sbci %C0,hlo8(-(%2))\;sbci %D0,hhi8(-(%2))",
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"sec\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__",
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"sec\;sbc %A0,__zero_reg__\;sbc %B0,__zero_reg__\;sbc %C0,__zero_reg__\;sbc %D0,__zero_reg__"
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"",
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""
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};
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if (which_alternative >= (signed) (sizeof (asm_code) / sizeof (*asm_code)))
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return avr_out_plus (operands, NULL);
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if (*asm_code[which_alternative])
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return asm_code [which_alternative];
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return asm_code [which_alternative];
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return avr_out_plus (operands, NULL, NULL);
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}
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[(set_attr "length" "4,3,3,4,5,5,8,8")
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(set_attr "adjust_len" "*,*,*,*,*,*,out_plus,out_plus")
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(set_attr "cc" "set_n,set_n,set_czn,set_czn,set_n,set_n,clobber,clobber")])
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[(set_attr "length" "4,4,4,8")
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(set_attr "adjust_len" "*,*,out_plus,out_plus")
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(set_attr "cc" "set_n,set_czn,out_plus,out_plus")])
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(define_insn "*addsi3_zero_extend"
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[(set (match_operand:SI 0 "register_operand" "=r")
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