[ARM,AArch64] more poly64 intrinsics and tests
2017-02-06 Christophe Lyon <christophe.lyon@linaro.org> gcc/ * config/aarch64/arm_neon.h (vtst_p8): Rewrite without asm. (vtst_p16): Likewise. (vtstq_p8): Likewise. (vtstq_p16): Likewise. (vtst_p64): New. (vtstq_p64): Likewise. * config/arm/arm_neon.h (vgetq_lane_p64): New. (vset_lane_p64): New. (vsetq_lane_p64): New. 2017-02-06 Christophe Lyon <christophe.lyon@linaro.org> gcc/testsuite/ * gcc.target/aarch64/advsimd-intrinsics/p64_p128.c (vget_lane_expected, vset_lane_expected, vtst_expected_poly64x1): New. (vmov_n_expected0, vmov_n_expected1, vmov_n_expected2) (expected_vld_st2_0, expected_vld_st2_1, expected_vld_st3_0) (expected_vld_st3_1, expected_vld_st3_2, expected_vld_st4_0) (expected_vld_st4_1, expected_vld_st4_2, expected_vld_st4_3) (vtst_expected_poly64x2): Move to aarch64-only section. (vget_lane_p64, vgetq_lane_p64, vset_lane_p64, vsetq_lane_p64) (vtst_p64, vtstq_p64): New tests. From-SVN: r245328
This commit is contained in:
Christophe Lyon
Christophe Lyon
parent
a7c8ed0c36
commit
052ef81d2d
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@ -1,3 +1,15 @@
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2017-02-10 Christophe Lyon <christophe.lyon@linaro.org>
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* config/aarch64/arm_neon.h (vtst_p8): Rewrite without asm.
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(vtst_p16): Likewise.
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(vtstq_p8): Likewise.
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(vtstq_p16): Likewise.
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(vtst_p64): New.
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(vtstq_p64): Likewise.
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* config/arm/arm_neon.h (vgetq_lane_p64): New.
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(vset_lane_p64): New.
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(vsetq_lane_p64): New.
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2017-02-10 Jakub Jelinek <jakub@redhat.com>
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PR tree-optimization/79411
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@ -10862,48 +10862,47 @@ __extension__ extern __inline uint8x8_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vtst_p8 (poly8x8_t a, poly8x8_t b)
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{
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uint8x8_t result;
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__asm__ ("cmtst %0.8b, %1.8b, %2.8b"
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: "=w"(result)
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: "w"(a), "w"(b)
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: /* No clobbers */);
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return result;
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return (uint8x8_t) ((((uint8x8_t) a) & ((uint8x8_t) b))
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!= 0);
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}
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__extension__ extern __inline uint16x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vtst_p16 (poly16x4_t a, poly16x4_t b)
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{
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uint16x4_t result;
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__asm__ ("cmtst %0.4h, %1.4h, %2.4h"
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: "=w"(result)
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: "w"(a), "w"(b)
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: /* No clobbers */);
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return result;
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return (uint16x4_t) ((((uint16x4_t) a) & ((uint16x4_t) b))
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!= 0);
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}
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__extension__ extern __inline uint64x1_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vtst_p64 (poly64x1_t a, poly64x1_t b)
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{
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return (uint64x1_t) ((a & b) != __AARCH64_INT64_C (0));
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}
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__extension__ extern __inline uint8x16_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vtstq_p8 (poly8x16_t a, poly8x16_t b)
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{
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uint8x16_t result;
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__asm__ ("cmtst %0.16b, %1.16b, %2.16b"
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: "=w"(result)
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: "w"(a), "w"(b)
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: /* No clobbers */);
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return result;
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return (uint8x16_t) ((((uint8x16_t) a) & ((uint8x16_t) b))
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!= 0);
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}
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__extension__ extern __inline uint16x8_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vtstq_p16 (poly16x8_t a, poly16x8_t b)
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{
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uint16x8_t result;
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__asm__ ("cmtst %0.8h, %1.8h, %2.8h"
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: "=w"(result)
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: "w"(a), "w"(b)
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: /* No clobbers */);
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return result;
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return (uint16x8_t) ((((uint16x8_t) a) & ((uint16x8_t) b))
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!= 0);
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}
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__extension__ extern __inline uint64x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vtstq_p64 (poly64x2_t a, poly64x2_t b)
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{
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return (uint64x2_t) ((((uint64x2_t) a) & ((uint64x2_t) b))
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!= __AARCH64_INT64_C (0));
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}
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/* End of temporary inline asm implementations. */
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@ -6309,6 +6309,16 @@ vgetq_lane_s64 (int64x2_t __a, const int __b)
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return (int64_t)__builtin_neon_vget_lanev2di (__a, __b);
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}
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#pragma GCC push_options
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#pragma GCC target ("fpu=crypto-neon-fp-armv8")
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__extension__ extern __inline poly64_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vgetq_lane_p64 (poly64x2_t __a, const int __b)
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{
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return (poly64_t)__builtin_neon_vget_lanev2di ((int64x2_t) __a, __b);
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}
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#pragma GCC pop_options
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__extension__ extern __inline uint64_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vgetq_lane_u64 (uint64x2_t __a, const int __b)
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@ -6405,6 +6415,16 @@ vset_lane_u64 (uint64_t __a, uint64x1_t __b, const int __c)
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return (uint64x1_t)__builtin_neon_vset_lanedi ((__builtin_neon_di) __a, (int64x1_t) __b, __c);
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}
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#pragma GCC push_options
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#pragma GCC target ("fpu=crypto-neon-fp-armv8")
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__extension__ extern __inline poly64x1_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vset_lane_p64 (poly64_t __a, poly64x1_t __b, const int __c)
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{
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return (poly64x1_t)__builtin_neon_vset_lanedi ((__builtin_neon_di) __a, (int64x1_t) __b, __c);
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}
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#pragma GCC pop_options
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__extension__ extern __inline int8x16_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vsetq_lane_s8 (int8_t __a, int8x16_t __b, const int __c)
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@ -6496,6 +6516,13 @@ vsetq_lane_u64 (uint64_t __a, uint64x2_t __b, const int __c)
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#pragma GCC push_options
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#pragma GCC target ("fpu=crypto-neon-fp-armv8")
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__extension__ extern __inline poly64x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vsetq_lane_p64 (poly64_t __a, poly64x2_t __b, const int __c)
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{
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return (poly64x2_t)__builtin_neon_vset_lanev2di ((__builtin_neon_di) __a, (int64x2_t) __b, __c);
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}
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__extension__ extern __inline poly64x1_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vcreate_p64 (uint64_t __a)
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@ -1,3 +1,16 @@
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2017-02-10 Christophe Lyon <christophe.lyon@linaro.org>
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* gcc.target/aarch64/advsimd-intrinsics/p64_p128.c
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(vget_lane_expected, vset_lane_expected, vtst_expected_poly64x1):
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New.
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(vmov_n_expected0, vmov_n_expected1, vmov_n_expected2)
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(expected_vld_st2_0, expected_vld_st2_1, expected_vld_st3_0)
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(expected_vld_st3_1, expected_vld_st3_2, expected_vld_st4_0)
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(expected_vld_st4_1, expected_vld_st4_2, expected_vld_st4_3)
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(vtst_expected_poly64x2): Move to aarch64-only section.
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(vget_lane_p64, vgetq_lane_p64, vset_lane_p64, vsetq_lane_p64)
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(vtst_p64, vtstq_p64): New tests.
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2017-02-10 Paolo Carlini <paolo.carlini@oracle.com>
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PR c++/71737
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@ -39,17 +39,6 @@ VECT_VAR_DECL(vdup_n_expected2,poly,64,1) [] = { 0xfffffffffffffff2 };
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VECT_VAR_DECL(vdup_n_expected2,poly,64,2) [] = { 0xfffffffffffffff2,
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0xfffffffffffffff2 };
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/* Expected results: vmov_n. */
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VECT_VAR_DECL(vmov_n_expected0,poly,64,1) [] = { 0xfffffffffffffff0 };
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VECT_VAR_DECL(vmov_n_expected0,poly,64,2) [] = { 0xfffffffffffffff0,
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0xfffffffffffffff0 };
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VECT_VAR_DECL(vmov_n_expected1,poly,64,1) [] = { 0xfffffffffffffff1 };
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VECT_VAR_DECL(vmov_n_expected1,poly,64,2) [] = { 0xfffffffffffffff1,
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0xfffffffffffffff1 };
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VECT_VAR_DECL(vmov_n_expected2,poly,64,1) [] = { 0xfffffffffffffff2 };
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VECT_VAR_DECL(vmov_n_expected2,poly,64,2) [] = { 0xfffffffffffffff2,
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0xfffffffffffffff2 };
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/* Expected results: vext. */
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VECT_VAR_DECL(vext_expected,poly,64,1) [] = { 0xfffffffffffffff0 };
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VECT_VAR_DECL(vext_expected,poly,64,2) [] = { 0xfffffffffffffff1, 0x88 };
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@ -124,6 +113,29 @@ VECT_VAR_DECL(vst1_lane_expected,poly,64,1) [] = { 0xfffffffffffffff0 };
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VECT_VAR_DECL(vst1_lane_expected,poly,64,2) [] = { 0xfffffffffffffff0,
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0x3333333333333333 };
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/* Expected results: vget_lane. */
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VECT_VAR_DECL(vget_lane_expected,poly,64,1) = 0xfffffffffffffff0;
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VECT_VAR_DECL(vget_lane_expected,poly,64,2) = 0xfffffffffffffff0;
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/* Expected results: vset_lane. */
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VECT_VAR_DECL(vset_lane_expected,poly,64,1) [] = { 0x88 };
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VECT_VAR_DECL(vset_lane_expected,poly,64,2) [] = { 0xfffffffffffffff0, 0x11 };
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/* Expected results: vtst. */
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VECT_VAR_DECL(vtst_expected,uint,64,1) [] = { 0x0 };
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#ifdef __aarch64__
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/* Expected results: vmov_n. */
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VECT_VAR_DECL(vmov_n_expected0,poly,64,1) [] = { 0xfffffffffffffff0 };
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VECT_VAR_DECL(vmov_n_expected0,poly,64,2) [] = { 0xfffffffffffffff0,
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0xfffffffffffffff0 };
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VECT_VAR_DECL(vmov_n_expected1,poly,64,1) [] = { 0xfffffffffffffff1 };
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VECT_VAR_DECL(vmov_n_expected1,poly,64,2) [] = { 0xfffffffffffffff1,
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0xfffffffffffffff1 };
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VECT_VAR_DECL(vmov_n_expected2,poly,64,1) [] = { 0xfffffffffffffff2 };
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VECT_VAR_DECL(vmov_n_expected2,poly,64,2) [] = { 0xfffffffffffffff2,
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0xfffffffffffffff2 };
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/* Expected results: vldX_lane. */
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VECT_VAR_DECL(expected_vld_st2_0,poly,64,1) [] = { 0xfffffffffffffff0 };
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VECT_VAR_DECL(expected_vld_st2_0,poly,64,2) [] = { 0xfffffffffffffff0,
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@ -153,9 +165,9 @@ VECT_VAR_DECL(expected_vld_st4_3,poly,64,1) [] = { 0xfffffffffffffff3 };
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VECT_VAR_DECL(expected_vld_st4_3,poly,64,2) [] = { 0xaaaaaaaaaaaaaaaa,
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0xaaaaaaaaaaaaaaaa };
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/* Expected results: vget_lane. */
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VECT_VAR_DECL(vget_lane_expected,poly,64,1) = 0xfffffffffffffff0;
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VECT_VAR_DECL(vget_lane_expected,poly,64,2) = 0xfffffffffffffff0;
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/* Expected results: vtst. */
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VECT_VAR_DECL(vtst_expected,uint,64,2) [] = { 0x0, 0xffffffffffffffff };
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#endif
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int main (void)
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{
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@ -727,7 +739,105 @@ int main (void)
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CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vst1_lane_expected, "");
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CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vst1_lane_expected, "");
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/* vget_lane_p64 tests. */
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#undef TEST_MSG
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#define TEST_MSG "VGET_LANE/VGETQ_LANE"
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#define TEST_VGET_LANE(Q, T1, T2, W, N, L) \
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VECT_VAR(vget_lane_vector, T1, W, N) = vget##Q##_lane_##T2##W(VECT_VAR(vget_lane_vector1, T1, W, N), L); \
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if (VECT_VAR(vget_lane_vector, T1, W, N) != VECT_VAR(vget_lane_expected, T1, W, N)) { \
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fprintf(stderr, \
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"ERROR in %s (%s line %d in result '%s') at type %s " \
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"got 0x%" PRIx##W " != 0x%" PRIx##W "\n", \
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TEST_MSG, __FILE__, __LINE__, \
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STR(VECT_VAR(vget_lane_expected, T1, W, N)), \
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STR(VECT_NAME(T1, W, N)), \
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VECT_VAR(vget_lane_vector, T1, W, N), \
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VECT_VAR(vget_lane_expected, T1, W, N)); \
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abort (); \
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}
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/* Initialize input values. */
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DECL_VARIABLE(vget_lane_vector1, poly, 64, 1);
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DECL_VARIABLE(vget_lane_vector1, poly, 64, 2);
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VLOAD(vget_lane_vector1, buffer, , poly, p, 64, 1);
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VLOAD(vget_lane_vector1, buffer, q, poly, p, 64, 2);
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VECT_VAR_DECL(vget_lane_vector, poly, 64, 1);
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VECT_VAR_DECL(vget_lane_vector, poly, 64, 2);
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TEST_VGET_LANE( , poly, p, 64, 1, 0);
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TEST_VGET_LANE(q, poly, p, 64, 2, 0);
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/* vset_lane_p64 tests. */
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#undef TEST_MSG
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#define TEST_MSG "VSET_LANE/VSETQ_LANE"
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#define TEST_VSET_LANE(Q, T1, T2, W, N, V, L) \
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VECT_VAR(vset_lane_vector, T1, W, N) = \
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vset##Q##_lane_##T2##W(V, \
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VECT_VAR(vset_lane_vector, T1, W, N), \
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L); \
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vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vset_lane_vector, T1, W, N))
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/* Initialize input values. */
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DECL_VARIABLE(vset_lane_vector, poly, 64, 1);
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DECL_VARIABLE(vset_lane_vector, poly, 64, 2);
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CLEAN(result, uint, 64, 1);
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CLEAN(result, uint, 64, 2);
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VLOAD(vset_lane_vector, buffer, , poly, p, 64, 1);
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VLOAD(vset_lane_vector, buffer, q, poly, p, 64, 2);
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/* Choose value and lane arbitrarily. */
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TEST_VSET_LANE(, poly, p, 64, 1, 0x88, 0);
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TEST_VSET_LANE(q, poly, p, 64, 2, 0x11, 1);
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CHECK(TEST_MSG, poly, 64, 1, PRIx64, vset_lane_expected, "");
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CHECK(TEST_MSG, poly, 64, 2, PRIx64, vset_lane_expected, "");
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/* vtst_p64 tests. */
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#undef TEST_MSG
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#define TEST_MSG "VTST"
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#define TEST_VTST1(INSN, Q, T1, T2, W, N) \
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VECT_VAR(vtst_vector_res, uint, W, N) = \
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INSN##Q##_##T2##W(VECT_VAR(vtst_vector, T1, W, N), \
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VECT_VAR(vtst_vector2, T1, W, N)); \
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vst1##Q##_u##W(VECT_VAR(result, uint, W, N), \
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VECT_VAR(vtst_vector_res, uint, W, N))
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#define TEST_VTST(INSN, Q, T1, T2, W, N) \
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TEST_VTST1(INSN, Q, T1, T2, W, N) \
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/* Initialize input values. */
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DECL_VARIABLE(vtst_vector, poly, 64, 1);
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DECL_VARIABLE(vtst_vector2, poly, 64, 1);
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DECL_VARIABLE(vtst_vector_res, uint, 64, 1);
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CLEAN(result, uint, 64, 1);
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VLOAD(vtst_vector, buffer, , poly, p, 64, 1);
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VDUP(vtst_vector2, , poly, p, 64, 1, 5);
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TEST_VTST(vtst, , poly, p, 64, 1);
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CHECK(TEST_MSG, uint, 64, 1, PRIx64, vtst_expected, "");
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/* vtstq_p64 is supported by aarch64 only. */
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#ifdef __aarch64__
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DECL_VARIABLE(vtst_vector, poly, 64, 2);
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DECL_VARIABLE(vtst_vector2, poly, 64, 2);
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DECL_VARIABLE(vtst_vector_res, uint, 64, 2);
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CLEAN(result, uint, 64, 2);
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VLOAD(vtst_vector, buffer, q, poly, p, 64, 2);
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VDUP(vtst_vector2, q, poly, p, 64, 2, 5);
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TEST_VTST(vtst, q, poly, p, 64, 2);
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CHECK(TEST_MSG, uint, 64, 2, PRIx64, vtst_expected, "");
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/* vmov_n_p64 tests. */
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#undef TEST_MSG
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@ -767,37 +877,6 @@ int main (void)
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}
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}
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/* vget_lane_p64 tests. */
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#undef TEST_MSG
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#define TEST_MSG "VGET_LANE/VGETQ_LANE"
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#define TEST_VGET_LANE(Q, T1, T2, W, N, L) \
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VECT_VAR(vget_lane_vector, T1, W, N) = vget##Q##_lane_##T2##W(VECT_VAR(vector, T1, W, N), L); \
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if (VECT_VAR(vget_lane_vector, T1, W, N) != VECT_VAR(vget_lane_expected, T1, W, N)) { \
|
||||
fprintf(stderr, \
|
||||
"ERROR in %s (%s line %d in result '%s') at type %s " \
|
||||
"got 0x%" PRIx##W " != 0x%" PRIx##W "\n", \
|
||||
TEST_MSG, __FILE__, __LINE__, \
|
||||
STR(VECT_VAR(vget_lane_expected, T1, W, N)), \
|
||||
STR(VECT_NAME(T1, W, N)), \
|
||||
(uint##W##_t)VECT_VAR(vget_lane_vector, T1, W, N), \
|
||||
(uint##W##_t)VECT_VAR(vget_lane_expected, T1, W, N)); \
|
||||
abort (); \
|
||||
}
|
||||
|
||||
/* Initialize input values. */
|
||||
DECL_VARIABLE(vector, poly, 64, 1);
|
||||
DECL_VARIABLE(vector, poly, 64, 2);
|
||||
|
||||
VLOAD(vector, buffer, , poly, p, 64, 1);
|
||||
VLOAD(vector, buffer, q, poly, p, 64, 2);
|
||||
|
||||
VECT_VAR_DECL(vget_lane_vector, poly, 64, 1);
|
||||
VECT_VAR_DECL(vget_lane_vector, poly, 64, 2);
|
||||
|
||||
TEST_VGET_LANE( , poly, p, 64, 1, 0);
|
||||
TEST_VGET_LANE(q, poly, p, 64, 2, 0);
|
||||
|
||||
/* vldx_lane_p64 tests. */
|
||||
#undef TEST_MSG
|
||||
#define TEST_MSG "VLDX_LANE/VLDXQ_LANE"
|
||||
|
|
|
|||
Loading…
Reference in New Issue