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Fix indentation problems 

From-SVN: r29027
This commit is contained in:
Bernd Schmidt 1999-09-01 14:30:35 +00:00 committed by Bernd Schmidt
parent 3b3958fc9a
commit 05d106753d
3 changed files with 300 additions and 295 deletions
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gcc/ChangeLog
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@ -1,3 +1,8 @@
Wed Sep 1 11:32:00 1999 Bernd Schmidt <bernds@cygnus.co.uk>
* reload1.c: Fix many indentation problems.
* reload.c: Likewise.
Tue Aug 31 22:08:03 1999 Marc Espie <espie@cvs.openbsd.org>
* alias.c (non_local_reference_p): Constify fmt.

272
gcc/reload.c
View File

@ -161,7 +161,7 @@ a register with any other reload. */
or more reloads.
reload_secondary_in_reload
reload_secondary_out_reload
int, gives the reload number of a secondary
int, gives the reload number of a secondary
reload, when needed; otherwise -1
reload_secondary_in_icode
reload_secondary_out_icode
@ -237,9 +237,9 @@ struct decomposition
#ifdef SECONDARY_MEMORY_NEEDED
/* Save MEMs needed to copy from one class of registers to another. One MEM
is used per mode, but normally only one or two modes are ever used.
is used per mode, but normally only one or two modes are ever used.
We keep two versions, before and after register elimination. The one
We keep two versions, before and after register elimination. The one
after register elimination is record separately for each operand. This
is done in case the address is not valid to be sure that we separately
reload each. */
@ -439,7 +439,7 @@ push_secondary_reload (in_p, x, opnum, optional, reload_class, reload_mode,
if (icode != CODE_FOR_nothing)
{
/* If IN_P is non-zero, the reload register will be the output in
/* If IN_P is non-zero, the reload register will be the output in
operand 0. If IN_P is zero, the reload register will be the input
in operand 1. Outputs should have an initial "=", which we must
skip. */
@ -587,7 +587,7 @@ push_secondary_reload (in_p, x, opnum, optional, reload_class, reload_mode,
#ifdef SECONDARY_MEMORY_NEEDED
/* If we need a memory location to copy between the two reload regs,
set it up now. Note that we do the input case before making
the reload and the output case after. This is due to the
the reload and the output case after. This is due to the
way reloads are output. */
if (in_p && icode == CODE_FOR_nothing
@ -613,7 +613,7 @@ push_secondary_reload (in_p, x, opnum, optional, reload_class, reload_mode,
reload_when_needed[s_reload] = secondary_type;
reload_secondary_in_reload[s_reload] = in_p ? t_reload : -1;
reload_secondary_out_reload[s_reload] = ! in_p ? t_reload : -1;
reload_secondary_in_icode[s_reload] = in_p ? t_icode : CODE_FOR_nothing;
reload_secondary_in_icode[s_reload] = in_p ? t_icode : CODE_FOR_nothing;
reload_secondary_out_icode[s_reload]
= ! in_p ? t_icode : CODE_FOR_nothing;
reload_secondary_p[s_reload] = 1;
@ -634,7 +634,7 @@ push_secondary_reload (in_p, x, opnum, optional, reload_class, reload_mode,
#ifdef SECONDARY_MEMORY_NEEDED
/* Return a memory location that will be used to copy X in mode MODE.
/* Return a memory location that will be used to copy X in mode MODE.
If we haven't already made a location for this mode in this insn,
call find_reloads_address on the location being returned. */
@ -664,7 +664,7 @@ get_secondary_mem (x, mode, opnum, type)
if (secondary_memlocs_elim[(int) mode][opnum] != 0)
return secondary_memlocs_elim[(int) mode][opnum];
/* If this is the first time we've tried to get a MEM for this mode,
/* If this is the first time we've tried to get a MEM for this mode,
allocate a new one. `something_changed' in reload will get set
by noticing that the frame size has changed. */
@ -774,12 +774,12 @@ find_reusable_reload (p_in, out, class, type, opnum, dont_share)
/* We can use an existing reload if the class is right
and at least one of IN and OUT is a match
and the other is at worst neutral.
(A zero compared against anything is neutral.)
(A zero compared against anything is neutral.)
If SMALL_REGISTER_CLASSES, don't use existing reloads unless they are
for the same thing since that can cause us to need more reload registers
than we otherwise would. */
for (i = 0; i < n_reloads; i++)
if ((reg_class_subset_p (class, reload_reg_class[i])
|| reg_class_subset_p (reload_reg_class[i], class))
@ -794,8 +794,8 @@ find_reusable_reload (p_in, out, class, type, opnum, dont_share)
&& (in == 0 || reload_in[i] == 0 || MATCHES (reload_in[i], in))))
&& (reload_out[i] == 0 || ! earlyclobber_operand_p (reload_out[i]))
&& (reg_class_size[(int) class] == 1 || SMALL_REGISTER_CLASSES)
&& MERGABLE_RELOADS (type, reload_when_needed[i],
opnum, reload_opnum[i]))
&& MERGABLE_RELOADS (type, reload_when_needed[i],
opnum, reload_opnum[i]))
return i;
/* Reloading a plain reg for input can match a reload to postincrement
@ -900,7 +900,7 @@ push_reload (in, out, inloc, outloc, class,
if (outmode == VOIDmode && out != 0)
outmode = GET_MODE (out);
/* If IN is a pseudo register everywhere-equivalent to a constant, and
/* If IN is a pseudo register everywhere-equivalent to a constant, and
it is not in a hard register, reload straight from the constant,
since we want to get rid of such pseudo registers.
Often this is done earlier, but not always in find_reloads_address. */
@ -1104,7 +1104,7 @@ push_reload (in, out, inloc, outloc, class,
((GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) - 1)
/ UNITS_PER_WORD)))
#endif
))
))
|| (GET_CODE (SUBREG_REG (out)) == REG
&& REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER
&& ((GET_MODE_SIZE (outmode) <= UNITS_PER_WORD
@ -1137,9 +1137,9 @@ push_reload (in, out, inloc, outloc, class,
{
out_subreg_loc = outloc;
outloc = &SUBREG_REG (out);
out = *outloc;
out = *outloc;
#if ! defined (LOAD_EXTEND_OP) && ! defined (WORD_REGISTER_OPERATIONS)
if (GET_CODE (out) == MEM
if (GET_CODE (out) == MEM
&& GET_MODE_SIZE (GET_MODE (out)) > GET_MODE_SIZE (outmode))
abort ();
#endif
@ -1304,7 +1304,7 @@ push_reload (in, out, inloc, outloc, class,
if (in != 0 && GET_CODE (in) == REG
&& REGNO (in) < FIRST_PSEUDO_REGISTER
&& SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
class, inmode))
class, inmode))
get_secondary_mem (in, inmode, opnum, type);
#endif
@ -1634,10 +1634,10 @@ loc_mentioned_in_p (loc, in)
if (loc == &in->fld[i].rtx)
return 1;
if (fmt[i] == 'e')
{
{
if (loc_mentioned_in_p (loc, XEXP (in, i)))
return 1;
}
}
else if (fmt[i] == 'E')
for (j = XVECLEN (in, i) - 1; i >= 0; i--)
if (loc_mentioned_in_p (loc, XVECEXP (in, i, j)))
@ -1806,10 +1806,10 @@ combine_reloads ()
<= HARD_REGNO_NREGS (REGNO (XEXP (note, 0)), GET_MODE (XEXP (note, 0))))
/* Ensure that a secondary or tertiary reload for this output
won't want this register. */
&& ((secondary_out = reload_secondary_out_reload[output_reload]) == -1
|| (! (TEST_HARD_REG_BIT
(reg_class_contents[(int) reload_reg_class[secondary_out]],
REGNO (XEXP (note, 0))))
&& ((secondary_out = reload_secondary_out_reload[output_reload]) == -1
|| (! (TEST_HARD_REG_BIT
(reg_class_contents[(int) reload_reg_class[secondary_out]],
REGNO (XEXP (note, 0))))
&& ((secondary_out = reload_secondary_out_reload[secondary_out]) == -1
|| ! (TEST_HARD_REG_BIT
(reg_class_contents[(int) reload_reg_class[secondary_out]],
@ -2077,7 +2077,7 @@ operands_match_p (x, y)
register RTX_CODE code = GET_CODE (x);
register const char *fmt;
int success_2;
if (x == y)
return 1;
if ((code == REG || (code == SUBREG && GET_CODE (SUBREG_REG (x)) == REG))
@ -2136,7 +2136,7 @@ operands_match_p (x, y)
slow:
/* Now we have disposed of all the cases
/* Now we have disposed of all the cases
in which different rtx codes can match. */
if (code != GET_CODE (y))
return 0;
@ -2207,11 +2207,11 @@ operands_match_p (x, y)
}
/* Describe the range of registers or memory referenced by X.
If X is a register, set REG_FLAG and put the first register
If X is a register, set REG_FLAG and put the first register
number into START and the last plus one into END.
If X is a memory reference, put a base address into BASE
If X is a memory reference, put a base address into BASE
and a range of integer offsets into START and END.
If X is pushing on the stack, we can assume it causes no trouble,
If X is pushing on the stack, we can assume it causes no trouble,
so we set the SAFE field. */
static struct decomposition
@ -2262,7 +2262,7 @@ decompose (x)
{
base = addr;
offset = const0_rtx;
}
}
if (GET_CODE (offset) == CONST)
offset = XEXP (offset, 0);
if (GET_CODE (offset) == PLUS)
@ -2303,7 +2303,7 @@ decompose (x)
else if (GET_CODE (x) == REG)
{
val.reg_flag = 1;
val.start = true_regnum (x);
val.start = true_regnum (x);
if (val.start < 0)
{
/* A pseudo with no hard reg. */
@ -2320,7 +2320,7 @@ decompose (x)
/* This could be more precise, but it's good enough. */
return decompose (SUBREG_REG (x));
val.reg_flag = 1;
val.start = true_regnum (x);
val.start = true_regnum (x);
if (val.start < 0)
return decompose (SUBREG_REG (x));
else
@ -2496,7 +2496,7 @@ find_reloads (insn, replace, ind_levels, live_known, reload_reg_p)
if (reg_set_p (cc0_rtx, PATTERN (insn)))
no_output_reloads = 1;
#endif
#ifdef SECONDARY_MEMORY_NEEDED
/* The eliminated forms of any secondary memory locations are per-insn, so
clear them out here. */
@ -2550,7 +2550,7 @@ find_reloads (insn, replace, ind_levels, live_known, reload_reg_p)
modified[i] = RELOAD_READ;
/* Scan this operand's constraint to see if it is an output operand,
/* Scan this operand's constraint to see if it is an output operand,
an in-out operand, is commutative, or should match another. */
while ((c = *p++))
@ -2605,7 +2605,7 @@ find_reloads (insn, replace, ind_levels, live_known, reload_reg_p)
and reload parts of the addresses into index registers.
Also here any references to pseudo regs that didn't get hard regs
but are equivalent to constants get replaced in the insn itself
with those constants. Nobody will ever see them again.
with those constants. Nobody will ever see them again.
Finally, set up the preferred classes of each operand. */
@ -2631,7 +2631,7 @@ find_reloads (insn, replace, ind_levels, live_known, reload_reg_p)
recog_operand[i], recog_operand_loc[i],
i, operand_type[i], ind_levels, insn);
/* If we now have a simple operand where we used to have a
/* If we now have a simple operand where we used to have a
PLUS or MULT, re-recognize and try again. */
if ((GET_RTX_CLASS (GET_CODE (*recog_operand_loc[i])) == 'o'
|| GET_CODE (*recog_operand_loc[i]) == SUBREG)
@ -2670,14 +2670,14 @@ find_reloads (insn, replace, ind_levels, live_known, reload_reg_p)
that didn't get a hard register, emit a USE with a REG_EQUAL
note in front so that we might inherit a previous, possibly
wider reload. */
if (replace
&& GET_CODE (op) == MEM
&& GET_CODE (reg) == REG
&& (GET_MODE_SIZE (GET_MODE (reg))
>= GET_MODE_SIZE (GET_MODE (op))))
REG_NOTES (emit_insn_before (gen_rtx_USE (VOIDmode, reg), insn))
= gen_rtx_EXPR_LIST (REG_EQUAL,
REG_NOTES (emit_insn_before (gen_rtx_USE (VOIDmode, reg), insn))
= gen_rtx_EXPR_LIST (REG_EQUAL,
reg_equiv_memory_loc[REGNO (reg)], NULL_RTX);
substed_operand[i] = recog_operand[i] = op;
@ -2702,13 +2702,13 @@ find_reloads (insn, replace, ind_levels, live_known, reload_reg_p)
&& (set == 0 || &SET_DEST (set) != recog_operand_loc[i]))
{
/* Record the existing mode so that the check if constants are
allowed will work when operand_mode isn't specified. */
allowed will work when operand_mode isn't specified. */
if (operand_mode[i] == VOIDmode)
operand_mode[i] = GET_MODE (recog_operand[i]);
substed_operand[i] = recog_operand[i]
= reg_equiv_constant[regno];
= reg_equiv_constant[regno];
}
if (reg_equiv_memory_loc[regno] != 0
&& (reg_equiv_address[regno] != 0 || num_not_at_initial_offset))
@ -2780,7 +2780,7 @@ find_reloads (insn, replace, ind_levels, live_known, reload_reg_p)
/* REJECT is a count of how undesirable this alternative says it is
if any reloading is required. If the alternative matches exactly
then REJECT is ignored, but otherwise it gets this much
counted against it in addition to the reloading needed. Each
counted against it in addition to the reloading needed. Each
? counts three times here since we want the disparaging caused by
a bad register class to only count 1/3 as much. */
int reject = 0;
@ -2808,7 +2808,7 @@ find_reloads (insn, replace, ind_levels, live_known, reload_reg_p)
int earlyclobber = 0;
/* If the predicate accepts a unary operator, it means that
we need to reload the operand, but do not do this for
we need to reload the operand, but do not do this for
match_operator and friends. */
if (GET_RTX_CLASS (GET_CODE (operand)) == '1' && *p != 0)
operand = XEXP (operand, 0);
@ -2838,10 +2838,10 @@ find_reloads (insn, replace, ind_levels, live_known, reload_reg_p)
made assumptions about the behavior of the machine in such
register access. If the data is, in fact, in memory we
must always load using the size assumed to be in the
register and let the insn do the different-sized
register and let the insn do the different-sized
accesses.
This is doubly true if WORD_REGISTER_OPERATIONS. In
This is doubly true if WORD_REGISTER_OPERATIONS. In
this case eliminate_regs has left non-paradoxical
subregs for push_reloads to see. Make sure it does
by forcing the reload.
@ -2955,10 +2955,10 @@ find_reloads (insn, replace, ind_levels, live_known, reload_reg_p)
don't exchange them, because operands_match is valid
only on one side of its diagonal. */
? (operands_match
[(c == commutative || c == commutative + 1)
? 2*commutative + 1 - c : c]
[(i == commutative || i == commutative + 1)
? 2*commutative + 1 - i : i])
[(c == commutative || c == commutative + 1)
? 2*commutative + 1 - c : c]
[(i == commutative || i == commutative + 1)
? 2*commutative + 1 - i : i])
: operands_match[c][i])
{
/* If we are matching a non-offsettable address where an
@ -3176,8 +3176,8 @@ find_reloads (insn, replace, ind_levels, live_known, reload_reg_p)
/* A SCRATCH is not a valid operand. */
&& GET_CODE (operand) != SCRATCH
#ifdef LEGITIMATE_PIC_OPERAND_P
&& (! CONSTANT_P (operand)
|| ! flag_pic
&& (! CONSTANT_P (operand)
|| ! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (operand))
#endif
&& (GENERAL_REGS == ALL_REGS
@ -3193,20 +3193,20 @@ find_reloads (insn, replace, ind_levels, live_known, reload_reg_p)
goto reg;
#ifdef EXTRA_CONSTRAINT
case 'Q':
case 'R':
case 'S':
case 'T':
case 'U':
case 'Q':
case 'R':
case 'S':
case 'T':
case 'U':
if (EXTRA_CONSTRAINT (operand, c))
win = 1;
break;
#endif
default:
this_alternative[i]
= (int) reg_class_subunion[this_alternative[i]][(int) REG_CLASS_FROM_LETTER (c)];
reg:
if (GET_MODE (operand) == BLKmode)
break;
@ -3247,7 +3247,7 @@ find_reloads (insn, replace, ind_levels, live_known, reload_reg_p)
/* If this is a pseudo-register that is set in the previous
insns, there's a good chance that it will already be in a
spill register and we can use that spill register. So
make this case cheaper.
make this case cheaper.
Disabled for egcs. egcs has better inheritance code and
this change causes problems with the improved reload
@ -3263,14 +3263,14 @@ find_reloads (insn, replace, ind_levels, live_known, reload_reg_p)
reload. This is consistent with other code and is
required to avoid choosing another alternative when
the constant is moved into memory by this function on
an early reload pass. Note that the test here is
an early reload pass. Note that the test here is
precisely the same as in the code below that calls
force_const_mem. */
if (CONSTANT_P (operand)
/* force_const_mem does not accept HIGH. */
&& GET_CODE (operand) != HIGH
&& ((PREFERRED_RELOAD_CLASS (operand,
(enum reg_class) this_alternative[i])
(enum reg_class) this_alternative[i])
== NO_REGS)
|| no_input_reloads)
&& operand_mode[i] != VOIDmode)
@ -3296,8 +3296,8 @@ find_reloads (insn, replace, ind_levels, live_known, reload_reg_p)
permitted for this insn. We can always reload SCRATCH
and objects with a REG_UNUSED note. */
else if (GET_CODE (operand) != SCRATCH
&& modified[i] != RELOAD_READ && no_output_reloads
&& ! find_reg_note (insn, REG_UNUSED, operand))
&& modified[i] != RELOAD_READ && no_output_reloads
&& ! find_reg_note (insn, REG_UNUSED, operand))
bad = 1;
else if (modified[i] != RELOAD_WRITE && no_input_reloads
&& ! const_to_mem)
@ -3307,7 +3307,7 @@ find_reloads (insn, replace, ind_levels, live_known, reload_reg_p)
/* We prefer to reload pseudos over reloading other things,
since such reloads may be able to be eliminated later.
If we are reloading a SCRATCH, we won't be generating any
insns, just using a register, so it is also preferred.
insns, just using a register, so it is also preferred.
So bump REJECT in other cases. Don't do this in the
case where we are forcing a constant into memory and
it will then win since we don't want to have a different
@ -3325,7 +3325,7 @@ find_reloads (insn, replace, ind_levels, live_known, reload_reg_p)
reject++;
}
/* If this operand is a pseudo register that didn't get a hard
/* If this operand is a pseudo register that didn't get a hard
reg and this alternative accepts some register, see if the
class that we want is a subset of the preferred class for this
register. If not, but it intersects that class, use the
@ -3356,7 +3356,7 @@ find_reloads (insn, replace, ind_levels, live_known, reload_reg_p)
{
/* Since we don't have a way of forming the intersection,
we just do something special if the preferred class
is a subset of the class we have; that's the most
is a subset of the class we have; that's the most
common case anyway. */
if (reg_class_subset_p (preferred_class[i],
this_alternative[i]))
@ -3375,13 +3375,13 @@ find_reloads (insn, replace, ind_levels, live_known, reload_reg_p)
if (this_alternative_earlyclobber[i]
&& this_alternative_win[i])
{
struct decomposition early_data;
struct decomposition early_data;
early_data = decompose (recog_operand[i]);
if (modified[i] == RELOAD_READ)
abort ();
if (this_alternative[i] == NO_REGS)
{
this_alternative_earlyclobber[i] = 0;
@ -3600,9 +3600,9 @@ find_reloads (insn, replace, ind_levels, live_known, reload_reg_p)
One special case that is worth checking is when we have an
output that is earlyclobber but isn't used past the insn (typically
a SCRATCH). In this case, we only need have the reload live
a SCRATCH). In this case, we only need have the reload live
through the insn itself, but not for any of our input or output
reloads.
reloads.
But we must not accidentally narrow the scope of an existing
RELOAD_OTHER reload - leave these alone.
@ -3623,7 +3623,7 @@ find_reloads (insn, replace, ind_levels, live_known, reload_reg_p)
/* force_const_mem does not accept HIGH. */
&& GET_CODE (recog_operand[i]) != HIGH
&& ((PREFERRED_RELOAD_CLASS (recog_operand[i],
(enum reg_class) goal_alternative[i])
(enum reg_class) goal_alternative[i])
== NO_REGS)
|| no_input_reloads)
&& operand_mode[i] != VOIDmode)
@ -3763,7 +3763,7 @@ find_reloads (insn, replace, ind_levels, live_known, reload_reg_p)
&& goal_alternative_matches[i] < 0
&& optimize)
{
/* For each non-matching operand that's a MEM or a pseudo-register
/* For each non-matching operand that's a MEM or a pseudo-register
that didn't get a hard register, make an optional reload.
This may get done even if the insn needs no reloads otherwise. */
@ -3857,7 +3857,7 @@ find_reloads (insn, replace, ind_levels, live_known, reload_reg_p)
operand_mode[i],
0, 1, goal_alternative_matches[i], RELOAD_OTHER);
}
/* Perform whatever substitutions on the operands we are supposed
to make due to commutativity or replacement of registers
with equivalent constants or memory slots. */
@ -3865,9 +3865,9 @@ find_reloads (insn, replace, ind_levels, live_known, reload_reg_p)
for (i = 0; i < noperands; i++)
{
/* We only do this on the last pass through reload, because it is
possible for some data (like reg_equiv_address) to be changed during
later passes. Moreover, we loose the opportunity to get a useful
reload_{in,out}_reg when we do these replacements. */
possible for some data (like reg_equiv_address) to be changed during
later passes. Moreover, we loose the opportunity to get a useful
reload_{in,out}_reg when we do these replacements. */
if (replace)
{
@ -3978,7 +3978,7 @@ find_reloads (insn, replace, ind_levels, live_known, reload_reg_p)
}
}
/* Scan all the reloads and update their type.
/* Scan all the reloads and update their type.
If a reload is for the address of an operand and we didn't reload
that operand, change the type. Similarly, change the operand number
of a reload when two operands match. If a reload is optional, treat it
@ -4023,7 +4023,7 @@ find_reloads (insn, replace, ind_levels, live_known, reload_reg_p)
/* If there's a tertiary reload we have to change it also. */
if (secondary_in_reload > 0
&& reload_secondary_in_reload[secondary_in_reload] != -1)
reload_when_needed[reload_secondary_in_reload[secondary_in_reload]]
reload_when_needed[reload_secondary_in_reload[secondary_in_reload]]
= RELOAD_FOR_OPADDR_ADDR;
}
@ -4039,7 +4039,7 @@ find_reloads (insn, replace, ind_levels, live_known, reload_reg_p)
/* If there's a tertiary reload we have to change it also. */
if (secondary_out_reload
&& reload_secondary_out_reload[secondary_out_reload] != -1)
reload_when_needed[reload_secondary_out_reload[secondary_out_reload]]
reload_when_needed[reload_secondary_out_reload[secondary_out_reload]]
= RELOAD_FOR_OPADDR_ADDR;
}
@ -4053,7 +4053,7 @@ find_reloads (insn, replace, ind_levels, live_known, reload_reg_p)
if ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS
|| reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS)
&& operand_reloadnum[reload_opnum[i]] >= 0
&& (reload_when_needed[operand_reloadnum[reload_opnum[i]]]
&& (reload_when_needed[operand_reloadnum[reload_opnum[i]]]
== RELOAD_OTHER))
reload_when_needed[i] = RELOAD_FOR_OTHER_ADDRESS;
@ -4392,8 +4392,8 @@ find_reloads_toplev (x, opnum, type, ind_levels, is_set_dest, insn)
if (reg_equiv_constant[regno] != 0 && !is_set_dest)
x = reg_equiv_constant[regno];
#if 0
/* This creates (subreg (mem...)) which would cause an unnecessary
reload of the mem. */
/* This creates (subreg (mem...)) which would cause an unnecessary
reload of the mem. */
else if (reg_equiv_mem[regno] != 0)
x = reg_equiv_mem[regno];
#endif
@ -4426,7 +4426,7 @@ find_reloads_toplev (x, opnum, type, ind_levels, is_set_dest, insn)
if (code == SUBREG && GET_CODE (SUBREG_REG (x)) == REG)
{
/* Check for SUBREG containing a REG that's equivalent to a constant.
/* Check for SUBREG containing a REG that's equivalent to a constant.
If the constant has a known value, truncate it right now.
Similarly if we are extracting a single-word of a multi-word
constant. If the constant is symbolic, allow it to be substituted
@ -4474,18 +4474,18 @@ find_reloads_toplev (x, opnum, type, ind_levels, is_set_dest, insn)
&& GET_CODE (reg_equiv_constant[regno]) == CONST_INT
&& (GET_MODE_SIZE (GET_MODE (x))
< GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
{
int shift = SUBREG_WORD (x) * BITS_PER_WORD;
if (WORDS_BIG_ENDIAN)
shift = (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
- GET_MODE_BITSIZE (GET_MODE (x))
- shift);
/* Here we use the knowledge that CONST_INTs have a
HOST_WIDE_INT field. */
if (shift >= HOST_BITS_PER_WIDE_INT)
shift = HOST_BITS_PER_WIDE_INT - 1;
return GEN_INT (INTVAL (reg_equiv_constant[regno]) >> shift);
}
{
int shift = SUBREG_WORD (x) * BITS_PER_WORD;
if (WORDS_BIG_ENDIAN)
shift = (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
- GET_MODE_BITSIZE (GET_MODE (x))
- shift);
/* Here we use the knowledge that CONST_INTs have a
HOST_WIDE_INT field. */
if (shift >= HOST_BITS_PER_WIDE_INT)
shift = HOST_BITS_PER_WIDE_INT - 1;
return GEN_INT (INTVAL (reg_equiv_constant[regno]) >> shift);
}
if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0
&& reg_equiv_constant[regno] != 0
@ -4512,7 +4512,7 @@ find_reloads_toplev (x, opnum, type, ind_levels, is_set_dest, insn)
#endif
&& (reg_equiv_address[regno] != 0
|| (reg_equiv_mem[regno] != 0
&& (! strict_memory_address_p (GET_MODE (x),
&& (! strict_memory_address_p (GET_MODE (x),
XEXP (reg_equiv_mem[regno], 0))
|| ! offsettable_memref_p (reg_equiv_mem[regno])
|| num_not_at_initial_offset))))
@ -4827,7 +4827,7 @@ find_reloads_address (mode, memrefloc, ad, loc, opnum, type, ind_levels, insn)
/* If we have an indexed stack slot, there are three possible reasons why
it might be invalid: The index might need to be reloaded, the address
might have been made by frame pointer elimination and hence have a
constant out of range, or both reasons might apply.
constant out of range, or both reasons might apply.
We can easily check for an index needing reload, but even if that is the
case, we might also have an invalid constant. To avoid making the
@ -4868,7 +4868,7 @@ find_reloads_address (mode, memrefloc, ad, loc, opnum, type, ind_levels, insn)
*loc = ad = gen_rtx_PLUS (GET_MODE (ad),
plus_constant (XEXP (XEXP (ad, 0), 0),
INTVAL (XEXP (ad, 1))),
XEXP (XEXP (ad, 0), 1));
XEXP (XEXP (ad, 0), 1));
find_reloads_address_part (XEXP (ad, 0), &XEXP (ad, 0), BASE_REG_CLASS,
GET_MODE (ad), opnum, type, ind_levels);
find_reloads_address_1 (mode, XEXP (ad, 1), 1, &XEXP (ad, 1), opnum,
@ -4876,7 +4876,7 @@ find_reloads_address (mode, memrefloc, ad, loc, opnum, type, ind_levels, insn)
return 0;
}
else if (GET_CODE (ad) == PLUS && GET_CODE (XEXP (ad, 1)) == CONST_INT
&& GET_CODE (XEXP (ad, 0)) == PLUS
&& (XEXP (XEXP (ad, 0), 1) == frame_pointer_rtx
@ -4900,7 +4900,7 @@ find_reloads_address (mode, memrefloc, ad, loc, opnum, type, ind_levels, insn)
return 0;
}
/* See if address becomes valid when an eliminable register
in a sum is replaced. */
@ -5003,7 +5003,7 @@ subst_reg_equivs (ad, insn)
&& GET_CODE (XEXP (ad, 1)) == CONST_INT)
return ad;
break;
default:
break;
}
@ -5095,9 +5095,9 @@ subst_indexed_address (addr)
&& reg_equiv_constant[regno] != 0)
op0 = reg_equiv_constant[regno];
else if (GET_CODE (op1) == REG
&& (regno = REGNO (op1)) >= FIRST_PSEUDO_REGISTER
&& reg_renumber[regno] < 0
&& reg_equiv_constant[regno] != 0)
&& (regno = REGNO (op1)) >= FIRST_PSEUDO_REGISTER
&& reg_renumber[regno] < 0
&& reg_equiv_constant[regno] != 0)
op1 = reg_equiv_constant[regno];
else if (GET_CODE (op0) == PLUS
&& (tem = subst_indexed_address (op0)) != op0)
@ -5191,7 +5191,7 @@ find_reloads_address_1 (mode, x, context, loc, opnum, type, ind_levels, insn)
REGNO (op1) + SUBREG_WORD (orig_op1));
}
if (code0 == MULT || code0 == SIGN_EXTEND || code0 == TRUNCATE
if (code0 == MULT || code0 == SIGN_EXTEND || code0 == TRUNCATE
|| code0 == ZERO_EXTEND || code1 == MEM)
{
find_reloads_address_1 (mode, orig_op0, 1, &XEXP (x, 0), opnum,
@ -5352,8 +5352,8 @@ find_reloads_address_1 (mode, x, context, loc, opnum, type, ind_levels, insn)
reloadnum
= push_reload (x, x, loc, loc,
(context ? INDEX_REG_CLASS : BASE_REG_CLASS),
GET_MODE (x), GET_MODE (x), 0, 0,
opnum, RELOAD_OTHER);
GET_MODE (x), GET_MODE (x), 0, 0,
opnum, RELOAD_OTHER);
/* If we created a new MEM based on reg_equiv_mem[REGNO], then
LOC above is part of the new MEM, not the MEM in INSN.
@ -5372,7 +5372,7 @@ find_reloads_address_1 (mode, x, context, loc, opnum, type, ind_levels, insn)
opnum, type);
reload_inc[reloadnum]
= find_inc_amount (PATTERN (this_insn), XEXP (x_orig, 0));
value = 1;
}
@ -5548,7 +5548,7 @@ find_reloads_address_1 (mode, x, context, loc, opnum, type, ind_levels, insn)
}
}
break;
default:
break;
}
@ -5926,7 +5926,7 @@ refers_to_regno_for_reload_p (regno, endregno, x, loc)
}
return (endregno > i
&& regno < i + (i < FIRST_PSEUDO_REGISTER
&& regno < i + (i < FIRST_PSEUDO_REGISTER
? HARD_REGNO_NREGS (i, GET_MODE (x))
: 1));
@ -5970,7 +5970,7 @@ refers_to_regno_for_reload_p (regno, endregno, x, loc)
return 0;
x = SET_SRC (x);
goto repeat;
default:
break;
}
@ -6009,7 +6009,7 @@ refers_to_regno_for_reload_p (regno, endregno, x, loc)
we check if any register number in X conflicts with the relevant register
numbers. If X is a constant, return 0. If X is a MEM, return 1 iff IN
contains a MEM (we don't bother checking for memory addresses that can't
conflict because we expect this to be a rare case.
conflict because we expect this to be a rare case.
This function is similar to reg_overlap_mention_p in rtlanal.c except
that we look at equivalences for pseudos that didn't get hard registers. */
@ -6079,14 +6079,14 @@ refers_to_mem_for_reload_p (x)
if (GET_CODE (x) == REG)
return (REGNO (x) >= FIRST_PSEUDO_REGISTER
&& reg_equiv_memory_loc[REGNO (x)]);
fmt = GET_RTX_FORMAT (GET_CODE (x));
for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
if (fmt[i] == 'e'
&& (GET_CODE (XEXP (x, i)) == MEM
|| refers_to_mem_for_reload_p (XEXP (x, i))))
return 1;
return 0;
}
@ -6178,12 +6178,12 @@ find_equiv_reg (goal, insn, class, other, reload_reg_p, goalreg, mode)
/* On some machines, certain regs must always be rejected
because they don't behave the way ordinary registers do. */
#ifdef OVERLAPPING_REGNO_P
if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
&& OVERLAPPING_REGNO_P (regno))
return 0;
#endif
if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
&& OVERLAPPING_REGNO_P (regno))
return 0;
#endif
/* Scan insns back from INSN, looking for one that copies
a value into or out of GOAL.
@ -6198,13 +6198,13 @@ find_equiv_reg (goal, insn, class, other, reload_reg_p, goalreg, mode)
/* If we don't want spill regs ... */
&& (! (reload_reg_p != 0
&& reload_reg_p != (short *) (HOST_WIDE_INT) 1)
/* ... then ignore insns introduced by reload; they aren't useful
and can cause results in reload_as_needed to be different
from what they were when calculating the need for spills.
If we notice an input-reload insn here, we will reject it below,
but it might hide a usable equivalent. That makes bad code.
It may even abort: perhaps no reg was spilled for this insn
because it was assumed we would find that equivalent. */
/* ... then ignore insns introduced by reload; they aren't useful
and can cause results in reload_as_needed to be different
from what they were when calculating the need for spills.
If we notice an input-reload insn here, we will reject it below,
but it might hide a usable equivalent. That makes bad code.
It may even abort: perhaps no reg was spilled for this insn
because it was assumed we would find that equivalent. */
|| INSN_UID (p) < reload_first_uid))
{
rtx tem;
@ -6325,11 +6325,11 @@ find_equiv_reg (goal, insn, class, other, reload_reg_p, goalreg, mode)
/* On some machines, certain regs must always be rejected
because they don't behave the way ordinary registers do. */
#ifdef OVERLAPPING_REGNO_P
if (OVERLAPPING_REGNO_P (valueno))
return 0;
#endif
#endif
nregs = HARD_REGNO_NREGS (regno, mode);
valuenregs = HARD_REGNO_NREGS (valueno, mode);
@ -6380,7 +6380,7 @@ find_equiv_reg (goal, insn, class, other, reload_reg_p, goalreg, mode)
|| need_stable_sp))
return 0;
#ifdef NON_SAVING_SETJMP
#ifdef NON_SAVING_SETJMP
if (NON_SAVING_SETJMP && GET_CODE (p) == NOTE
&& NOTE_LINE_NUMBER (p) == NOTE_INSN_SETJMP)
return 0;
@ -6388,9 +6388,9 @@ find_equiv_reg (goal, insn, class, other, reload_reg_p, goalreg, mode)
#ifdef INSN_CLOBBERS_REGNO_P
if ((valueno >= 0 && valueno < FIRST_PSEUDO_REGISTER
&& INSN_CLOBBERS_REGNO_P (p, valueno))
&& INSN_CLOBBERS_REGNO_P (p, valueno))
|| (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
&& INSN_CLOBBERS_REGNO_P (p, regno)))
&& INSN_CLOBBERS_REGNO_P (p, regno)))
return 0;
#endif
@ -6398,8 +6398,8 @@ find_equiv_reg (goal, insn, class, other, reload_reg_p, goalreg, mode)
{
pat = PATTERN (p);
/* Watch out for unspec_volatile, and volatile asms. */
if (volatile_insn_p (pat))
/* Watch out for unspec_volatile, and volatile asms. */
if (volatile_insn_p (pat))
return 0;
/* If this insn P stores in either GOAL or VALUE, return 0.
@ -6640,16 +6640,16 @@ regno_clobbered_p (regno, insn)
static const char *reload_when_needed_name[] =
{
"RELOAD_FOR_INPUT",
"RELOAD_FOR_OUTPUT",
"RELOAD_FOR_INPUT",
"RELOAD_FOR_OUTPUT",
"RELOAD_FOR_INSN",
"RELOAD_FOR_INPUT_ADDRESS",
"RELOAD_FOR_INPADDR_ADDRESS",
"RELOAD_FOR_OUTPUT_ADDRESS",
"RELOAD_FOR_OUTADDR_ADDRESS",
"RELOAD_FOR_OPERAND_ADDRESS",
"RELOAD_FOR_OPERAND_ADDRESS",
"RELOAD_FOR_OPADDR_ADDR",
"RELOAD_OTHER",
"RELOAD_OTHER",
"RELOAD_FOR_OTHER_ADDRESS"
};

318
gcc/reload1.c
View File

@ -165,7 +165,7 @@ static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
/* This table is the inverse mapping of spill_regs:
indexed by hard reg number,
it contains the position of that reg in spill_regs,
or -1 for something that is not in spill_regs.
or -1 for something that is not in spill_regs.
?!? This is no longer accurate. */
static short spill_reg_order[FIRST_PSEUDO_REGISTER];
@ -680,7 +680,7 @@ reload (first, global, dumpfile)
/* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
Also find all paradoxical subregs and find largest such for each pseudo.
On machines with small register classes, record hard registers that
are used for user variables. These can never be used for spills.
are used for user variables. These can never be used for spills.
Also look for a "constant" NOTE_INSN_SETJMP. This means that all
caller-saved registers must be marked live. */
@ -837,7 +837,7 @@ reload (first, global, dumpfile)
insns_need_reload = 0;
something_needs_elimination = 0;
/* Initialize to -1, which means take the first spill register. */
last_spill_reg = -1;
@ -1179,14 +1179,14 @@ reload (first, global, dumpfile)
if (flag_stack_check && ! STACK_CHECK_BUILTIN)
{
HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
static int verbose_warned = 0;
static int verbose_warned = 0;
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
size += UNITS_PER_WORD;
if (size > STACK_CHECK_MAX_FRAME_SIZE)
{
{
warning ("frame size too large for reliable stack checking");
if (! verbose_warned)
{
@ -1324,7 +1324,7 @@ maybe_fix_stack_asms ()
default:
cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
}
}
}
@ -2009,7 +2009,7 @@ find_reload_regs (chain, dumpfile)
return;
}
}
/* We know which hard regs to use, now mark the pseudos that live in them
as needing to be kicked out. */
EXECUTE_IF_SET_IN_REG_SET
@ -2296,9 +2296,9 @@ new_spill_reg (chain, i, class, nongroup, dumpfile)
if (asm_noperands (PATTERN (chain->insn)) < 0)
{
/* The error message is still correct - we know only that it wasn't
an asm statement that caused the problem, but one of the global
registers declared by the users might have screwed us. */
/* The error message is still correct - we know only that it wasn't
an asm statement that caused the problem, but one of the global
registers declared by the users might have screwed us. */
error ("fixed or forbidden register %d (%s) was spilled for class %s.",
regno, reg_names[regno], reg_class_names[class]);
error ("This may be due to a compiler bug or to impossible asm");
@ -2464,7 +2464,7 @@ alter_reg (i, from_reg)
stack_slot = gen_rtx_MEM (mode_for_size (total_size
* BITS_PER_UNIT,
MODE_INT, 1),
plus_constant (XEXP (x, 0), adjust));
plus_constant (XEXP (x, 0), adjust));
}
spill_stack_slot[from_reg] = stack_slot;
spill_stack_slot_width[from_reg] = total_size;
@ -2480,7 +2480,7 @@ alter_reg (i, from_reg)
if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
{
x = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
plus_constant (XEXP (x, 0), adjust));
plus_constant (XEXP (x, 0), adjust));
/* If this was shared among registers, must ensure we never
set it readonly since that can cause scheduling
@ -2656,7 +2656,7 @@ set_label_offsets (x, insn, initial_p)
if (p->offset != p->initial_offset)
p->can_eliminate = 0;
break;
default:
break;
}
@ -2851,7 +2851,7 @@ eliminate_regs (x, mem_mode, insn)
return x;
case MULT:
/* If this is the product of an eliminable register and a
/* If this is the product of an eliminable register and a
constant, apply the distribute law and move the constant out
so that we have (plus (mult ..) ..). This is needed in order
to keep load-address insns valid. This case is pathological.
@ -2993,7 +2993,7 @@ eliminate_regs (x, mem_mode, insn)
&& GET_CODE (insn) != INSN_LIST)
REG_NOTES (emit_insn_before (gen_rtx_USE (VOIDmode,
SUBREG_REG (x)),
insn))
insn))
= gen_rtx_EXPR_LIST (REG_EQUAL, new, NULL_RTX);
/* Ensure NEW isn't shared in case we have to reload it. */
@ -3016,10 +3016,10 @@ eliminate_regs (x, mem_mode, insn)
#ifdef WORD_REGISTER_OPERATIONS
/* On these machines, combine can create rtl of the form
(set (subreg:m1 (reg:m2 R) 0) ...)
where m1 < m2, and expects something interesting to
where m1 < m2, and expects something interesting to
happen to the entire word. Moreover, it will use the
(reg:m2 R) later, expecting all bits to be preserved.
So if the number of words is the same, preserve the
So if the number of words is the same, preserve the
subreg so that push_reloads can see it. */
&& ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
#endif
@ -3193,7 +3193,7 @@ eliminate_regs (x, mem_mode, insn)
}
else
return x;
default:
break;
}
@ -3399,7 +3399,7 @@ eliminate_regs_in_insn (insn, replace)
old_asm_operands_vec = 0;
/* Replace the body of this insn with a substituted form. If we changed
something, return non-zero.
something, return non-zero.
If we are replacing a body that was a (set X (plus Y Z)), try to
re-recognize the insn. We do this in case we had a simple addition
@ -3573,7 +3573,7 @@ verify_initial_elim_offsets ()
INITIAL_FRAME_POINTER_OFFSET (t);
if (t != reg_eliminate[0].initial_offset)
abort ();
#endif
#endif
}
/* Reset all offsets on eliminable registers to their initial values. */
@ -3734,7 +3734,7 @@ init_elim_table ()
bzero ((PTR) reg_eliminate,
sizeof(struct elim_table) * NUM_ELIMINABLE_REGS);
}
/* Does this function require a frame pointer? */
frame_pointer_needed = (! flag_omit_frame_pointer
@ -3826,7 +3826,7 @@ ior_hard_reg_set (set1, set2)
{
IOR_HARD_REG_SET (*set1, *set2);
}
/* After find_reload_regs has been run for all insn that need reloads,
and/or spill_hard_regs was called, this function is used to actually
spill pseudo registers and try to reallocate them. It also sets up the
@ -3907,7 +3907,7 @@ finish_spills (global, dumpfile)
/* Retry allocating the spilled pseudos. For each reg, merge the
various reg sets that indicate which hard regs can't be used,
and call retry_global_alloc.
We change spill_pseudos here to only contain pseudos that did not
We change spill_pseudos here to only contain pseudos that did not
get a new hard register. */
for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
if (reg_old_renumber[i] != reg_renumber[i])
@ -3962,7 +3962,7 @@ finish_spills (global, dumpfile)
int regno = reg_renumber[i];
if (reg_old_renumber[i] == regno)
continue;
alter_reg (i, reg_old_renumber[i]);
reg_old_renumber[i] = regno;
if (dumpfile)
@ -3978,7 +3978,7 @@ finish_spills (global, dumpfile)
return something_changed;
}
/* Find all paradoxical subregs within X and update reg_max_ref_width.
/* Find all paradoxical subregs within X and update reg_max_ref_width.
Also mark any hard registers used to store user variables as
forbidden from being used for spill registers. */
@ -4017,7 +4017,7 @@ scan_paradoxical_subregs (x)
reg_max_ref_width[REGNO (SUBREG_REG (x))]
= GET_MODE_SIZE (GET_MODE (x));
return;
default:
break;
}
@ -4040,7 +4040,7 @@ static int
hard_reg_use_compare (p1p, p2p)
const GENERIC_PTR p1p;
const GENERIC_PTR p2p;
{
{
struct hard_reg_n_uses *p1 = (struct hard_reg_n_uses *)p1p;
struct hard_reg_n_uses *p2 = (struct hard_reg_n_uses *)p2p;
int bad1 = TEST_HARD_REG_BIT (bad_spill_regs, p1->regno);
@ -4082,7 +4082,7 @@ count_pseudo (n_uses, reg)
nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
while (nregs-- > 0)
n_uses[r++].uses += REG_N_REFS (reg);
n_uses[r++].uses += REG_N_REFS (reg);
}
/* Choose the order to consider regs for use as reload registers
based on how much trouble would be caused by spilling one.
@ -4287,7 +4287,7 @@ reload_as_needed (live_known)
Record the choices of reload reg in reload_reg_rtx. */
choose_reload_regs (chain);
/* Merge any reloads that we didn't combine for fear of
/* Merge any reloads that we didn't combine for fear of
increasing the number of spill registers needed but now
discover can be safely merged. */
if (SMALL_REGISTER_CLASSES)
@ -4357,7 +4357,7 @@ reload_as_needed (live_known)
some other (e.g. output operand) pseudo. */
&& (reg_reloaded_contents[REGNO (reload_reg_rtx[i])]
== REGNO (XEXP (in_reg, 0))))
{
rtx reload_reg = reload_reg_rtx[i];
enum machine_mode mode = GET_MODE (reload_reg);
@ -4397,7 +4397,7 @@ reload_as_needed (live_known)
reload_reg, p);
break;
}
}
break;
}
@ -4755,7 +4755,7 @@ clear_reload_reg_in_use (regno, opnum, type, mode)
more then what would be necessary if we used a HARD_REG_SET here.
But this should only happen very infrequently, so there should
be no reason to worry about it. */
start_regno = regno;
end_regno = regno + nregs;
if (check_opnum || check_any)
@ -4857,8 +4857,8 @@ reload_reg_free_p (regno, opnum, type)
case RELOAD_FOR_INPADDR_ADDRESS:
/* Can't use a register if it is used for an input address
for this operand or used as an input in an earlier
one. */
for this operand or used as an input in an earlier
one. */
if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
return 0;
@ -4882,8 +4882,8 @@ reload_reg_free_p (regno, opnum, type)
case RELOAD_FOR_OUTADDR_ADDRESS:
/* Can't use a register if it is used for an output address
for this operand or used as an output in this or a
later operand. */
for this operand or used as an output in this or a
later operand. */
if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
return 0;
@ -4903,8 +4903,8 @@ reload_reg_free_p (regno, opnum, type)
case RELOAD_FOR_OPADDR_ADDR:
for (i = 0; i < reload_n_operands; i++)
if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
return 0;
if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
return 0;
return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
@ -4964,7 +4964,7 @@ reload_reg_reaches_end_p (regno, opnum, type)
return 1;
/* If this use is for part of the insn,
its value reaches if no subsequent part uses the same register.
its value reaches if no subsequent part uses the same register.
Just like the above function, don't try to do this with lots
of fallthroughs. */
@ -5015,7 +5015,7 @@ reload_reg_reaches_end_p (regno, opnum, type)
case RELOAD_FOR_INPUT:
/* Similar to input address, except we start at the next operand for
both input and input address and we do not check for
both input and input address and we do not check for
RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
would conflict. */
@ -5095,7 +5095,7 @@ reloads_conflict (r1, r2)
switch (r1_type)
{
case RELOAD_FOR_INPUT:
return (r2_type == RELOAD_FOR_INSN
return (r2_type == RELOAD_FOR_INSN
|| r2_type == RELOAD_FOR_OPERAND_ADDRESS
|| r2_type == RELOAD_FOR_OPADDR_ADDR
|| r2_type == RELOAD_FOR_INPUT
@ -5124,7 +5124,7 @@ reloads_conflict (r1, r2)
|| r2_type == RELOAD_FOR_OPERAND_ADDRESS);
case RELOAD_FOR_OPADDR_ADDR:
return (r2_type == RELOAD_FOR_INPUT
return (r2_type == RELOAD_FOR_INPUT
|| r2_type == RELOAD_FOR_OPADDR_ADDR);
case RELOAD_FOR_OUTPUT:
@ -5190,7 +5190,7 @@ int reload_spill_index[MAX_RELOADS];
register. */
static int
reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum,
ignore_address_reloads)
ignore_address_reloads)
int regno;
int opnum;
enum reload_type type;
@ -5231,12 +5231,12 @@ reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum,
case RELOAD_OTHER:
time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
break;
/* For each input, we might have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
respectively, to the time values for these, we get distinct time
values. To get distinct time values for each operand, we have to
multiply opnum by at least three. We round that up to four because
multiply by four is often cheaper. */
/* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
respectively, to the time values for these, we get distinct time
values. To get distinct time values for each operand, we have to
multiply opnum by at least three. We round that up to four because
multiply by four is often cheaper. */
case RELOAD_FOR_INPADDR_ADDRESS:
time1 = opnum * 4 + 2;
break;
@ -5249,8 +5249,8 @@ reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum,
time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
break;
case RELOAD_FOR_OPADDR_ADDR:
/* opnum * 4 + 4
<= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
/* opnum * 4 + 4
<= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
time1 = MAX_RECOG_OPERANDS * 4 + 1;
break;
case RELOAD_FOR_OPERAND_ADDRESS:
@ -5319,8 +5319,8 @@ reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum,
case RELOAD_FOR_INPUT:
time2 = reload_opnum[i] * 4 + 4;
break;
/* reload_opnum[i] * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
== MAX_RECOG_OPERAND * 4 */
/* reload_opnum[i] * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
== MAX_RECOG_OPERAND * 4 */
case RELOAD_FOR_OPADDR_ADDR:
if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
&& ignore_address_reloads
@ -5335,13 +5335,13 @@ reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum,
time2 = MAX_RECOG_OPERANDS * 4 + 3;
break;
case RELOAD_FOR_OUTPUT:
/* All RELOAD_FOR_OUTPUT reloads become live just after the
instruction is executed. */
/* All RELOAD_FOR_OUTPUT reloads become live just after the
instruction is executed. */
time2 = MAX_RECOG_OPERANDS * 4 + 4;
break;
/* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
the RELOAD_FOR_OUTPUT reloads, so assign it the same time
value. */
/* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
the RELOAD_FOR_OUTPUT reloads, so assign it the same time
value. */
case RELOAD_FOR_OUTADDR_ADDRESS:
if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
&& ignore_address_reloads
@ -5438,7 +5438,7 @@ allocate_reload_reg (chain, r, last_reload, noerror)
of leapfrogging each other. Don't do this, however, when we have
group needs and failure would be fatal; if we only have a relatively
small number of spill registers, and more than one of them has
group needs, then by starting in the middle, we may end up
group needs, then by starting in the middle, we may end up
allocating the first one in such a way that we are not left with
sufficient groups to handle the rest. */
@ -5446,7 +5446,7 @@ allocate_reload_reg (chain, r, last_reload, noerror)
i = last_spill_reg;
else
i = -1;
for (count = 0; count < n_spills; count++)
{
int class = (int) reload_reg_class[r];
@ -5460,14 +5460,14 @@ allocate_reload_reg (chain, r, last_reload, noerror)
if ((reload_reg_free_p (regnum, reload_opnum[r],
reload_when_needed[r])
|| (reload_in[r]
/* We check reload_reg_used to make sure we
don't clobber the return register. */
/* We check reload_reg_used to make sure we
don't clobber the return register. */
&& ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
&& reload_reg_free_for_value_p (regnum,
reload_opnum[r],
reload_when_needed[r],
reload_in[r],
reload_out[r], r, 1)))
reload_opnum[r],
reload_when_needed[r],
reload_in[r],
reload_out[r], r, 1)))
&& TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
&& HARD_REGNO_MODE_OK (regnum, reload_mode[r])
/* Look first for regs to share, then for unshared. But
@ -5536,7 +5536,7 @@ allocate_reload_reg (chain, r, last_reload, noerror)
if (new == 0 || GET_MODE (new) != reload_mode[r])
spill_reg_rtx[i] = new
= gen_rtx_REG (reload_mode[r], spill_regs[i]);
regno = true_regnum (new);
/* Detect when the reload reg can't hold the reload mode.
@ -5661,7 +5661,7 @@ choose_reload_regs (chain)
}
IOR_COMPL_HARD_REG_SET (reload_reg_used, chain->used_spill_regs);
#if 0 /* Not needed, now that we can always retry without inheritance. */
/* See if we have more mandatory reloads than spill regs.
If so, then we cannot risk optimizations that could prevent
@ -5699,10 +5699,10 @@ choose_reload_regs (chain)
reload_spill_index[j] = -1;
reload_mode[j]
= (reload_inmode[j] == VOIDmode
= ((reload_inmode[j] == VOIDmode
|| (GET_MODE_SIZE (reload_outmode[j])
> GET_MODE_SIZE (reload_inmode[j])))
? reload_outmode[j] : reload_inmode[j];
? reload_outmode[j] : reload_inmode[j]);
reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]);
@ -5893,7 +5893,7 @@ choose_reload_regs (chain)
{
enum reg_class class = reload_reg_class[r], last_class;
rtx last_reg = reg_last_reload_reg[regno];
i = REGNO (last_reg) + word;
last_class = REGNO_REG_CLASS (i);
if ((GET_MODE_SIZE (GET_MODE (last_reg))
@ -6177,7 +6177,7 @@ choose_reload_regs (chain)
&& reg_classes_intersect_p (reload_reg_class[r],
reload_reg_class[s]))
|| reload_nregs[s] < reload_nregs[r])
break;
break;
}
if (i == n_reloads)
@ -6270,15 +6270,15 @@ choose_reload_regs (chain)
check_reg = reload_reg_rtx[r];
else if (reload_override_in[r]
&& (GET_CODE (reload_override_in[r]) == REG
|| GET_CODE (reload_override_in[r]) == SUBREG))
|| GET_CODE (reload_override_in[r]) == SUBREG))
check_reg = reload_override_in[r];
else
continue;
if (! reload_reg_free_for_value_p (true_regnum (check_reg),
reload_opnum[r],
reload_when_needed[r],
reload_in[r],
(reload_inherited[r]
reload_opnum[r],
reload_when_needed[r],
reload_in[r],
(reload_inherited[r]
? reload_out[r] : const0_rtx),
r, 1))
{
@ -6387,7 +6387,7 @@ deallocate_reload_reg (r)
/* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
reloads of the same item for fear that we might not have enough reload
registers. However, normally they will get the same reload register
and hence actually need not be loaded twice.
and hence actually need not be loaded twice.
Here we check for the most common case of this phenomenon: when we have
a number of reloads for the same object, each of which were allocated
@ -6492,7 +6492,7 @@ merge_assigned_reloads (insn)
? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
}
}
}
}
/* Output insns to reload values in and out of the chosen reload regs. */
@ -6790,7 +6790,7 @@ emit_reload_insns (chain)
uses the same reg first. */
&& reload_reg_free_for_value_p (REGNO (reloadreg),
reload_opnum[j],
reload_when_needed[j],
reload_when_needed[j],
old, reload_out[j],
j, 0))
{
@ -6871,12 +6871,12 @@ emit_reload_insns (chain)
equivalent MEM, we must fall back to reload_in, which
will have all the necessary substitutions registered.
Likewise for a pseudo that can't be replaced with its
equivalent constant.
equivalent constant.
Take extra care for subregs of such pseudos. Note that
we cannot use reg_equiv_mem in this case because it is
not in the right mode. */
tmp = oldequiv;
if (GET_CODE (tmp) == SUBREG)
tmp = SUBREG_REG (tmp);
@ -6964,7 +6964,7 @@ emit_reload_insns (chain)
to see if it is being used as a scratch or intermediate
register and generate code appropriately. If we need
a scratch register, use REAL_OLDEQUIV since the form of
the insn may depend on the actual address if it is
the insn may depend on the actual address if it is
a MEM. */
if (second_reload_reg)
@ -6985,7 +6985,7 @@ emit_reload_insns (chain)
if (tertiary_icode != CODE_FOR_nothing)
{
rtx third_reload_reg
= reload_reg_rtx[reload_secondary_in_reload[secondary_reload]];
= reload_reg_rtx[reload_secondary_in_reload[secondary_reload]];
emit_insn ((GEN_FCN (tertiary_icode)
(second_reload_reg, real_oldequiv,
@ -7064,12 +7064,12 @@ emit_reload_insns (chain)
/* There doesn't seem to be any reason to restrict this to pseudos
and doing so loses in the case where we are copying from a
register of the wrong class. */
&& REGNO (spill_reg_stored_to[REGNO (reload_reg_rtx[j])])
>= FIRST_PSEUDO_REGISTER
&& (REGNO (spill_reg_stored_to[REGNO (reload_reg_rtx[j])])
>= FIRST_PSEUDO_REGISTER)
#endif
/* The insn might have already some references to stackslots
replaced by MEMs, while reload_out_reg still names the
original pseudo. */
/* The insn might have already some references to stackslots
replaced by MEMs, while reload_out_reg still names the
original pseudo. */
&& (dead_or_set_p (insn,
spill_reg_stored_to[REGNO (reload_reg_rtx[j])])
|| rtx_equal_p (spill_reg_stored_to[REGNO (reload_reg_rtx[j])],
@ -7088,7 +7088,7 @@ emit_reload_insns (chain)
store. */
{
rtx pseudo = reload_out_reg[j];
if (pseudo
&& GET_CODE (pseudo) == REG
&& ! rtx_equal_p (reload_in_reg[j], pseudo)
@ -7320,8 +7320,8 @@ emit_reload_insns (chain)
has and where the actual store to the pseudo is
made; leave new_spill_reg_store alone. */
else if (s >= 0
&& SET_SRC (set) == reload_reg_rtx[j]
&& SET_DEST (set) == reload_reg_rtx[s])
&& SET_SRC (set) == reload_reg_rtx[j]
&& SET_DEST (set) == reload_reg_rtx[s])
{
/* Usually the next instruction will be the
secondary reload insn; if we can confirm
@ -7407,9 +7407,9 @@ emit_reload_insns (chain)
if (n_basic_blocks)
{
if (BLOCK_HEAD (chain->block) == insn)
BLOCK_HEAD (chain->block) = NEXT_INSN (before_insn);
BLOCK_HEAD (chain->block) = NEXT_INSN (before_insn);
if (BLOCK_END (chain->block) == insn)
BLOCK_END (chain->block) = PREV_INSN (following_insn);
BLOCK_END (chain->block) = PREV_INSN (following_insn);
}
/* For all the spill regs newly reloaded in this instruction,
@ -7425,33 +7425,33 @@ emit_reload_insns (chain)
register int i = reload_spill_index[r];
/* If this is a non-inherited input reload from a pseudo, we must
clear any memory of a previous store to the same pseudo. Only do
something if there will not be an output reload for the pseudo
being reloaded. */
clear any memory of a previous store to the same pseudo. Only do
something if there will not be an output reload for the pseudo
being reloaded. */
if (reload_in_reg[r] != 0
&& ! (reload_inherited[r] || reload_override_in[r]))
{
rtx reg = reload_in_reg[r];
&& ! (reload_inherited[r] || reload_override_in[r]))
{
rtx reg = reload_in_reg[r];
if (GET_CODE (reg) == SUBREG)
if (GET_CODE (reg) == SUBREG)
reg = SUBREG_REG (reg);
if (GET_CODE (reg) == REG
if (GET_CODE (reg) == REG
&& REGNO (reg) >= FIRST_PSEUDO_REGISTER
&& ! reg_has_output_reload[REGNO (reg)])
{
int nregno = REGNO (reg);
if (reg_last_reload_reg[nregno])
{
int last_regno = REGNO (reg_last_reload_reg[nregno]);
{
int last_regno = REGNO (reg_last_reload_reg[nregno]);
if (reg_reloaded_contents[last_regno] == nregno)
if (reg_reloaded_contents[last_regno] == nregno)
spill_reg_store[last_regno] = 0;
}
}
}
}
/* I is nonneg if this reload used a register.
If reload_reg_rtx[r] is 0, this is an optional reload
that we opted to ignore. */
@ -7508,7 +7508,7 @@ emit_reload_insns (chain)
reg_last_reload_reg[nregno] = reload_reg_rtx[r];
/* If NREGNO is a hard register, it may occupy more than
one register. If it does, say what is in the
one register. If it does, say what is in the
rest of the registers assuming that both registers
agree on how many words the object takes. If not,
invalidate the subsequent registers. */
@ -7560,7 +7560,7 @@ emit_reload_insns (chain)
nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
: HARD_REGNO_NREGS (nregno,
GET_MODE (reload_reg_rtx[r])));
reg_last_reload_reg[nregno] = reload_reg_rtx[r];
if (nregno < FIRST_PSEUDO_REGISTER)
@ -7697,7 +7697,7 @@ emit_reload_insns (chain)
/* Emit code to perform a reload from IN (which may be a reload register) to
OUT (which may also be a reload register). IN or OUT is from operand
OPNUM with reload type TYPE.
OPNUM with reload type TYPE.
Returns first insn emitted. */
@ -7936,7 +7936,7 @@ delete_output_reload (insn, j, last_reload_reg)
int n_inherited = 0;
register rtx i1;
rtx substed;
/* Get the raw pseudo-register referred to. */
while (GET_CODE (reg) == SUBREG)
@ -8288,7 +8288,7 @@ inc_for_reload (reloadreg, in, value, inc_amount)
add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
gen_rtx_PLUS (GET_MODE (incloc),
incloc, inc)));
code = recog_memoized (add_insn);
if (code >= 0)
{
@ -8423,7 +8423,7 @@ count_occurrences (x, find)
if (SET_DEST (x) == find)
return count_occurrences (SET_SRC (x), find);
break;
default:
break;
}
@ -8519,8 +8519,8 @@ reload_cse_invalidate_regno (regno, mode, clobber)
&& refers_to_regno_p (regno, endregno, XEXP (x, 0), NULL_PTR))
{
/* If this is the only entry on the list, clear
reg_values[i]. Otherwise, just clear this entry on
the list. */
reg_values[i]. Otherwise, just clear this entry on
the list. */
if (XEXP (x, 1) == 0 && x == reg_values[i])
{
reg_values[i] = 0;
@ -8641,8 +8641,8 @@ reload_cse_invalidate_mem (mem_rtx)
&& reload_cse_mem_conflict_p (mem_rtx, XEXP (x, 0)))
{
/* If this is the only entry on the list, clear
reg_values[i]. Otherwise, just clear this entry on
the list. */
reg_values[i]. Otherwise, just clear this entry on
the list. */
if (XEXP (x, 1) == 0 && x == reg_values[i])
{
reg_values[i] = 0;
@ -8685,7 +8685,7 @@ reload_cse_invalidate_rtx (dest, ignore)
This function also detects cases where we load a value from memory
into two different registers, and (if memory is more expensive than
registers) changes it to simply copy the first register into the
second register.
second register.
Another optimization is performed that scans the operands of each
instruction to see whether the value is already available in a
@ -8726,14 +8726,14 @@ reload_cse_regs_1 (first)
if (GET_CODE (insn) == CODE_LABEL)
{
/* Forget all the register values at a code label. We don't
try to do anything clever around jumps. */
try to do anything clever around jumps. */
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
reg_values[i] = 0;
continue;
}
#ifdef NON_SAVING_SETJMP
#ifdef NON_SAVING_SETJMP
if (NON_SAVING_SETJMP && GET_CODE (insn) == NOTE
&& NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
{
@ -8760,7 +8760,7 @@ reload_cse_regs_1 (first)
reload_cse_invalidate_mem (callmem);
}
/* Forget all the register values at a volatile asm. */
if (GET_CODE (insn) == INSN
&& GET_CODE (PATTERN (insn)) == ASM_OPERANDS
@ -8807,7 +8807,7 @@ reload_cse_regs_1 (first)
apply_change_group ();
else
reload_cse_simplify_operands (insn);
reload_cse_record_set (body, body);
}
else if (GET_CODE (body) == PARALLEL)
@ -8816,7 +8816,7 @@ reload_cse_regs_1 (first)
rtx value = NULL_RTX;
/* If every action in a PARALLEL is a noop, we can delete
the entire PARALLEL. */
the entire PARALLEL. */
for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
{
rtx part = XVECEXP (body, 0, i);
@ -8854,7 +8854,7 @@ reload_cse_regs_1 (first)
/* We're done with this insn. */
continue;
}
/* It's not a no-op, but we can try to simplify it. */
for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
if (GET_CODE (XVECEXP (body, 0, i)) == SET)
@ -8866,7 +8866,7 @@ reload_cse_regs_1 (first)
reload_cse_simplify_operands (insn);
/* Look through the PARALLEL and record the values being
set, if possible. Also handle any CLOBBERs. */
set, if possible. Also handle any CLOBBERs. */
for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
{
rtx x = XVECEXP (body, 0, i);
@ -8882,8 +8882,8 @@ reload_cse_regs_1 (first)
#ifdef AUTO_INC_DEC
/* Clobber any registers which appear in REG_INC notes. We
could keep track of the changes to their values, but it is
unlikely to help. */
could keep track of the changes to their values, but it is
unlikely to help. */
{
rtx x;
@ -8894,7 +8894,7 @@ reload_cse_regs_1 (first)
#endif
/* Look for any CLOBBERs in CALL_INSN_FUNCTION_USAGE, but only
after we have processed the insn. */
after we have processed the insn. */
if (GET_CODE (insn) == CALL_INSN)
{
rtx x;
@ -8998,12 +8998,12 @@ reload_cse_noop_set_p (set, insn)
ret = 1;
/* Check for setting a register to a value which we already know
is in the register. */
is in the register. */
else if (reload_cse_regno_equal_p (dreg, src, dest_mode))
ret = 1;
/* Check for setting a register DREG to another register SREG
where SREG is equal to a value which is already in DREG. */
where SREG is equal to a value which is already in DREG. */
else if (sreg >= 0)
{
rtx x;
@ -9035,7 +9035,7 @@ reload_cse_noop_set_p (set, insn)
else if (GET_CODE (dest) == MEM)
{
/* Check for storing a register to memory when we know that the
register is equivalent to the memory location. */
register is equivalent to the memory location. */
if (sreg >= 0
&& reload_cse_regno_equal_p (sreg, dest, dest_mode)
&& ! side_effects_p (dest))
@ -9098,7 +9098,7 @@ reload_cse_simplify_set (set, insn)
gen_rtx_REG (dest_mode, i), 1);
/* Go back to the obstack we are using for temporary
storage. */
storage. */
push_obstacks (&reload_obstack, &reload_obstack);
if (validated)
@ -9109,8 +9109,8 @@ reload_cse_simplify_set (set, insn)
}
/* Try to replace operands in INSN with equivalent values that are already
in registers. This can be viewed as optional reloading.
in registers. This can be viewed as optional reloading.
For each non-register operand in the insn, see if any hard regs are
known to be equivalent to that operand. Record the alternatives which
can accept these hard registers. Among all alternatives, select the
@ -9127,7 +9127,7 @@ reload_cse_simplify_operands (insn)
int i,j;
const char *constraints[MAX_RECOG_OPERANDS];
/* Vector recording how bad an alternative is. */
int *alternative_reject;
/* Vector recording how many registers can be introduced by choosing
@ -9140,7 +9140,7 @@ reload_cse_simplify_operands (insn)
/* Array of alternatives, sorted in order of decreasing desirability. */
int *alternative_order;
rtx reg = gen_rtx_REG (VOIDmode, -1);
extract_insn (insn);
if (recog_n_alternatives == 0 || recog_n_operands == 0)
@ -9209,12 +9209,12 @@ reload_cse_simplify_operands (insn)
for (;;)
{
char c = *p++;
switch (c)
{
case '=': case '+': case '?':
case '#': case '&': case '!':
case '*': case '%':
case '*': case '%':
case '0': case '1': case '2': case '3': case '4':
case 'm': case '<': case '>': case 'V': case 'o':
case 'E': case 'F': case 'G': case 'H':
@ -9289,12 +9289,12 @@ reload_cse_simplify_operands (insn)
best_nregs = this_nregs;
}
}
tmp = alternative_order[best];
alternative_order[best] = alternative_order[i];
alternative_order[i] = tmp;
}
/* Substitute the operands as determined by op_alt_regno for the best
alternative. */
j = alternative_order[0];
@ -9441,7 +9441,7 @@ reload_cse_record_set (set, body)
int i;
/* This is an assignment to a register. Update the value we
have stored for the register. */
have stored for the register. */
if (sreg >= 0)
{
rtx x;
@ -9460,24 +9460,24 @@ reload_cse_record_set (set, body)
if (dest_mode == GET_MODE (XEXP (x, 0)))
tmp = XEXP (x, 0);
else if (GET_MODE_BITSIZE (dest_mode)
> GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
> GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
continue;
else
tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
if (tmp)
reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, tmp,
reg_values[dreg]);
}
}
}
else
reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, src, NULL_RTX);
/* We've changed DREG, so invalidate any values held by other
registers that depend upon it. */
registers that depend upon it. */
reload_cse_invalidate_regno (dreg, dest_mode, 0);
/* If this assignment changes more than one hard register,
forget anything we know about the others. */
forget anything we know about the others. */
for (i = 1; i < HARD_REGNO_NREGS (dreg, dest_mode); i++)
reg_values[dreg + i] = 0;
}
@ -9487,7 +9487,7 @@ reload_cse_record_set (set, body)
reload_cse_invalidate_mem (dest);
/* If we're storing a register to memory, add DEST to the list
in REG_VALUES. */
in REG_VALUES. */
if (sreg >= 0 && ! side_effects_p (dest))
reg_values[sreg] = gen_rtx_EXPR_LIST (dest_mode, dest,
reg_values[sreg]);
@ -9610,7 +9610,7 @@ reload_combine ()
/* We cannot do our optimization across labels. Invalidating all the use
information we have would be costly, so we just note where the label
is and then later disable any optimization that would cross it. */
is and then later disable any optimization that would cross it. */
if (GET_CODE (insn) == CODE_LABEL)
last_label_ruid = reload_combine_ruid;
if (GET_CODE (insn) == BARRIER)
@ -9670,11 +9670,11 @@ reload_combine ()
}
else
{
/* Otherwise, look for a free index register. Since we have
checked above that neiter REG nor BASE are index registers,
if we find anything at all, it will be different from these
two registers. */
for (i = first_index_reg; i <= last_index_reg; i++)
/* Otherwise, look for a free index register. Since we have
checked above that neiter REG nor BASE are index registers,
if we find anything at all, it will be different from these
two registers. */
for (i = first_index_reg; i <= last_index_reg; i++)
{
if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i)
&& reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
@ -9825,7 +9825,7 @@ reload_combine_note_store (dst, set)
regno += REGNO (dst);
/* note_stores might have stripped a STRICT_LOW_PART, so we have to be
careful with registers / register parts that are not full words.
careful with registers / register parts that are not full words.
Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
if (GET_CODE (set) != SET
@ -9884,7 +9884,7 @@ reload_combine_note_use (xp, insn)
break;
offset = XEXP (x, 1);
x = XEXP (x, 0);
/* Fall through. */
/* Fall through. */
case REG:
{
int regno = REGNO (x);
@ -10023,9 +10023,9 @@ reload_cse_move2add (first)
/* ??? We don't know how zero / sign extension is handled, hence
we can't go from a narrower to a wider mode. */
if (reg_set_luid[regno] > last_label_luid
&& (GET_MODE_SIZE (GET_MODE (reg))
<= GET_MODE_SIZE (reg_mode[regno]))
&& GET_CODE (reg_offset[regno]) == CONST_INT)
&& (GET_MODE_SIZE (GET_MODE (reg))
<= GET_MODE_SIZE (reg_mode[regno]))
&& GET_CODE (reg_offset[regno]) == CONST_INT)
{
/* Try to transform (set (REGX) (CONST_INT A))
...