OpenE2K/gcc
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

invoke.texi (core2): Add item.

Browse Source 
2006-11-18  Vladimir Makarov  <vmakarov@redhat.com>

	* doc/invoke.texi (core2): Add item.

	* config/i386/i386.h (TARGET_CORE2, TARGET_CPU_DEFAULT_core2): New
	macros.
	(TARGET_CPU_CPP_BUILTINS): Add code for core2.
	(TARGET_CPU_DEFAULT_generic): Change value.
	(TARGET_CPU_DEFAULT_NAMES): Add core2.
	(processor_type): Add new constant PROCESSOR_CORE2.

	* config/i386/i386.md (cpu): Add core2.

	* config/i386/i386.c (core2_cost): New initialized variable.
	(m_CORE2): New macro.
	(x86_use_leave, x86_push_memory, x86_movx, x86_unroll_strlen,
	x86_deep_branch, x86_partial_reg_stall, x86_use_simode_fiop,
	x86_use_cltd, x86_promote_QImode, x86_sub_esp_4, x86_sub_esp_8,
	x86_add_esp_4, x86_add_esp_8, x86_integer_DFmode_moves,
	x86_partial_reg_dependency, x86_memory_mismatch_stall,
	x86_accumulate_outgoing_args, x86_prologue_using_move,
	x86_epilogue_using_move, x86_arch_always_fancy_math_387,
	x86_sse_partial_reg_dependency, x86_rep_movl_optimal,
	x86_use_incdec, x86_four_jump_limit, x86_schedule,
	x86_pad_returns): Add m_CORE2.
	(override_options): Add entries for Core2.
	(ix86_issue_rate): Add case for Core2.

From-SVN: r118973
This commit is contained in:
Vladimir Makarov 2006-11-18 18:43:19 +00:00 committed by Vladimir Makarov
parent a357b5ae8d
commit 05f85dbb6d
5 changed files with 131 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
gcc/ChangeLog
View File

@ -1,3 +1,31 @@
2006-11-18 Vladimir Makarov <vmakarov@redhat.com>
* doc/invoke.texi (core2): Add item.
* config/i386/i386.h (TARGET_CORE2, TARGET_CPU_DEFAULT_core2): New
macros.
(TARGET_CPU_CPP_BUILTINS): Add code for core2.
(TARGET_CPU_DEFAULT_generic): Change value.
(TARGET_CPU_DEFAULT_NAMES): Add core2.
(processor_type): Add new constant PROCESSOR_CORE2.
* config/i386/i386.md (cpu): Add core2.
* config/i386/i386.c (core2_cost): New initialized variable.
(m_CORE2): New macro.
(x86_use_leave, x86_push_memory, x86_movx, x86_unroll_strlen,
x86_deep_branch, x86_partial_reg_stall, x86_use_simode_fiop,
x86_use_cltd, x86_promote_QImode, x86_sub_esp_4, x86_sub_esp_8,
x86_add_esp_4, x86_add_esp_8, x86_integer_DFmode_moves,
x86_partial_reg_dependency, x86_memory_mismatch_stall,
x86_accumulate_outgoing_args, x86_prologue_using_move,
x86_epilogue_using_move, x86_arch_always_fancy_math_387,
x86_sse_partial_reg_dependency, x86_rep_movl_optimal,
x86_use_incdec, x86_four_jump_limit, x86_schedule,
x86_pad_returns): Add m_CORE2.
(override_options): Add entries for Core2.
(ix86_issue_rate): Add case for Core2.
2006-11-18 Aldy Hernandez <aldyh@redhat.com>
* doc/invoke.texi: Fix mno-isel typo.

114
gcc/config/i386/i386.c
View File

@ -658,6 +658,58 @@ struct processor_costs nocona_cost = {
COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
};
static const
struct processor_costs core2_cost = {
COSTS_N_INSNS (1), /* cost of an add instruction */
COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
COSTS_N_INSNS (1), /* variable shift costs */
COSTS_N_INSNS (1), /* constant shift costs */
{COSTS_N_INSNS (3), /* cost of starting multiply for QI */
COSTS_N_INSNS (3), /* HI */
COSTS_N_INSNS (3), /* SI */
COSTS_N_INSNS (3), /* DI */
COSTS_N_INSNS (3)}, /* other */
0, /* cost of multiply per each bit set */
{COSTS_N_INSNS (22), /* cost of a divide/mod for QI */
COSTS_N_INSNS (22), /* HI */
COSTS_N_INSNS (22), /* SI */
COSTS_N_INSNS (22), /* DI */
COSTS_N_INSNS (22)}, /* other */
COSTS_N_INSNS (1), /* cost of movsx */
COSTS_N_INSNS (1), /* cost of movzx */
8, /* "large" insn */
16, /* MOVE_RATIO */
2, /* cost for loading QImode using movzbl */
{6, 6, 6}, /* cost of loading integer registers
in QImode, HImode and SImode.
Relative to reg-reg move (2). */
{4, 4, 4}, /* cost of storing integer registers */
2, /* cost of reg,reg fld/fst */
{6, 6, 6}, /* cost of loading fp registers
in SFmode, DFmode and XFmode */
{4, 4, 4}, /* cost of loading integer registers */
2, /* cost of moving MMX register */
{6, 6}, /* cost of loading MMX registers
in SImode and DImode */
{4, 4}, /* cost of storing MMX registers
in SImode and DImode */
2, /* cost of moving SSE register */
{6, 6, 6}, /* cost of loading SSE registers
in SImode, DImode and TImode */
{4, 4, 4}, /* cost of storing SSE registers
in SImode, DImode and TImode */
2, /* MMX or SSE register to integer */
128, /* size of prefetch block */
8, /* number of parallel prefetches */
3, /* Branch cost */
COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
COSTS_N_INSNS (5), /* cost of FMUL instruction. */
COSTS_N_INSNS (32), /* cost of FDIV instruction. */
COSTS_N_INSNS (1), /* cost of FABS instruction. */
COSTS_N_INSNS (1), /* cost of FCHS instruction. */
COSTS_N_INSNS (58), /* cost of FSQRT instruction. */
};
/* Generic64 should produce code tuned for Nocona and K8. */
static const
struct processor_costs generic64_cost = {
@ -787,26 +839,27 @@ const struct processor_costs *ix86_cost = &pentium_cost;
#define m_K8 (1<<PROCESSOR_K8)
#define m_ATHLON_K8 (m_K8 | m_ATHLON)
#define m_NOCONA (1<<PROCESSOR_NOCONA)
#define m_CORE2 (1<<PROCESSOR_CORE2)
#define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
#define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
#define m_GENERIC (m_GENERIC32 | m_GENERIC64)
/* Generic instruction choice should be common subset of supported CPUs
(PPro/PENT4/NOCONA/Athlon/K8). */
(PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
/* Leave is not affecting Nocona SPEC2000 results negatively, so enabling for
Generic64 seems like good code size tradeoff. We can't enable it for 32bit
generic because it is not working well with PPro base chips. */
const int x86_use_leave = m_386 | m_K6_GEODE | m_ATHLON_K8 | m_GENERIC64;
const int x86_push_memory = m_386 | m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC;
const int x86_use_leave = m_386 | m_K6_GEODE | m_ATHLON_K8 | m_CORE2 | m_GENERIC64;
const int x86_push_memory = m_386 | m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
const int x86_zero_extend_with_and = m_486 | m_PENT;
const int x86_movx = m_ATHLON_K8 | m_PPRO | m_PENT4 | m_NOCONA | m_GENERIC | m_GEODE /* m_386 | m_K6 */;
const int x86_movx = m_ATHLON_K8 | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */;
const int x86_double_with_add = ~m_386;
const int x86_use_bit_test = m_386;
const int x86_unroll_strlen = m_486 | m_PENT | m_PPRO | m_ATHLON_K8 | m_K6 | m_GENERIC;
const int x86_unroll_strlen = m_486 | m_PENT | m_PPRO | m_ATHLON_K8 | m_K6 | m_CORE2 | m_GENERIC;
const int x86_cmove = m_PPRO | m_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
const int x86_3dnow_a = m_ATHLON_K8;
const int x86_deep_branch = m_PPRO | m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC;
const int x86_deep_branch = m_PPRO | m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
/* Branch hints were put in P4 based on simulation result. But
after P4 was made, no performance benefit was observed with
branch hints. It also increases the code size. As the result,
@ -822,15 +875,15 @@ const int x86_use_sahf = m_PPRO | m_K6_GEODE | m_PENT4 | m_NOCONA | m_GENERIC32;
with partial reg. dependencies used by Athlon/P4 based chips, it is better
to leave it off for generic32 for now. */
const int x86_partial_reg_stall = m_PPRO;
const int x86_partial_flag_reg_stall = m_GENERIC;
const int x86_partial_flag_reg_stall = m_CORE2 | m_GENERIC;
const int x86_use_himode_fiop = m_386 | m_486 | m_K6_GEODE;
const int x86_use_simode_fiop = ~(m_PPRO | m_ATHLON_K8 | m_PENT | m_GENERIC);
const int x86_use_simode_fiop = ~(m_PPRO | m_ATHLON_K8 | m_PENT | m_CORE2 | m_GENERIC);
const int x86_use_mov0 = m_K6;
const int x86_use_cltd = ~(m_PENT | m_K6 | m_GENERIC);
const int x86_use_cltd = ~(m_PENT | m_K6 | m_CORE2 | m_GENERIC);
const int x86_read_modify_write = ~m_PENT;
const int x86_read_modify = ~(m_PENT | m_PPRO);
const int x86_split_long_moves = m_PPRO;
const int x86_promote_QImode = m_K6_GEODE | m_PENT | m_386 | m_486 | m_ATHLON_K8 | m_GENERIC; /* m_PENT4 ? */
const int x86_promote_QImode = m_K6_GEODE | m_PENT | m_386 | m_486 | m_ATHLON_K8 | m_CORE2 | m_GENERIC; /* m_PENT4 ? */
const int x86_fast_prefix = ~(m_PENT | m_486 | m_386);
const int x86_single_stringop = m_386 | m_PENT4 | m_NOCONA;
const int x86_qimode_math = ~(0);
@ -840,18 +893,18 @@ const int x86_promote_qi_regs = 0;
if our scheme for avoiding partial stalls was more effective. */
const int x86_himode_math = ~(m_PPRO);
const int x86_promote_hi_regs = m_PPRO;
const int x86_sub_esp_4 = m_ATHLON_K8 | m_PPRO | m_PENT4 | m_NOCONA | m_GENERIC;
const int x86_sub_esp_8 = m_ATHLON_K8 | m_PPRO | m_386 | m_486 | m_PENT4 | m_NOCONA | m_GENERIC;
const int x86_add_esp_4 = m_ATHLON_K8 | m_K6_GEODE | m_PENT4 | m_NOCONA | m_GENERIC;
const int x86_add_esp_8 = m_ATHLON_K8 | m_PPRO | m_K6_GEODE | m_386 | m_486 | m_PENT4 | m_NOCONA | m_GENERIC;
const int x86_integer_DFmode_moves = ~(m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_GENERIC | m_GEODE);
const int x86_partial_reg_dependency = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC;
const int x86_memory_mismatch_stall = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC;
const int x86_accumulate_outgoing_args = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_GENERIC;
const int x86_prologue_using_move = m_ATHLON_K8 | m_PPRO | m_GENERIC;
const int x86_epilogue_using_move = m_ATHLON_K8 | m_PPRO | m_GENERIC;
const int x86_sub_esp_4 = m_ATHLON_K8 | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
const int x86_sub_esp_8 = m_ATHLON_K8 | m_PPRO | m_386 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
const int x86_add_esp_4 = m_ATHLON_K8 | m_K6_GEODE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
const int x86_add_esp_8 = m_ATHLON_K8 | m_PPRO | m_K6_GEODE | m_386 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
const int x86_integer_DFmode_moves = ~(m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC | m_GEODE);
const int x86_partial_reg_dependency = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
const int x86_memory_mismatch_stall = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
const int x86_accumulate_outgoing_args = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
const int x86_prologue_using_move = m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC;
const int x86_epilogue_using_move = m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC;
const int x86_shift1 = ~m_486;
const int x86_arch_always_fancy_math_387 = m_PENT | m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC;
const int x86_arch_always_fancy_math_387 = m_PENT | m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
/* In Generic model we have an conflict here in between PPro/Pentium4 based chips
that thread 128bit SSE registers as single units versus K8 based chips that
divide SSE registers to two 64bit halves.
@ -861,7 +914,7 @@ const int x86_arch_always_fancy_math_387 = m_PENT | m_PPRO | m_ATHLON_K8 | m_PEN
this option on P4 brings over 20% SPECfp regression, while enabling it on
K8 brings roughly 2.4% regression that can be partly masked by careful scheduling
of moves. */
const int x86_sse_partial_reg_dependency = m_PENT4 | m_NOCONA | m_PPRO | m_GENERIC;
const int x86_sse_partial_reg_dependency = m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
/* Set for machines where the type and dependencies are resolved on SSE
register parts instead of whole registers, so we may maintain just
lower part of scalar values in proper format leaving the upper part
@ -870,8 +923,8 @@ const int x86_sse_split_regs = m_ATHLON_K8;
const int x86_sse_typeless_stores = m_ATHLON_K8;
const int x86_sse_load0_by_pxor = m_PPRO | m_PENT4 | m_NOCONA;
const int x86_use_ffreep = m_ATHLON_K8;
const int x86_rep_movl_optimal = m_386 | m_PENT | m_PPRO | m_K6_GEODE;
const int x86_use_incdec = ~(m_PENT4 | m_NOCONA | m_GENERIC);
const int x86_rep_movl_optimal = m_386 | m_PENT | m_PPRO | m_K6_GEODE | m_CORE2;
const int x86_use_incdec = ~(m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC);
/* ??? Allowing interunit moves makes it all too easy for the compiler to put
integer data in xmm registers. Which results in pretty abysmal code. */
@ -880,8 +933,8 @@ const int x86_inter_unit_moves = 0 /* ~(m_ATHLON_K8) */;
const int x86_ext_80387_constants = m_K6_GEODE | m_ATHLON | m_PENT4 | m_NOCONA | m_PPRO | m_GENERIC32;
/* Some CPU cores are not able to predict more than 4 branch instructions in
the 16 byte window. */
const int x86_four_jump_limit = m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC;
const int x86_schedule = m_PPRO | m_ATHLON_K8 | m_K6_GEODE | m_PENT | m_GENERIC;
const int x86_four_jump_limit = m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
const int x86_schedule = m_PPRO | m_ATHLON_K8 | m_K6_GEODE | m_PENT | m_CORE2 | m_GENERIC;
const int x86_use_bt = m_ATHLON_K8;
/* Compare and exchange was added for 80486. */
const int x86_cmpxchg = ~m_386;
@ -893,7 +946,7 @@ const int x86_cmpxchg16b = m_NOCONA;
const int x86_xadd = ~m_386;
/* Byteswap was added for 80486. */
const int x86_bswap = ~m_386;
const int x86_pad_returns = m_ATHLON_K8 | m_GENERIC;
const int x86_pad_returns = m_ATHLON_K8 | m_CORE2 | m_GENERIC;
/* In case the average insn count for single function invocation is
lower than this constant, emit fast (but longer) prologue and
@ -1523,6 +1576,7 @@ override_options (void)
{&pentium4_cost, 0, 0, 0, 0, 0, 0, 0},
{&k8_cost, 0, 0, 16, 7, 16, 7, 16},
{&nocona_cost, 0, 0, 0, 0, 0, 0, 0},
{&core2_cost, 0, 0, 16, 7, 16, 7, 16},
{&generic32_cost, 0, 0, 16, 7, 16, 7, 16},
{&generic64_cost, 0, 0, 16, 7, 16, 7, 16}
};
@ -1570,6 +1624,9 @@ override_options (void)
| PTA_MMX | PTA_PREFETCH_SSE},
{"nocona", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_64BIT
| PTA_MMX | PTA_PREFETCH_SSE},
{"core2", PROCESSOR_CORE2, PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_64BIT | PTA_MMX
| PTA_PREFETCH_SSE},
{"geode", PROCESSOR_GEODE, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
| PTA_3DNOW_A},
{"k6", PROCESSOR_K6, PTA_MMX},
@ -13857,6 +13914,9 @@ ix86_issue_rate (void)
case PROCESSOR_GENERIC64:
return 3;
case PROCESSOR_CORE2:
return 4;
default:
return 1;
}

14
gcc/config/i386/i386.h
View File

@ -137,6 +137,7 @@ extern const struct processor_costs *ix86_cost;
#define TARGET_K8 (ix86_tune == PROCESSOR_K8)
#define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
#define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
#define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2)
#define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32)
#define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)
#define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
@ -403,6 +404,8 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
builtin_define ("__tune_pentium4__"); \
else if (TARGET_NOCONA) \
builtin_define ("__tune_nocona__"); \
else if (TARGET_CORE2) \
builtin_define ("__tune_core2__"); \
\
if (TARGET_MMX) \
builtin_define ("__MMX__"); \
@ -483,6 +486,11 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
builtin_define ("__nocona"); \
builtin_define ("__nocona__"); \
} \
else if (ix86_arch == PROCESSOR_CORE2) \
{ \
builtin_define ("__core2"); \
builtin_define ("__core2__"); \
} \
} \
while (0)
@ -504,14 +512,15 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
#define TARGET_CPU_DEFAULT_pentium_m 15
#define TARGET_CPU_DEFAULT_prescott 16
#define TARGET_CPU_DEFAULT_nocona 17
#define TARGET_CPU_DEFAULT_generic 18
#define TARGET_CPU_DEFAULT_core2 18
#define TARGET_CPU_DEFAULT_generic 19
#define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
"pentiumpro", "pentium2", "pentium3", \
"pentium4", "geode", "k6", "k6-2", "k6-3", \
"athlon", "athlon-4", "k8", \
"pentium-m", "prescott", "nocona", \
"generic"}
"core2", "generic"}
#ifndef CC1_SPEC
#define CC1_SPEC "%(cc1_cpu) "
@ -2073,6 +2082,7 @@ enum processor_type
PROCESSOR_PENTIUM4,
PROCESSOR_K8,
PROCESSOR_NOCONA,
PROCESSOR_CORE2,
PROCESSOR_GENERIC32,
PROCESSOR_GENERIC64,
PROCESSOR_max

2
gcc/config/i386/i386.md
View File

@ -194,7 +194,7 @@
;; Processor type. This attribute must exactly match the processor_type
;; enumeration in i386.h.
(define_attr "cpu" "i386,i486,pentium,pentiumpro,geode,k6,athlon,pentium4,k8,nocona,generic32,generic64"
(define_attr "cpu" "i386,i486,pentium,pentiumpro,geode,k6,athlon,pentium4,k8,nocona,core2,generic32,generic64"
(const (symbol_ref "ix86_tune")))
;; A basic instruction type. Refinements due to arguments to be

3
gcc/doc/invoke.texi
View File

@ -9296,6 +9296,9 @@ set support.
@item nocona
Improved version of Intel Pentium4 CPU with 64-bit extensions, MMX, SSE,
SSE2 and SSE3 instruction set support.
@item core2
Intel Core2 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3
instruction set support.
@item k6
AMD K6 CPU with MMX instruction set support.
@item k6-2, k6-3