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rs6000: Support [u]mod<mode>3 for vector modulo insns

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This patch is to make Power10 newly introduced vector
modulo instructions exploited in vectorized loops, it
just simply renames existing define_insns as standard
pattern names.

gcc/ChangeLog:

	* config/rs6000/vsx.md (mods_<mode>): Rename to...
	(mod<mode>3): ... this.
	(modu_<mode>): Rename to...
	(umod<mode>3): ... this.
	* config/rs6000/rs6000-builtin.def (MODS_V2DI, MODS_V4SI, MODU_V2DI,
	MODU_V4SI): Adjust.

gcc/testsuite/ChangeLog:

	* gcc.target/powerpc/mod-vectorize.c: New test.
This commit is contained in:
Kewen Lin 2021-07-08 22:00:24 -05:00
parent df85baa568
commit 062c762ef2
3 changed files with 52 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
gcc/config/rs6000/rs6000-builtin.def
View File

@ -3031,10 +3031,10 @@ BU_P10V_AV_2 (DIVS_V4SI, "vdivsw", CONST, divv4si3)
BU_P10V_AV_2 (DIVS_V2DI, "vdivsd", CONST, divv2di3)
BU_P10V_AV_2 (DIVU_V4SI, "vdivuw", CONST, udivv4si3)
BU_P10V_AV_2 (DIVU_V2DI, "vdivud", CONST, udivv2di3)
BU_P10V_AV_2 (MODS_V2DI, "vmodsd", CONST, mods_v2di)
BU_P10V_AV_2 (MODS_V4SI, "vmodsw", CONST, mods_v4si)
BU_P10V_AV_2 (MODU_V2DI, "vmodud", CONST, modu_v2di)
BU_P10V_AV_2 (MODU_V4SI, "vmoduw", CONST, modu_v4si)
BU_P10V_AV_2 (MODS_V2DI, "vmodsd", CONST, modv2di3)
BU_P10V_AV_2 (MODS_V4SI, "vmodsw", CONST, modv4si3)
BU_P10V_AV_2 (MODU_V2DI, "vmodud", CONST, umodv2di3)
BU_P10V_AV_2 (MODU_V4SI, "vmoduw", CONST, umodv4si3)
BU_P10V_AV_2 (MULHS_V2DI, "vmulhsd", CONST, mulhs_v2di)
BU_P10V_AV_2 (MULHS_V4SI, "vmulhsw", CONST, mulhs_v4si)
BU_P10V_AV_2 (MULHU_V2DI, "vmulhud", CONST, mulhu_v2di)

4
gcc/config/rs6000/vsx.md
View File

@ -6333,7 +6333,7 @@
[(set_attr "type" "vecdiv")
(set_attr "size" "<bits>")])
(define_insn "mods_<mode>"
(define_insn "mod<mode>3"
[(set (match_operand:VIlong 0 "vsx_register_operand" "=v")
(mod:VIlong (match_operand:VIlong 1 "vsx_register_operand" "v")
(match_operand:VIlong 2 "vsx_register_operand" "v")))]
@ -6342,7 +6342,7 @@
[(set_attr "type" "vecdiv")
(set_attr "size" "<bits>")])
(define_insn "modu_<mode>"
(define_insn "umod<mode>3"
[(set (match_operand:VIlong 0 "vsx_register_operand" "=v")
(umod:VIlong (match_operand:VIlong 1 "vsx_register_operand" "v")
(match_operand:VIlong 2 "vsx_register_operand" "v")))]

46
gcc/testsuite/gcc.target/powerpc/mod-vectorize.c Normal file
View File

@ -0,0 +1,46 @@
/* { dg-require-effective-target power10_ok } */
/* { dg-options "-mdejagnu-cpu=power10 -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fdump-tree-vect-details" } */
/* Test vectorizer can exploit ISA 3.1 instructions Vector Modulo
Signed/Unsigned Word/Doubleword for word/doubleword modulo operations. */
#define N 128
extern signed int si_a[N], si_b[N], si_c[N];
extern unsigned int ui_a[N], ui_b[N], ui_c[N];
extern signed long long sd_a[N], sd_b[N], sd_c[N];
extern unsigned long long ud_a[N], ud_b[N], ud_c[N];
__attribute__ ((noipa)) void
test_si ()
{
for (int i = 0; i < N; i++)
si_c[i] = si_a[i] % si_b[i];
}
__attribute__ ((noipa)) void
test_ui ()
{
for (int i = 0; i < N; i++)
ui_c[i] = ui_a[i] % ui_b[i];
}
__attribute__ ((noipa)) void
test_sd ()
{
for (int i = 0; i < N; i++)
sd_c[i] = sd_a[i] % sd_b[i];
}
__attribute__ ((noipa)) void
test_ud ()
{
for (int i = 0; i < N; i++)
ud_c[i] = ud_a[i] % ud_b[i];
}
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 4 "vect" } } */
/* { dg-final { scan-assembler-times {\mvmodsw\M} 1 } } */
/* { dg-final { scan-assembler-times {\mvmoduw\M} 1 } } */
/* { dg-final { scan-assembler-times {\mvmodsd\M} 1 } } */
/* { dg-final { scan-assembler-times {\mvmodud\M} 1 } } */