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tilegx.md (floatsisf2): New pattern. 

2013-03-25  Walter Lee  <walt@tilera.com>

	* config/tilegx/tilegx.md (floatsisf2): New pattern.
        (floatunssisf2): New pattern.
        (floatsidf2): New pattern.
        (floatunssidf2): New pattern.

From-SVN: r197079
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Walter Lee 2013-03-26 00:46:35 +00:00 committed by Walter Lee
parent 9b2732d64f
commit 065a36055e
2 changed files with 109 additions and 0 deletions
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7
gcc/ChangeLog
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@ -1,3 +1,10 @@
2013-03-25 Walter Lee <walt@tilera.com>
* config/tilegx/tilegx.md (floatsisf2): New pattern.
(floatunssisf2): New pattern.
(floatsidf2): New pattern.
(floatunssidf2): New pattern.
2013-03-25 Walter Lee <walt@tilera.com> 2013-03-25 Walter Lee <walt@tilera.com>
* config/tilegx/tilegx.c (expand_set_cint64_one_inst): Inline * config/tilegx/tilegx.c (expand_set_cint64_one_inst): Inline

102
gcc/config/tilegx/tilegx.md
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@ -2129,6 +2129,108 @@
"" ""
"rotl\t%0, %r1, %r2") "rotl\t%0, %r1, %r2")
;; Integer to floating point conversions
(define_expand "floatsisf2"
[(set (match_operand:SF 0 "register_operand" "")
(float:SI (match_operand:SI 1 "register_operand" "")))]
""
{
rtx result = gen_lowpart (DImode, operands[0]);
rtx a = operands[1];
rtx nega = gen_reg_rtx (SImode);
rtx exp = gen_reg_rtx (DImode);
rtx sign = gen_reg_rtx (DImode);
rtx abs = gen_reg_rtx (DImode);
rtx flags = gen_reg_rtx (DImode);
rtx tmp1 = gen_reg_rtx (DImode);
rtx tmp2 = gen_reg_rtx (DImode);
emit_move_insn (exp, GEN_INT (0x9e));
emit_insn (gen_negsi2 (nega, a));
emit_insn (gen_insn_cmplts_sisi (gen_lowpart (SImode, sign), a, const0_rtx));
emit_insn (gen_insn_cmoveqz (abs, gen_lowpart (DImode, nega), sign,
gen_lowpart (DImode, a)));
emit_insn (gen_insn_bfins (tmp1, exp, sign, GEN_INT (10), GEN_INT (10)));
emit_insn (gen_insn_bfins (tmp2, tmp1, abs, GEN_INT (32), GEN_INT (63)));
emit_insn (gen_insn_fsingle_pack1 (flags, tmp2));
emit_insn (gen_insn_fsingle_pack2 (result, tmp2, flags));
DONE;
})
(define_expand "floatunssisf2"
[(set (match_operand:SF 0 "register_operand" "")
(float:SI (match_operand:SI 1 "register_operand" "")))]
""
{
rtx result = gen_lowpart (DImode, operands[0]);
rtx a = operands[1];
rtx exp = gen_reg_rtx (DImode);
rtx flags = gen_reg_rtx (DImode);
rtx tmp = gen_reg_rtx (DImode);
emit_move_insn (exp, GEN_INT (0x9e));
emit_insn (gen_insn_bfins (tmp, exp, gen_lowpart (DImode, a),
GEN_INT (32), GEN_INT (63)));
emit_insn (gen_insn_fsingle_pack1 (flags, tmp));
emit_insn (gen_insn_fsingle_pack2 (result, tmp, flags));
DONE;
})
(define_expand "floatsidf2"
[(set (match_operand:DF 0 "register_operand" "")
(float:SI (match_operand:SI 1 "register_operand" "")))]
""
{
rtx result = gen_lowpart (DImode, operands[0]);
rtx a = gen_lowpart (DImode, operands[1]);
rtx nega = gen_reg_rtx (DImode);
rtx exp = gen_reg_rtx (DImode);
rtx sign = gen_reg_rtx (DImode);
rtx abs = gen_reg_rtx (DImode);
rtx tmp1 = gen_reg_rtx (DImode);
rtx tmp2 = gen_reg_rtx (DImode);
rtx tmp3 = gen_reg_rtx (DImode);
emit_move_insn (exp, GEN_INT (0x21b00));
emit_insn (gen_negdi2 (nega, a));
emit_insn (gen_insn_cmplts_didi (sign, a, const0_rtx));
emit_insn (gen_insn_cmovnez (abs, a, sign, nega));
emit_insn (gen_ashldi3 (tmp1, abs, GEN_INT (4)));
emit_insn (gen_insn_bfins (tmp2, exp, sign, GEN_INT (20), GEN_INT (20)));
emit_insn (gen_insn_fdouble_pack1 (tmp3, tmp1, tmp2));
emit_insn (gen_insn_fdouble_pack2 (result, tmp3, tmp1, const0_rtx));
DONE;
})
(define_expand "floatunssidf2"
[(set (match_operand:DF 0 "register_operand" "")
(float:SI (match_operand:SI 1 "register_operand" "")))]
""
{
rtx result = gen_lowpart (DImode, operands[0]);
rtx a = gen_lowpart (DImode, operands[1]);
rtx exp = gen_reg_rtx (DImode);
rtx tmp1 = gen_reg_rtx (DImode);
rtx tmp2 = gen_reg_rtx (DImode);
emit_move_insn (exp, GEN_INT (0x21b00));
emit_insn (gen_insn_bfins (tmp1, const0_rtx, a, GEN_INT (4), GEN_INT (35)));
emit_insn (gen_insn_fdouble_pack1 (tmp2, tmp1, exp));
emit_insn (gen_insn_fdouble_pack2 (result, tmp2, tmp1, const0_rtx));
DONE;
})
;; ;;
;; Multiplies ;; Multiplies