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[AARCH64]Fix TLS local exec model addressing code generation inconsistency.

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gcc/

	* config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Correct
	the comment.
	* config/aarch64/aarch64.md * (tlsle_small_<mode>): Add left shift
	12-bit for higher part.

From-SVN: r220116
This commit is contained in:
Renlin Li 2015-01-26 15:42:15 +00:00 committed by Renlin Li
parent ee5f05239f
commit 0699caae0f
3 changed files with 10 additions and 3 deletions
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7
gcc/ChangeLog
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@ -1,3 +1,10 @@
2015-01-26 Renlin Li <renlin.li@arm.com>
* config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Correct
the comment.
* config/aarch64/aarch64.md (tlsle_small_<mode>): Add left shift 12-bit
for higher part.
2015-01-26 Richard Biener <rguenther@suse.de>
PR middle-end/64764

4
gcc/config/aarch64/aarch64.c
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@ -818,8 +818,8 @@ tls_symbolic_operand_type (rtx addr)
Local Exec:
mrs tp, tpidr_el0
add t0, tp, #:tprel_hi12:imm
add t0, #:tprel_lo12_nc:imm
add t0, tp, #:tprel_hi12:imm, lsl #12
add t0, t0, #:tprel_lo12_nc:imm
*/
static void

2
gcc/config/aarch64/aarch64.md
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@ -4224,7 +4224,7 @@
(match_operand 2 "aarch64_tls_le_symref" "S")]
UNSPEC_GOTSMALLTLS))]
""
"add\\t%<w>0, %<w>1, #%G2\;add\\t%<w>0, %<w>0, #%L2"
"add\\t%<w>0, %<w>1, #%G2, lsl #12\;add\\t%<w>0, %<w>0, #%L2"
[(set_attr "type" "alu_sreg")
(set_attr "length" "8")]
)