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mips-modes.def (V2SF, CCV2, CCV4): New modes.

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2004-08-29  Chao-ying Fu  <fu@mips.com>
	    James E Wilson  <wilson@specifixinc.com>

	* config/mips/mips-modes.def (V2SF, CCV2, CCV4): New modes. Give CCV2
	8 byte size and alignment.  Give CCV4 16 byte size and alignment.
	* config/mips/mips-ps-3d.md: New file.
	* config/mips/mips.c (TARGET_VECTOR_MODE_SUPPORTED_P,
	TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): Define.
	(mips_const_insns): Handle CONST_VECTOR the same as CONST_DOUBLE.
	(mips_output_move): Emit "mov.ps" for V2SFmode.
	(mips_arg_info): Add checks for VECTOR_FLOAT_TYPE_P and
	MODE_VECTOR_FLOAT.
	(override_options): Check if TARGET_MIPS3D and there was an explicit
	!TARGET_PAIRED_SINGLE_FLOAT.  Set MASK_PAIRED_SINGLE, if TARGET_MIPS3D.
	Check if TARGET_FLOAT64 and TARGET_HARD_FLOAT are both true, when
	TARGET_PAIRED_SINGLE_FLOAT is true.  Check if the ISA supports
	TARGET_PAIRED_SINGLE_FLOAT.  Allow MODE_VECTOR_FLOAT in fp registers,
	and allow CCV2 and CCV4 to occupy two and four CC registers.
	(print_fcc_operand): New function.
	(print_operand): Add %Y, %y, %V, %v, %Q for CCV2, CCV4, CC.  Modify
	%Z to call print_fcc_operand.
	(mips_function_value): Handle MODE_VECTOR_FLOAT.
	(mips_class_max_nregs): Check for ST_REGS, and handle CCmodes.
	(mips_vector_mode_supported_p): New function.
	(mips_hard_regno_nregs): Check for ST_REG_P, and handle CCmodes.
	(builtin_description): New struct.
	(mips_bdesc): New array of struct builtin_description.
	(mips_expand_builtin, mips_init_builtins,
	mips_expand_ps_cond_move_builtin, mips_expand_4s_compare_builtin,
	mips_expand_compare_builtin, mips_expand_ps_compare_builtin): New
	functions.
	* config/mips/mips.h (MASK_PAIRED_SINGLE, MASK_MIPS3D): New defines.
	(TARGET_PAIRED_SINGLE_FLOAT, TARGET_MIPS3D): New defines.
	(TARGET_CPU_CPP_BUILTINS): Add __mips_paired_single_float.
	(TARGET_SWITCHES): Added "-mpaired-single", "-mno-paired-single",
	"-mips3d", and "-mno-mips3d".
	(ASM_SPEC): Map -mips3d to -mips3d in gas.
	(EXTRA_CONSTRAINT_Y): New macro.
	(EXTRA_CONSTRAINT_STR): Renamed from EXTRA_CONSTRAINT.  Add new
	multi-letter constraint 'Y'.
	(CONSTRAINT_LEN): New macro.
	(enum mips_builtins): New for MIPS builtin functions.
	(enum mips_function_type): New for the types of MIPS builtin functions.
	(enum mips_cmp_choice): New for the MIPS comparison builtin functions.
	* config/mips/mips.md: New constants for paired single and MIPS-3D
	instructions.  Include the new mips-ps-3d.md file.
	(addv2sf3, subv2sf3, mulv2sf3, absv2sf2, negv2sf2, movv2sf,
	movv2sf_hardfloat_64bit): New named patterns.
	(madd.ps, msub.ps, nmaddv2sf, nmaddv2sf_fastmath, nmsubv2sf,
	nmsubv2sf_fastmath, ldxc1_v2sf_si, ldxc1_v2sf_di, sdxc1_v2sf_si,
	sdxc1_v2sf_di): New unnamed patterns.
	* config/mips/predicates.md (const_0_operand, const_1_operand): Add
	const_vector support.
	(const_0_or_1_operand): New predicate.
	* doc/invoke.texi (MIPS Options): Add -mpaired-single and -mips3d.

Co-Authored-By: James E Wilson <wilson@specifixinc.com>

From-SVN: r86713
This commit is contained in:
Chao-ying Fu 2004-08-29 09:19:34 +00:00 committed by Richard Sandiford
parent b8d65dace7
commit 06a4ab7022
8 changed files with 4360 additions and 31 deletions
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56
gcc/ChangeLog
View File

@ -1,3 +1,59 @@
2004-08-29 Chao-ying Fu <fu@mips.com>
James E Wilson <wilson@specifixinc.com>
* config/mips/mips-modes.def (V2SF, CCV2, CCV4): New modes. Give CCV2
8 byte size and alignment. Give CCV4 16 byte size and alignment.
* config/mips/mips-ps-3d.md: New file.
* config/mips/mips.c (TARGET_VECTOR_MODE_SUPPORTED_P,
TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): Define.
(mips_const_insns): Handle CONST_VECTOR the same as CONST_DOUBLE.
(mips_output_move): Emit "mov.ps" for V2SFmode.
(mips_arg_info): Add checks for VECTOR_FLOAT_TYPE_P and
MODE_VECTOR_FLOAT.
(override_options): Check if TARGET_MIPS3D and there was an explicit
!TARGET_PAIRED_SINGLE_FLOAT. Set MASK_PAIRED_SINGLE, if TARGET_MIPS3D.
Check if TARGET_FLOAT64 and TARGET_HARD_FLOAT are both true, when
TARGET_PAIRED_SINGLE_FLOAT is true. Check if the ISA supports
TARGET_PAIRED_SINGLE_FLOAT. Allow MODE_VECTOR_FLOAT in fp registers,
and allow CCV2 and CCV4 to occupy two and four CC registers.
(print_fcc_operand): New function.
(print_operand): Add %Y, %y, %V, %v, %Q for CCV2, CCV4, CC. Modify
%Z to call print_fcc_operand.
(mips_function_value): Handle MODE_VECTOR_FLOAT.
(mips_class_max_nregs): Check for ST_REGS, and handle CCmodes.
(mips_vector_mode_supported_p): New function.
(mips_hard_regno_nregs): Check for ST_REG_P, and handle CCmodes.
(builtin_description): New struct.
(mips_bdesc): New array of struct builtin_description.
(mips_expand_builtin, mips_init_builtins,
mips_expand_ps_cond_move_builtin, mips_expand_4s_compare_builtin,
mips_expand_compare_builtin, mips_expand_ps_compare_builtin): New
functions.
* config/mips/mips.h (MASK_PAIRED_SINGLE, MASK_MIPS3D): New defines.
(TARGET_PAIRED_SINGLE_FLOAT, TARGET_MIPS3D): New defines.
(TARGET_CPU_CPP_BUILTINS): Add __mips_paired_single_float.
(TARGET_SWITCHES): Added "-mpaired-single", "-mno-paired-single",
"-mips3d", and "-mno-mips3d".
(ASM_SPEC): Map -mips3d to -mips3d in gas.
(EXTRA_CONSTRAINT_Y): New macro.
(EXTRA_CONSTRAINT_STR): Renamed from EXTRA_CONSTRAINT. Add new
multi-letter constraint 'Y'.
(CONSTRAINT_LEN): New macro.
(enum mips_builtins): New for MIPS builtin functions.
(enum mips_function_type): New for the types of MIPS builtin functions.
(enum mips_cmp_choice): New for the MIPS comparison builtin functions.
* config/mips/mips.md: New constants for paired single and MIPS-3D
instructions. Include the new mips-ps-3d.md file.
(addv2sf3, subv2sf3, mulv2sf3, absv2sf2, negv2sf2, movv2sf,
movv2sf_hardfloat_64bit): New named patterns.
(madd.ps, msub.ps, nmaddv2sf, nmaddv2sf_fastmath, nmsubv2sf,
nmsubv2sf_fastmath, ldxc1_v2sf_si, ldxc1_v2sf_di, sdxc1_v2sf_si,
sdxc1_v2sf_di): New unnamed patterns.
* config/mips/predicates.md (const_0_operand, const_1_operand): Add
const_vector support.
(const_0_or_1_operand): New predicate.
* doc/invoke.texi (MIPS Options): Add -mpaired-single and -mips3d.
2004-08-29 Diego Novillo <dnovillo@redhat.com>
* Makefile.in (OBJS-common): Add tree-ssa-propagate.o

12
gcc/config/mips/mips-modes.def
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@ -25,3 +25,15 @@ RESET_FLOAT_FORMAT (DF, mips_double_format);
/* Irix6 will override this via MIPS_TFMODE_FORMAT. */
FLOAT_MODE (TF, 16, mips_quad_format);
/* Vector modes. */
VECTOR_MODES (FLOAT, 8); /* V4HF V2SF */
/* Paired single comparison instructions use 2 or 4 CC. */
CC_MODE (CCV2);
ADJUST_BYTESIZE (CCV2, 8);
ADJUST_ALIGNMENT (CCV2, 8);
CC_MODE (CCV4);
ADJUST_BYTESIZE (CCV4, 16);
ADJUST_ALIGNMENT (CCV4, 16);

1607
gcc/config/mips/mips-ps-3d.md Normal file
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2046
gcc/config/mips/mips.c
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409
gcc/config/mips/mips.h
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@ -161,6 +161,9 @@ extern const struct mips_cpu_info *mips_tune_info;
#define MASK_VR4130_ALIGN 0x02000000 /* Perform VR4130 alignment opts. */
#define MASK_FP_EXCEPTIONS 0x04000000 /* FP exceptions are enabled. */
#define MASK_PAIRED_SINGLE 0x10000000 /* Support paired-single FPU. */
#define MASK_MIPS3D 0x20000000 /* Support MIPS-3D instructions. */
/* Debug switches, not documented */
#define MASK_DEBUG 0 /* unused */
#define MASK_DEBUG_D 0 /* don't do define_split's */
@ -234,6 +237,10 @@ extern const struct mips_cpu_info *mips_tune_info;
#define TARGET_FP_EXCEPTIONS ((target_flags & MASK_FP_EXCEPTIONS) != 0)
#define TARGET_PAIRED_SINGLE_FLOAT \
((target_flags & MASK_PAIRED_SINGLE) != 0)
#define TARGET_MIPS3D ((target_flags & MASK_MIPS3D) != 0)
/* True if we should use NewABI-style relocation operators for
symbolic addresses. This is never true for mips16 code,
which has its own conventions. */
@ -452,7 +459,10 @@ extern const struct mips_cpu_info *mips_tune_info;
builtin_define ("__mips_soft_float"); \
\
if (TARGET_SINGLE_FLOAT) \
builtin_define ("__mips_single_float"); \
builtin_define ("__mips_single_float"); \
\
if (TARGET_PAIRED_SINGLE_FLOAT) \
builtin_define ("__mips_paired_single_float"); \
\
if (TARGET_BIG_ENDIAN) \
{ \
@ -575,6 +585,14 @@ extern const struct mips_cpu_info *mips_tune_info;
N_("Use single (32-bit) FP only")}, \
{"double-float", -MASK_SINGLE_FLOAT, \
N_("Don't use single (32-bit) FP only")}, \
{"paired-single", MASK_PAIRED_SINGLE, \
N_("Use paired-single floating point instructions")}, \
{"no-paired-single", -MASK_PAIRED_SINGLE, \
N_("Use paired-single floating point instructions")}, \
{"ips3d", MASK_MIPS3D, \
N_("Use MIPS-3D instructions")}, \
{"no-mips3d", -MASK_MIPS3D, \
N_("Use MIPS-3D instructions")}, \
{"mad", MASK_MAD, \
N_("Use multiply accumulate")}, \
{"no-mad", -MASK_MAD, \
@ -1048,6 +1066,7 @@ extern const struct mips_cpu_info *mips_tune_info;
%{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
%{mips32} %{mips32r2} %{mips64} \
%{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
%{mips3d:-mips3d} \
%{mfix-vr4120} \
%(subtarget_asm_optimizing_spec) \
%(subtarget_asm_debugging_spec) \
@ -1950,9 +1969,16 @@ extern enum reg_class mips_char_to_class[256];
`W' is for memory references that are based on a member of BASE_REG_CLASS.
This is true for all non-mips16 references (although it can sometimes
be indirect if !TARGET_EXPLICIT_RELOCS). For mips16, it excludes
stack and constant-pool references. */
stack and constant-pool references.
`YG' is for 0 valued vector constants. */
#define EXTRA_CONSTRAINT(OP,CODE) \
#define EXTRA_CONSTRAINT_Y(OP,STR) \
(((STR)[1] == 'G') ? (GET_CODE (OP) == CONST_VECTOR \
&& (OP) == CONST0_RTX (GET_MODE (OP))) \
: FALSE)
#define EXTRA_CONSTRAINT_STR(OP,CODE,STR) \
(((CODE) == 'Q') ? const_arith_operand (OP, VOIDmode) \
: ((CODE) == 'R') ? (GET_CODE (OP) == MEM \
&& mips_fetch_insns (OP) == 1) \
@ -1969,8 +1995,15 @@ extern enum reg_class mips_char_to_class[256];
&& (!TARGET_MIPS16 \
|| (!stack_operand (OP, VOIDmode) \
&& !CONSTANT_P (XEXP (OP, 0))))) \
: ((CODE) == 'Y') ? EXTRA_CONSTRAINT_Y (OP, STR) \
: FALSE)
/* Y is the only multi-letter constraint, and has length 2. */
#define CONSTRAINT_LEN(C,STR) \
(((C) == 'Y') ? 2 \
: DEFAULT_CONSTRAINT_LEN (C, STR))
/* Say which of the above are memory constraints. */
#define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'R' || (C) == 'W')
@ -2987,3 +3020,373 @@ while (0)
" TEXT_SECTION_ASM_OP);
#endif
#endif
/* MIPS Paired-Single Floating Point Instruction & MIPS-3D Support. */
/* Builtin functions for MIPS. */
/* NOTE: The order of mips_bdesc[] in mips.c must be the same as the order of
enum mips_builtins{}. */
enum mips_builtins
{
MIPS_BUILTIN_PLL_PS,
MIPS_BUILTIN_PUL_PS,
MIPS_BUILTIN_PLU_PS,
MIPS_BUILTIN_PUU_PS,
MIPS_BUILTIN_CVT_PS_S,
MIPS_BUILTIN_CVT_S_PL,
MIPS_BUILTIN_CVT_S_PU,
MIPS_BUILTIN_ABS_PS,
MIPS_BUILTIN_ALNV_PS,
MIPS_BUILTIN_ADDR_PS,
MIPS_BUILTIN_MULR_PS,
MIPS_BUILTIN_CVT_PW_PS,
MIPS_BUILTIN_CVT_PS_PW,
MIPS_BUILTIN_RECIP1_S,
MIPS_BUILTIN_RECIP1_D,
MIPS_BUILTIN_RECIP1_PS,
MIPS_BUILTIN_RECIP2_S,
MIPS_BUILTIN_RECIP2_D,
MIPS_BUILTIN_RECIP2_PS,
MIPS_BUILTIN_RSQRT1_S,
MIPS_BUILTIN_RSQRT1_D,
MIPS_BUILTIN_RSQRT1_PS,
MIPS_BUILTIN_RSQRT2_S,
MIPS_BUILTIN_RSQRT2_D,
MIPS_BUILTIN_RSQRT2_PS,
MIPS_BUILTIN_ANY_C_F_PS,
MIPS_BUILTIN_UPPER_C_F_PS,
MIPS_BUILTIN_LOWER_C_F_PS,
MIPS_BUILTIN_ALL_C_F_PS,
MIPS_BUILTIN_ANY_C_UN_PS,
MIPS_BUILTIN_UPPER_C_UN_PS,
MIPS_BUILTIN_LOWER_C_UN_PS,
MIPS_BUILTIN_ALL_C_UN_PS,
MIPS_BUILTIN_ANY_C_EQ_PS,
MIPS_BUILTIN_UPPER_C_EQ_PS,
MIPS_BUILTIN_LOWER_C_EQ_PS,
MIPS_BUILTIN_ALL_C_EQ_PS,
MIPS_BUILTIN_ANY_C_UEQ_PS,
MIPS_BUILTIN_UPPER_C_UEQ_PS,
MIPS_BUILTIN_LOWER_C_UEQ_PS,
MIPS_BUILTIN_ALL_C_UEQ_PS,
MIPS_BUILTIN_ANY_C_OLT_PS,
MIPS_BUILTIN_UPPER_C_OLT_PS,
MIPS_BUILTIN_LOWER_C_OLT_PS,
MIPS_BUILTIN_ALL_C_OLT_PS,
MIPS_BUILTIN_ANY_C_ULT_PS,
MIPS_BUILTIN_UPPER_C_ULT_PS,
MIPS_BUILTIN_LOWER_C_ULT_PS,
MIPS_BUILTIN_ALL_C_ULT_PS,
MIPS_BUILTIN_ANY_C_OLE_PS,
MIPS_BUILTIN_UPPER_C_OLE_PS,
MIPS_BUILTIN_LOWER_C_OLE_PS,
MIPS_BUILTIN_ALL_C_OLE_PS,
MIPS_BUILTIN_ANY_C_ULE_PS,
MIPS_BUILTIN_UPPER_C_ULE_PS,
MIPS_BUILTIN_LOWER_C_ULE_PS,
MIPS_BUILTIN_ALL_C_ULE_PS,
MIPS_BUILTIN_ANY_C_SF_PS,
MIPS_BUILTIN_UPPER_C_SF_PS,
MIPS_BUILTIN_LOWER_C_SF_PS,
MIPS_BUILTIN_ALL_C_SF_PS,
MIPS_BUILTIN_ANY_C_NGLE_PS,
MIPS_BUILTIN_UPPER_C_NGLE_PS,
MIPS_BUILTIN_LOWER_C_NGLE_PS,
MIPS_BUILTIN_ALL_C_NGLE_PS,
MIPS_BUILTIN_ANY_C_SEQ_PS,
MIPS_BUILTIN_UPPER_C_SEQ_PS,
MIPS_BUILTIN_LOWER_C_SEQ_PS,
MIPS_BUILTIN_ALL_C_SEQ_PS,
MIPS_BUILTIN_ANY_C_NGL_PS,
MIPS_BUILTIN_UPPER_C_NGL_PS,
MIPS_BUILTIN_LOWER_C_NGL_PS,
MIPS_BUILTIN_ALL_C_NGL_PS,
MIPS_BUILTIN_ANY_C_LT_PS,
MIPS_BUILTIN_UPPER_C_LT_PS,
MIPS_BUILTIN_LOWER_C_LT_PS,
MIPS_BUILTIN_ALL_C_LT_PS,
MIPS_BUILTIN_ANY_C_NGE_PS,
MIPS_BUILTIN_UPPER_C_NGE_PS,
MIPS_BUILTIN_LOWER_C_NGE_PS,
MIPS_BUILTIN_ALL_C_NGE_PS,
MIPS_BUILTIN_ANY_C_LE_PS,
MIPS_BUILTIN_UPPER_C_LE_PS,
MIPS_BUILTIN_LOWER_C_LE_PS,
MIPS_BUILTIN_ALL_C_LE_PS,
MIPS_BUILTIN_ANY_C_NGT_PS,
MIPS_BUILTIN_UPPER_C_NGT_PS,
MIPS_BUILTIN_LOWER_C_NGT_PS,
MIPS_BUILTIN_ALL_C_NGT_PS,
MIPS_BUILTIN_ANY_CABS_F_PS,
MIPS_BUILTIN_UPPER_CABS_F_PS,
MIPS_BUILTIN_LOWER_CABS_F_PS,
MIPS_BUILTIN_ALL_CABS_F_PS,
MIPS_BUILTIN_ANY_CABS_UN_PS,
MIPS_BUILTIN_UPPER_CABS_UN_PS,
MIPS_BUILTIN_LOWER_CABS_UN_PS,
MIPS_BUILTIN_ALL_CABS_UN_PS,
MIPS_BUILTIN_ANY_CABS_EQ_PS,
MIPS_BUILTIN_UPPER_CABS_EQ_PS,
MIPS_BUILTIN_LOWER_CABS_EQ_PS,
MIPS_BUILTIN_ALL_CABS_EQ_PS,
MIPS_BUILTIN_ANY_CABS_UEQ_PS,
MIPS_BUILTIN_UPPER_CABS_UEQ_PS,
MIPS_BUILTIN_LOWER_CABS_UEQ_PS,
MIPS_BUILTIN_ALL_CABS_UEQ_PS,
MIPS_BUILTIN_ANY_CABS_OLT_PS,
MIPS_BUILTIN_UPPER_CABS_OLT_PS,
MIPS_BUILTIN_LOWER_CABS_OLT_PS,
MIPS_BUILTIN_ALL_CABS_OLT_PS,
MIPS_BUILTIN_ANY_CABS_ULT_PS,
MIPS_BUILTIN_UPPER_CABS_ULT_PS,
MIPS_BUILTIN_LOWER_CABS_ULT_PS,
MIPS_BUILTIN_ALL_CABS_ULT_PS,
MIPS_BUILTIN_ANY_CABS_OLE_PS,
MIPS_BUILTIN_UPPER_CABS_OLE_PS,
MIPS_BUILTIN_LOWER_CABS_OLE_PS,
MIPS_BUILTIN_ALL_CABS_OLE_PS,
MIPS_BUILTIN_ANY_CABS_ULE_PS,
MIPS_BUILTIN_UPPER_CABS_ULE_PS,
MIPS_BUILTIN_LOWER_CABS_ULE_PS,
MIPS_BUILTIN_ALL_CABS_ULE_PS,
MIPS_BUILTIN_ANY_CABS_SF_PS,
MIPS_BUILTIN_UPPER_CABS_SF_PS,
MIPS_BUILTIN_LOWER_CABS_SF_PS,
MIPS_BUILTIN_ALL_CABS_SF_PS,
MIPS_BUILTIN_ANY_CABS_NGLE_PS,
MIPS_BUILTIN_UPPER_CABS_NGLE_PS,
MIPS_BUILTIN_LOWER_CABS_NGLE_PS,
MIPS_BUILTIN_ALL_CABS_NGLE_PS,
MIPS_BUILTIN_ANY_CABS_SEQ_PS,
MIPS_BUILTIN_UPPER_CABS_SEQ_PS,
MIPS_BUILTIN_LOWER_CABS_SEQ_PS,
MIPS_BUILTIN_ALL_CABS_SEQ_PS,
MIPS_BUILTIN_ANY_CABS_NGL_PS,
MIPS_BUILTIN_UPPER_CABS_NGL_PS,
MIPS_BUILTIN_LOWER_CABS_NGL_PS,
MIPS_BUILTIN_ALL_CABS_NGL_PS,
MIPS_BUILTIN_ANY_CABS_LT_PS,
MIPS_BUILTIN_UPPER_CABS_LT_PS,
MIPS_BUILTIN_LOWER_CABS_LT_PS,
MIPS_BUILTIN_ALL_CABS_LT_PS,
MIPS_BUILTIN_ANY_CABS_NGE_PS,
MIPS_BUILTIN_UPPER_CABS_NGE_PS,
MIPS_BUILTIN_LOWER_CABS_NGE_PS,
MIPS_BUILTIN_ALL_CABS_NGE_PS,
MIPS_BUILTIN_ANY_CABS_LE_PS,
MIPS_BUILTIN_UPPER_CABS_LE_PS,
MIPS_BUILTIN_LOWER_CABS_LE_PS,
MIPS_BUILTIN_ALL_CABS_LE_PS,
MIPS_BUILTIN_ANY_CABS_NGT_PS,
MIPS_BUILTIN_UPPER_CABS_NGT_PS,
MIPS_BUILTIN_LOWER_CABS_NGT_PS,
MIPS_BUILTIN_ALL_CABS_NGT_PS,
MIPS_BUILTIN_ANY_C_F_4S,
MIPS_BUILTIN_ALL_C_F_4S,
MIPS_BUILTIN_ANY_C_UN_4S,
MIPS_BUILTIN_ALL_C_UN_4S,
MIPS_BUILTIN_ANY_C_EQ_4S,
MIPS_BUILTIN_ALL_C_EQ_4S,
MIPS_BUILTIN_ANY_C_UEQ_4S,
MIPS_BUILTIN_ALL_C_UEQ_4S,
MIPS_BUILTIN_ANY_C_OLT_4S,
MIPS_BUILTIN_ALL_C_OLT_4S,
MIPS_BUILTIN_ANY_C_ULT_4S,
MIPS_BUILTIN_ALL_C_ULT_4S,
MIPS_BUILTIN_ANY_C_OLE_4S,
MIPS_BUILTIN_ALL_C_OLE_4S,
MIPS_BUILTIN_ANY_C_ULE_4S,
MIPS_BUILTIN_ALL_C_ULE_4S,
MIPS_BUILTIN_ANY_C_SF_4S,
MIPS_BUILTIN_ALL_C_SF_4S,
MIPS_BUILTIN_ANY_C_NGLE_4S,
MIPS_BUILTIN_ALL_C_NGLE_4S,
MIPS_BUILTIN_ANY_C_SEQ_4S,
MIPS_BUILTIN_ALL_C_SEQ_4S,
MIPS_BUILTIN_ANY_C_NGL_4S,
MIPS_BUILTIN_ALL_C_NGL_4S,
MIPS_BUILTIN_ANY_C_LT_4S,
MIPS_BUILTIN_ALL_C_LT_4S,
MIPS_BUILTIN_ANY_C_NGE_4S,
MIPS_BUILTIN_ALL_C_NGE_4S,
MIPS_BUILTIN_ANY_C_LE_4S,
MIPS_BUILTIN_ALL_C_LE_4S,
MIPS_BUILTIN_ANY_C_NGT_4S,
MIPS_BUILTIN_ALL_C_NGT_4S,
MIPS_BUILTIN_ANY_CABS_F_4S,
MIPS_BUILTIN_ALL_CABS_F_4S,
MIPS_BUILTIN_ANY_CABS_UN_4S,
MIPS_BUILTIN_ALL_CABS_UN_4S,
MIPS_BUILTIN_ANY_CABS_EQ_4S,
MIPS_BUILTIN_ALL_CABS_EQ_4S,
MIPS_BUILTIN_ANY_CABS_UEQ_4S,
MIPS_BUILTIN_ALL_CABS_UEQ_4S,
MIPS_BUILTIN_ANY_CABS_OLT_4S,
MIPS_BUILTIN_ALL_CABS_OLT_4S,
MIPS_BUILTIN_ANY_CABS_ULT_4S,
MIPS_BUILTIN_ALL_CABS_ULT_4S,
MIPS_BUILTIN_ANY_CABS_OLE_4S,
MIPS_BUILTIN_ALL_CABS_OLE_4S,
MIPS_BUILTIN_ANY_CABS_ULE_4S,
MIPS_BUILTIN_ALL_CABS_ULE_4S,
MIPS_BUILTIN_ANY_CABS_SF_4S,
MIPS_BUILTIN_ALL_CABS_SF_4S,
MIPS_BUILTIN_ANY_CABS_NGLE_4S,
MIPS_BUILTIN_ALL_CABS_NGLE_4S,
MIPS_BUILTIN_ANY_CABS_SEQ_4S,
MIPS_BUILTIN_ALL_CABS_SEQ_4S,
MIPS_BUILTIN_ANY_CABS_NGL_4S,
MIPS_BUILTIN_ALL_CABS_NGL_4S,
MIPS_BUILTIN_ANY_CABS_LT_4S,
MIPS_BUILTIN_ALL_CABS_LT_4S,
MIPS_BUILTIN_ANY_CABS_NGE_4S,
MIPS_BUILTIN_ALL_CABS_NGE_4S,
MIPS_BUILTIN_ANY_CABS_LE_4S,
MIPS_BUILTIN_ALL_CABS_LE_4S,
MIPS_BUILTIN_ANY_CABS_NGT_4S,
MIPS_BUILTIN_ALL_CABS_NGT_4S,
MIPS_BUILTIN_CABS_F_S,
MIPS_BUILTIN_CABS_UN_S,
MIPS_BUILTIN_CABS_EQ_S,
MIPS_BUILTIN_CABS_UEQ_S,
MIPS_BUILTIN_CABS_OLT_S,
MIPS_BUILTIN_CABS_ULT_S,
MIPS_BUILTIN_CABS_OLE_S,
MIPS_BUILTIN_CABS_ULE_S,
MIPS_BUILTIN_CABS_SF_S,
MIPS_BUILTIN_CABS_NGLE_S,
MIPS_BUILTIN_CABS_SEQ_S,
MIPS_BUILTIN_CABS_NGL_S,
MIPS_BUILTIN_CABS_LT_S,
MIPS_BUILTIN_CABS_NGE_S,
MIPS_BUILTIN_CABS_LE_S,
MIPS_BUILTIN_CABS_NGT_S,
MIPS_BUILTIN_CABS_F_D,
MIPS_BUILTIN_CABS_UN_D,
MIPS_BUILTIN_CABS_EQ_D,
MIPS_BUILTIN_CABS_UEQ_D,
MIPS_BUILTIN_CABS_OLT_D,
MIPS_BUILTIN_CABS_ULT_D,
MIPS_BUILTIN_CABS_OLE_D,
MIPS_BUILTIN_CABS_ULE_D,
MIPS_BUILTIN_CABS_SF_D,
MIPS_BUILTIN_CABS_NGLE_D,
MIPS_BUILTIN_CABS_SEQ_D,
MIPS_BUILTIN_CABS_NGL_D,
MIPS_BUILTIN_CABS_LT_D,
MIPS_BUILTIN_CABS_NGE_D,
MIPS_BUILTIN_CABS_LE_D,
MIPS_BUILTIN_CABS_NGT_D,
MIPS_BUILTIN_MOVT_C_F_PS,
MIPS_BUILTIN_MOVT_C_UN_PS,
MIPS_BUILTIN_MOVT_C_EQ_PS,
MIPS_BUILTIN_MOVT_C_UEQ_PS,
MIPS_BUILTIN_MOVT_C_OLT_PS,
MIPS_BUILTIN_MOVT_C_ULT_PS,
MIPS_BUILTIN_MOVT_C_OLE_PS,
MIPS_BUILTIN_MOVT_C_ULE_PS,
MIPS_BUILTIN_MOVT_C_SF_PS,
MIPS_BUILTIN_MOVT_C_NGLE_PS,
MIPS_BUILTIN_MOVT_C_SEQ_PS,
MIPS_BUILTIN_MOVT_C_NGL_PS,
MIPS_BUILTIN_MOVT_C_LT_PS,
MIPS_BUILTIN_MOVT_C_NGE_PS,
MIPS_BUILTIN_MOVT_C_LE_PS,
MIPS_BUILTIN_MOVT_C_NGT_PS,
MIPS_BUILTIN_MOVT_CABS_F_PS,
MIPS_BUILTIN_MOVT_CABS_UN_PS,
MIPS_BUILTIN_MOVT_CABS_EQ_PS,
MIPS_BUILTIN_MOVT_CABS_UEQ_PS,
MIPS_BUILTIN_MOVT_CABS_OLT_PS,
MIPS_BUILTIN_MOVT_CABS_ULT_PS,
MIPS_BUILTIN_MOVT_CABS_OLE_PS,
MIPS_BUILTIN_MOVT_CABS_ULE_PS,
MIPS_BUILTIN_MOVT_CABS_SF_PS,
MIPS_BUILTIN_MOVT_CABS_NGLE_PS,
MIPS_BUILTIN_MOVT_CABS_SEQ_PS,
MIPS_BUILTIN_MOVT_CABS_NGL_PS,
MIPS_BUILTIN_MOVT_CABS_LT_PS,
MIPS_BUILTIN_MOVT_CABS_NGE_PS,
MIPS_BUILTIN_MOVT_CABS_LE_PS,
MIPS_BUILTIN_MOVT_CABS_NGT_PS,
MIPS_BUILTIN_MOVF_C_F_PS,
MIPS_BUILTIN_MOVF_C_UN_PS,
MIPS_BUILTIN_MOVF_C_EQ_PS,
MIPS_BUILTIN_MOVF_C_UEQ_PS,
MIPS_BUILTIN_MOVF_C_OLT_PS,
MIPS_BUILTIN_MOVF_C_ULT_PS,
MIPS_BUILTIN_MOVF_C_OLE_PS,
MIPS_BUILTIN_MOVF_C_ULE_PS,
MIPS_BUILTIN_MOVF_C_SF_PS,
MIPS_BUILTIN_MOVF_C_NGLE_PS,
MIPS_BUILTIN_MOVF_C_SEQ_PS,
MIPS_BUILTIN_MOVF_C_NGL_PS,
MIPS_BUILTIN_MOVF_C_LT_PS,
MIPS_BUILTIN_MOVF_C_NGE_PS,
MIPS_BUILTIN_MOVF_C_LE_PS,
MIPS_BUILTIN_MOVF_C_NGT_PS,
MIPS_BUILTIN_MOVF_CABS_F_PS,
MIPS_BUILTIN_MOVF_CABS_UN_PS,
MIPS_BUILTIN_MOVF_CABS_EQ_PS,
MIPS_BUILTIN_MOVF_CABS_UEQ_PS,
MIPS_BUILTIN_MOVF_CABS_OLT_PS,
MIPS_BUILTIN_MOVF_CABS_ULT_PS,
MIPS_BUILTIN_MOVF_CABS_OLE_PS,
MIPS_BUILTIN_MOVF_CABS_ULE_PS,
MIPS_BUILTIN_MOVF_CABS_SF_PS,
MIPS_BUILTIN_MOVF_CABS_NGLE_PS,
MIPS_BUILTIN_MOVF_CABS_SEQ_PS,
MIPS_BUILTIN_MOVF_CABS_NGL_PS,
MIPS_BUILTIN_MOVF_CABS_LT_PS,
MIPS_BUILTIN_MOVF_CABS_NGE_PS,
MIPS_BUILTIN_MOVF_CABS_LE_PS,
MIPS_BUILTIN_MOVF_CABS_NGT_PS,
/* THE LAST BUILTIN. */
MIPS_BUILTIN_MAX_BUILTIN
};
/* MIPS builtin function types. */
enum mips_function_type
{
MIPS_V2SF_FTYPE_V2SF,
MIPS_V2SF_FTYPE_V2SF_V2SF,
MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF,
MIPS_V2SF_FTYPE_SF_SF,
MIPS_INT_FTYPE_V2SF_V2SF,
MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF,
MIPS_INT_FTYPE_SF_SF,
MIPS_INT_FTYPE_DF_DF,
MIPS_SF_FTYPE_V2SF,
MIPS_SF_FTYPE_SF,
MIPS_SF_FTYPE_SF_SF,
MIPS_DF_FTYPE_DF,
MIPS_DF_FTYPE_DF_DF,
/* The last type. */
MIPS_MAX_FTYPE_MAX
};
/* MIPS compare choices used for MIPS builtin functions. */
enum mips_cmp_choice
{
MIPS_CMP_ANY, /* Check if any result is true. */
MIPS_CMP_UPPER, /* Check if the upper one of two results is true. */
MIPS_CMP_LOWER, /* Check if the lower one of two results is true. */
MIPS_CMP_ALL, /* Check if all results are true. */
MIPS_CMP_MOVT, /* Conditional move if true. */
MIPS_CMP_MOVF, /* Conditional move if false. */
MIPS_CMP_MAX
};

237
gcc/config/mips/mips.md
View File

@ -48,7 +48,70 @@
(UNSPEC_ADDRESS_FIRST 100)
(FAKE_CALL_REGNO 79)])
(FAKE_CALL_REGNO 79)
;; For MIPS Paired-Singled Floating Point Instructions.
(UNSPEC_C_F 201)
(UNSPEC_C_UN 202)
(UNSPEC_C_EQ 203)
(UNSPEC_C_UEQ 204)
(UNSPEC_C_OLT 205)
(UNSPEC_C_ULT 206)
(UNSPEC_C_OLE 207)
(UNSPEC_C_ULE 208)
(UNSPEC_C_SF 209)
(UNSPEC_C_NGLE 210)
(UNSPEC_C_SEQ 211)
(UNSPEC_C_NGL 212)
(UNSPEC_C_LT 213)
(UNSPEC_C_NGE 214)
(UNSPEC_C_LE 215)
(UNSPEC_C_NGT 216)
;; MIPS64/MIPS32R2 alnv.ps
(UNSPEC_ALNV_PS 217)
;; MIPS-3D instructions
(UNSPEC_CABS_F 218)
(UNSPEC_CABS_UN 219)
(UNSPEC_CABS_EQ 220)
(UNSPEC_CABS_UEQ 221)
(UNSPEC_CABS_OLT 222)
(UNSPEC_CABS_ULT 223)
(UNSPEC_CABS_OLE 224)
(UNSPEC_CABS_ULE 225)
(UNSPEC_CABS_SF 226)
(UNSPEC_CABS_NGLE 227)
(UNSPEC_CABS_SEQ 228)
(UNSPEC_CABS_NGL 229)
(UNSPEC_CABS_LT 230)
(UNSPEC_CABS_NGE 231)
(UNSPEC_CABS_LE 232)
(UNSPEC_CABS_NGT 233)
(UNSPEC_ADDR_PS 234)
(UNSPEC_CVT_PW_PS 235)
(UNSPEC_CVT_PS_PW 236)
(UNSPEC_MULR_PS 237)
(UNSPEC_RECIP1_S 238)
(UNSPEC_RECIP1_D 239)
(UNSPEC_RECIP1_PS 240)
(UNSPEC_RECIP2_S 241)
(UNSPEC_RECIP2_D 242)
(UNSPEC_RECIP2_PS 243)
(UNSPEC_RSQRT1_S 244)
(UNSPEC_RSQRT1_D 245)
(UNSPEC_RSQRT1_PS 246)
(UNSPEC_RSQRT2_S 247)
(UNSPEC_RSQRT2_D 248)
(UNSPEC_RSQRT2_PS 249)
]
)
(include "predicates.md")
@ -471,6 +534,15 @@
[(set_attr "type" "fadd")
(set_attr "mode" "SF")])
(define_insn "addv2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=f")
(plus:V2SF (match_operand:V2SF 1 "register_operand" "f")
(match_operand:V2SF 2 "register_operand" "f")))]
"TARGET_PAIRED_SINGLE_FLOAT"
"add.ps\t%0,%1,%2"
[(set_attr "type" "fadd")
(set_attr "mode" "SF")])
(define_expand "add<mode>3"
[(set (match_operand:GPR 0 "register_operand")
(plus:GPR (match_operand:GPR 1 "register_operand")
@ -719,6 +791,15 @@
[(set_attr "type" "fadd")
(set_attr "mode" "SF")])
(define_insn "subv2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=f")
(minus:V2SF (match_operand:V2SF 1 "register_operand" "f")
(match_operand:V2SF 2 "register_operand" "f")))]
"TARGET_PAIRED_SINGLE_FLOAT"
"sub.ps\t%0,%1,%2"
[(set_attr "type" "fadd")
(set_attr "mode" "SF")])
(define_insn "sub<mode>3"
[(set (match_operand:GPR 0 "register_operand" "=d")
(minus:GPR (match_operand:GPR 1 "register_operand" "d")
@ -804,6 +885,14 @@
(set_attr "mode" "SF")
(set_attr "length" "8")])
(define_insn "mulv2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=f")
(mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
(match_operand:V2SF 2 "register_operand" "f")))]
"TARGET_PAIRED_SINGLE_FLOAT"
"mul.ps\t%0,%1,%2"
[(set_attr "type" "fmul")
(set_attr "mode" "SF")])
;; The original R4000 has a cpu bug. If a double-word or a variable
;; shift executes while an integer multiplication is in progress, the
@ -1602,6 +1691,16 @@
[(set_attr "type" "fmadd")
(set_attr "mode" "SF")])
(define_insn ""
[(set (match_operand:V2SF 0 "register_operand" "=f")
(plus:V2SF (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
(match_operand:V2SF 2 "register_operand" "f"))
(match_operand:V2SF 3 "register_operand" "f")))]
"TARGET_PAIRED_SINGLE_FLOAT"
"madd.ps\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "SF")])
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f")
(minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
@ -1623,6 +1722,16 @@
[(set_attr "type" "fmadd")
(set_attr "mode" "SF")])
(define_insn ""
[(set (match_operand:V2SF 0 "register_operand" "=f")
(minus:V2SF (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
(match_operand:V2SF 2 "register_operand" "f"))
(match_operand:V2SF 3 "register_operand" "f")))]
"TARGET_PAIRED_SINGLE_FLOAT"
"msub.ps\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "SF")])
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f")
(neg:DF (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
@ -1667,6 +1776,28 @@
[(set_attr "type" "fmadd")
(set_attr "mode" "SF")])
(define_insn "*nmaddv2sf"
[(set (match_operand:V2SF 0 "register_operand" "=f")
(neg:V2SF (plus:V2SF (mult:V2SF
(match_operand:V2SF 1 "register_operand" "f")
(match_operand:V2SF 2 "register_operand" "f"))
(match_operand:V2SF 3 "register_operand" "f"))))]
"TARGET_PAIRED_SINGLE_FLOAT && HONOR_SIGNED_ZEROS (V2SFmode)"
"nmadd.ps\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "SF")])
(define_insn "*nmaddv2sf_fastmath"
[(set (match_operand:V2SF 0 "register_operand" "=f")
(minus:V2SF (mult:V2SF (neg:V2SF
(match_operand:V2SF 1 "register_operand" "f"))
(match_operand:V2SF 2 "register_operand" "f"))
(match_operand:V2SF 3 "register_operand" "f")))]
"TARGET_PAIRED_SINGLE_FLOAT && !HONOR_SIGNED_ZEROS (V2SFmode)"
"nmadd.ps\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "SF")])
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f")
(neg:DF (minus:DF (mult:DF (match_operand:DF 2 "register_operand" "f")
@ -1710,6 +1841,27 @@
"nmsub.s\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "SF")])
(define_insn "*nmsubv2sf"
[(set (match_operand:V2SF 0 "register_operand" "=f")
(neg:V2SF (minus:V2SF
(mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
(match_operand:V2SF 2 "register_operand" "f"))
(match_operand:V2SF 3 "register_operand" "f"))))]
"TARGET_PAIRED_SINGLE_FLOAT && HONOR_SIGNED_ZEROS (V2SFmode)"
"nmsub.ps\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "SF")])
(define_insn "*nmsubv2sf_fastmath"
[(set (match_operand:V2SF 0 "register_operand" "=f")
(minus:V2SF (match_operand:V2SF 1 "register_operand" "f")
(mult:V2SF (match_operand:V2SF 2 "register_operand" "f")
(match_operand:V2SF 3 "register_operand" "f"))))]
"TARGET_PAIRED_SINGLE_FLOAT && !HONOR_SIGNED_ZEROS (V2SFmode)"
"nmsub.ps\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "SF")])
;;
;; ....................
@ -2033,6 +2185,14 @@
"abs.s\t%0,%1"
[(set_attr "type" "fabs")
(set_attr "mode" "SF")])
(define_insn "absv2sf2"
[(set (match_operand:V2SF 0 "register_operand" "=f")
(abs:V2SF (match_operand:V2SF 1 "register_operand" "f")))]
"TARGET_PAIRED_SINGLE_FLOAT"
"abs.ps\t%0,%1"
[(set_attr "type" "fabs")
(set_attr "mode" "SF")])
;;
;; ....................
@ -2133,6 +2293,14 @@ beq\t%2,%.,1b\;\
[(set_attr "type" "fneg")
(set_attr "mode" "SF")])
(define_insn "negv2sf2"
[(set (match_operand:V2SF 0 "register_operand" "=f")
(neg:V2SF (match_operand:V2SF 1 "register_operand" "f")))]
"TARGET_PAIRED_SINGLE_FLOAT"
"neg.ps\t%0,%1"
[(set_attr "type" "fneg")
(set_attr "mode" "SF")])
(define_insn "one_cmpl<mode>2"
[(set (match_operand:GPR 0 "register_operand" "=d")
(not:GPR (match_operand:GPR 1 "register_operand" "d")))]
@ -3749,6 +3917,26 @@ beq\t%2,%.,1b\;\
[(set_attr "type" "fpidxload")
(set_attr "mode" "DF")])
(define_insn "*ldxc1_v2sf_si"
[(set (match_operand:V2SF 0 "register_operand" "=f")
(mem:V2SF (plus:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d"))))]
"TARGET_PAIRED_SINGLE_FLOAT"
"ldxc1\t%0,%1(%2)"
[(set_attr "type" "fpidxload")
(set_attr "mode" "SF")
(set_attr "length" "4")])
(define_insn "*ldxc1_v2sf_di"
[(set (match_operand:V2SF 0 "register_operand" "=f")
(mem:V2SF (plus:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:DI 2 "register_operand" "d"))))]
"TARGET_PAIRED_SINGLE_FLOAT"
"ldxc1\t%0,%1(%2)"
[(set_attr "type" "fpidxload")
(set_attr "mode" "SF")
(set_attr "length" "4")])
(define_insn "*swxc1_<mode>"
[(set (mem:SF (plus:P (match_operand:P 1 "register_operand" "d")
(match_operand:P 2 "register_operand" "d")))
@ -3767,6 +3955,26 @@ beq\t%2,%.,1b\;\
[(set_attr "type" "fpidxstore")
(set_attr "mode" "DF")])
(define_insn "*sdxc1_v2sf_si"
[(set (mem:V2SF (plus:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d")))
(match_operand:V2SF 0 "register_operand" "f"))]
"TARGET_PAIRED_SINGLE_FLOAT"
"sdxc1\t%0,%1(%2)"
[(set_attr "type" "fpidxstore")
(set_attr "mode" "SF")
(set_attr "length" "4")])
(define_insn "*sdxc1_v2sf_di"
[(set (mem:V2SF (plus:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:DI 2 "register_operand" "d")))
(match_operand:V2SF 0 "register_operand" "f"))]
"TARGET_PAIRED_SINGLE_FLOAT"
"sdxc1\t%0,%1(%2)"
[(set_attr "type" "fpidxstore")
(set_attr "mode" "SF")
(set_attr "length" "4")])
;; 16-bit Integer moves
;; Unlike most other insns, the move insns can't be split with
@ -4094,6 +4302,29 @@ beq\t%2,%.,1b\;\
operands[3] = GEN_INT (-INTVAL (operands[1]));
})
;; 64-bit paired-single floating point moves
(define_expand "movv2sf"
[(set (match_operand:V2SF 0)
(match_operand:V2SF 1))]
"TARGET_PAIRED_SINGLE_FLOAT"
{
if (mips_legitimize_move (V2SFmode, operands[0], operands[1]))
DONE;
})
(define_insn "movv2sf_hardfloat_64bit"
[(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,*f,*d,*d,*d,*m")
(match_operand:V2SF 1 "move_operand" "f,YG,m,fYG,*d,*f,*d*YG,*m,*d"))]
"TARGET_PAIRED_SINGLE_FLOAT
&& TARGET_64BIT
&& (register_operand (operands[0], V2SFmode)
|| reg_or_0_operand (operands[1], V2SFmode))"
{ return mips_output_move (operands[0], operands[1]); }
[(set_attr "type" "fmove,xfer,fpload,fpstore,xfer,xfer,arith,load,store")
(set_attr "mode" "SF")
(set_attr "length" "4,4,*,*,4,4,4,*,*")])
;; The HI and LO registers are not truly independent. If we move an mthi
;; instruction before an mflo instruction, it will make the result of the
;; mflo unpredictable. The same goes for mtlo and mfhi.
@ -5815,3 +6046,7 @@ beq\t%2,%.,1b\;\
"reload_completed"
[(match_dup 0)]
{ operands[0] = mips_rewrite_small_data (operands[0]); })
; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
(include "mips-ps-3d.md")

10
gcc/config/mips/predicates.md
View File

@ -43,7 +43,7 @@
(match_test "INTVAL (op) + 1 != 0")))
(define_predicate "const_0_operand"
(and (match_code "const_int,const_double")
(and (match_code "const_int,const_double,const_vector")
(match_test "op == CONST0_RTX (GET_MODE (op))")))
(define_predicate "reg_or_0_operand"
@ -52,13 +52,19 @@
(match_operand 0 "register_operand")))
(define_predicate "const_1_operand"
(and (match_code "const_int,const_double")
(and (match_code "const_int,const_double,const_vector")
(match_test "op == CONST1_RTX (GET_MODE (op))")))
(define_predicate "reg_or_1_operand"
(ior (match_operand 0 "const_1_operand")
(match_operand 0 "register_operand")))
;; This is used for indexing into vectors, and hence only accepts const_int.
(define_predicate "const_0_or_1_operand"
(and (match_code "const_int")
(ior (match_test "op == CONST0_RTX (GET_MODE (op))")
(match_test "op == CONST1_RTX (GET_MODE (op))"))))
(define_predicate "fpr_operand"
(and (match_code "reg")
(match_test "FP_REG_P (REGNO (op))")))

14
gcc/doc/invoke.texi
View File

@ -538,6 +538,7 @@ Objective-C and Objective-C++ Dialects}.
-mips16 -mno-mips16 -mabi=@var{abi} -mabicalls -mno-abicalls @gol
-mxgot -mno-xgot -mgp32 -mgp64 -mfp32 -mfp64 @gol
-mhard-float -msoft-float -msingle-float -mdouble-float @gol
-mpaired-single -mips3d @gol
-mint64 -mlong64 -mlong32 @gol
-G@var{num} -membedded-data -mno-embedded-data @gol
-muninit-const-in-rodata -mno-uninit-const-in-rodata @gol
@ -9262,6 +9263,19 @@ operations.
Assume that the floating-point coprocessor supports double-precision
operations. This is the default.
@itemx -mpaired-single
@itemx -mno-paired-single
@opindex mpaired-single
@opindex mno-paired-single
Use (do not use) the paired single instructions.
@itemx -mips3d
@itemx -mno-mips3d
@opindex mips3d
@opindex mno-mips3d
Use (do not use) the MIPS-3D ASE. The option @option{-mips3d} implies
@option{-mpaired-single}.
@item -mint64
@opindex mint64
Force @code{int} and @code{long} types to be 64 bits wide. See