(mulsidi3-1, mulsidi3, umulsidi3-1, umulsidi3): Enable.
(smulsi3_highpart-1, smulsi3_highpart): New patterns. (umulsi3_highpart-1, umulsi3_highpart): Likewise. (movdi-1): Add r/x constraint. From-SVN: r10559
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68958847e7
commit
06e1bace95
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@ -506,46 +506,84 @@
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}
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}
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}")
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}")
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;; ??? Why is this disabled?
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(define_insn ""
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(define_insn ""
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[(set (reg:DI 20)
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[(set (reg:DI 20)
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(mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
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(mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
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(sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))]
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(sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))]
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"(TARGET_SH2) && 0"
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"TARGET_SH2"
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"dmuls.l %2,%1"
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"dmuls.l %2,%1"
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[(set_attr "type" "dmpy")])
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[(set_attr "type" "dmpy")])
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;; ??? Why is this disabled?
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(define_expand "mulsidi3"
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(define_expand "mulsidi3"
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[(set (reg:DI 20)
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[(set (reg:DI 20)
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(mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
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(mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
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(sign_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
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(sign_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
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(set (match_operand:DI 0 "arith_reg_operand" "")
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(set (match_operand:DI 0 "arith_reg_operand" "")
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(reg:DI 20))]
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(reg:DI 20))]
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"(TARGET_SH2) && 0"
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"TARGET_SH2"
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"")
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"")
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;; ??? Why is this disabled?
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(define_insn ""
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(define_insn ""
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[(set (reg:DI 20)
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[(set (reg:DI 20)
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(mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
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(mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
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(zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))]
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(zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))]
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"(TARGET_SH2) && 0"
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"TARGET_SH2"
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"dmulu.l %2,%1"
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"dmulu.l %2,%1"
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[(set_attr "type" "dmpy")])
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[(set_attr "type" "dmpy")])
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;; ??? Why is this disabled?
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(define_expand "umulsidi3"
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(define_expand "umulsidi3"
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[(set (reg:DI 20)
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[(set (reg:DI 20)
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(mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
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(mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
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(zero_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
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(zero_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
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(set (match_operand:DI 0 "arith_reg_operand" "")
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(set (match_operand:DI 0 "arith_reg_operand" "")
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(reg:DI 20))]
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(reg:DI 20))]
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"(TARGET_SH2) && 0"
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"TARGET_SH2"
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"")
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(define_insn ""
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[(set (reg:SI 20)
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(truncate:SI
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(lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
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(sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r")))
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(const_int 32))))
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(clobber (reg:SI 21))]
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"TARGET_SH2"
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"dmuls.l %2,%1"
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[(set_attr "type" "dmpy")])
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(define_expand "smulsi3_highpart"
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[(parallel [(set (reg:SI 20)
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(truncate:SI
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(lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
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(sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
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(const_int 32))))
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(clobber (reg:SI 21))])
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(set (match_operand:SI 0 "arith_reg_operand" "")
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(reg:SI 20))]
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"TARGET_SH2"
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"")
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(define_insn ""
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[(set (reg:SI 20)
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(truncate:SI
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(lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
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(zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r")))
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(const_int 32))))
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(clobber (reg:SI 21))]
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"TARGET_SH2"
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"dmulu.l %2,%1"
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[(set_attr "type" "dmpy")])
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(define_expand "umulsi3_highpart"
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[(parallel [(set (reg:SI 20)
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(truncate:SI
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(lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
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(zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
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(const_int 32))))
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(clobber (reg:SI 21))])
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(set (match_operand:SI 0 "arith_reg_operand" "")
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(reg:SI 20))]
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"TARGET_SH2"
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"")
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"")
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;; -------------------------------------------------------------------------
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;; -------------------------------------------------------------------------
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@ -1160,13 +1198,13 @@
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;; ??? This should be a define expand.
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;; ??? This should be a define expand.
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(define_insn ""
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(define_insn ""
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[(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,m,r")
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[(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,m,r,r")
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(match_operand:DI 1 "general_movsrc_operand" "Q,r,m,r,i"))]
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(match_operand:DI 1 "general_movsrc_operand" "Q,r,m,r,i,x"))]
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"arith_reg_operand (operands[0], DImode)
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"arith_reg_operand (operands[0], DImode)
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|| arith_reg_operand (operands[1], DImode)"
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|| arith_reg_operand (operands[1], DImode)"
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"* return output_movedouble (insn, operands, DImode);"
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"* return output_movedouble (insn, operands, DImode);"
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[(set_attr "length" "4")
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[(set_attr "length" "4")
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(set_attr "type" "pcload,move,load,store,move")])
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(set_attr "type" "pcload,move,load,store,move,move")])
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;; If the output is a register and the input is memory or a register, we have
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;; If the output is a register and the input is memory or a register, we have
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;; to be careful and see which word needs to be loaded first.
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;; to be careful and see which word needs to be loaded first.
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