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RISC-V: Always pass -misa-spec to assembler [PR104219] 

Add -misa-spec to OPTION_DEFAULT_SPECS to make sure -misa-spec will
always pass that into assembler, that prevent GCC and binutils using
different way to interpret the ISA string.

gcc/ChangeLog:

	PR target/104219
	* config.gcc (riscv*-*-*): Normalize the with_isa_spec value.
	(all_defaults): Add isa_spec.
	* config/riscv/riscv.h (OPTION_DEFAULT_SPECS): Add isa_spec.
This commit is contained in:
Kito Cheng 2022-01-25 20:44:04 +08:00
parent 119cea98f6
commit 06e32a5ebf
2 changed files with 5 additions and 1 deletions
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4
gcc/config.gcc
View File

@ -4643,12 +4643,14 @@ case "${target}" in
case "${with_isa_spec}" in
""|default|20191213|201912)
tm_defines="${tm_defines} TARGET_DEFAULT_ISA_SPEC=ISA_SPEC_CLASS_20191213"
with_isa_spec=20191213
;;
2.2)
tm_defines="${tm_defines} TARGET_DEFAULT_ISA_SPEC=ISA_SPEC_CLASS_2P2"
;;
20190608 | 201906)
tm_defines="${tm_defines} TARGET_DEFAULT_ISA_SPEC=ISA_SPEC_CLASS_20190608"
with_isa_spec=20190608
;;
*)
echo "--with-isa-spec only accept 2.2, 20191213, 201912, 20190608 or 201906" 1>&2
@ -5430,7 +5432,7 @@ case ${target} in
esac
t=
all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls lxc1-sxc1 madd4"
all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls lxc1-sxc1 madd4 isa_spec"
for option in $all_defaults
do
eval "val=\$with_"`echo $option | sed s/-/_/g`

2
gcc/config/riscv/riscv.h
View File

@ -60,6 +60,7 @@ extern const char *riscv_default_mtune (int argc, const char **argv);
--with-arch is ignored if -march or -mcpu is specified.
--with-abi is ignored if -mabi is specified.
--with-tune is ignored if -mtune or -mcpu is specified.
--with-isa-spec is ignored if -misa-spec is specified.
But using default -march/-mtune value if -mcpu don't have valid option. */
#define OPTION_DEFAULT_SPECS \
@ -70,6 +71,7 @@ extern const char *riscv_default_mtune (int argc, const char **argv);
" %{!mcpu=*:-march=%(VALUE)}" \
" %{mcpu=*:%:riscv_expand_arch_from_cpu(%* %(VALUE))}}" }, \
{"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
{"isa_spec", "%{!misa-spec=*:-misa-spec=%(VALUE)}" }, \
#ifdef IN_LIBGCC2
#undef TARGET_64BIT