re PR target/83831 ([RX] Unused bclr,bnot,bset insns)
gcc/ PR target/83831 * config/rx/rx-protos.h (rx_reg_dead_or_unused_after_insn, rx_copy_reg_dead_or_unused_notes, rx_fuse_in_memory_bitop): New declarations. (set_of_reg): New struct. (rx_find_set_of_reg, rx_find_use_of_reg): New functions. * config/rx/rx.c (rx_reg_dead_or_unused_after_insn, rx_copy_reg_dead_or_unused_notes, rx_fuse_in_memory_bitop): New functions. * config/rx/rx.md (andsi3, iorsi3, xorsi3): Convert to insn_and_split. Split into bitclr, bitset, bitinvert patterns if appropriate. (*bitset, *bitinvert, *bitclr): Convert to named insn_and_split and use rx_fuse_in_memory_bitop. (*bitset_in_memory, *bitinvert_in_memory, *bitclr_in_memory): Convert to named insn, correct maximum insn length. gcc/testsuite/ PR target/83831 * gcc.target/rx/pr83831.c: New tests. From-SVN: r257655
This commit is contained in:
Oleg Endo
parent
d1fe612461
commit
06e972705d
@ -1,3 +1,21 @@
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2018-02-14 Oleg Endo <olegendo@gcc.gnu.org>
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PR target/83831
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* config/rx/rx-protos.h (rx_reg_dead_or_unused_after_insn,
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rx_copy_reg_dead_or_unused_notes, rx_fuse_in_memory_bitop): New
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declarations.
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(set_of_reg): New struct.
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(rx_find_set_of_reg, rx_find_use_of_reg): New functions.
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* config/rx/rx.c (rx_reg_dead_or_unused_after_insn,
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rx_copy_reg_dead_or_unused_notes, rx_fuse_in_memory_bitop): New
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functions.
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* config/rx/rx.md (andsi3, iorsi3, xorsi3): Convert to insn_and_split.
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Split into bitclr, bitset, bitinvert patterns if appropriate.
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(*bitset, *bitinvert, *bitclr): Convert to named insn_and_split and
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use rx_fuse_in_memory_bitop.
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(*bitset_in_memory, *bitinvert_in_memory, *bitclr_in_memory): Convert
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to named insn, correct maximum insn length.
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2018-02-14 Jozef Lawrynowicz <jozefl.gcc@gmail.com>
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PR target/79242
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@ -63,6 +63,112 @@ extern void rx_notice_update_cc (rtx, rtx);
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extern void rx_split_cbranch (machine_mode, enum rtx_code,
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rtx, rtx, rtx);
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extern machine_mode rx_select_cc_mode (enum rtx_code, rtx, rtx);
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extern bool rx_reg_dead_or_unused_after_insn (const rtx_insn* i, int regno);
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extern void rx_copy_reg_dead_or_unused_notes (rtx reg, const rtx_insn* src,
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rtx_insn* dst);
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extern bool rx_fuse_in_memory_bitop (rtx* operands, rtx_insn* curr_insn,
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rtx (*gen_insn)(rtx, rtx));
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/* Result value of rx_find_set_of_reg. */
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struct set_of_reg
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{
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/* The insn where sh_find_set_of_reg stopped looking.
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Can be NULL_RTX if the end of the insn list was reached. */
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rtx_insn* insn;
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/* The set rtx of the specified reg if found, NULL_RTX otherwise. */
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const_rtx set_rtx;
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/* The set source rtx of the specified reg if found, NULL_RTX otherwise.
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Usually, this is the most interesting return value. */
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rtx set_src;
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};
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/* FIXME: Copy-pasta from SH. Move to rtl.h.
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Given a reg rtx and a start insn, try to find the insn that sets
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the specified reg by using the specified insn stepping function,
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such as 'prev_nonnote_nondebug_insn_bb'. When the insn is found,
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try to extract the rtx of the reg set. */
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template <typename F> inline set_of_reg
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rx_find_set_of_reg (rtx reg, rtx_insn* insn, F stepfunc,
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bool ignore_reg_reg_copies = false)
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{
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set_of_reg result;
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result.insn = insn;
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result.set_rtx = NULL_RTX;
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result.set_src = NULL_RTX;
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if (!REG_P (reg) || insn == NULL_RTX)
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return result;
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for (rtx_insn* i = stepfunc (insn); i != NULL_RTX; i = stepfunc (i))
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{
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if (BARRIER_P (i))
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break;
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if (!INSN_P (i) || DEBUG_INSN_P (i))
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continue;
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if (reg_set_p (reg, i))
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{
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if (CALL_P (i))
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break;
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result.insn = i;
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result.set_rtx = set_of (reg, i);
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if (result.set_rtx == NULL_RTX || GET_CODE (result.set_rtx) != SET)
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break;
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result.set_src = XEXP (result.set_rtx, 1);
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if (ignore_reg_reg_copies && REG_P (result.set_src))
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{
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reg = result.set_src;
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continue;
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}
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if (ignore_reg_reg_copies && SUBREG_P (result.set_src)
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&& REG_P (SUBREG_REG (result.set_src)))
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{
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reg = SUBREG_REG (result.set_src);
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continue;
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}
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break;
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}
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}
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/* If the searched reg is found inside a (mem (post_inc:SI (reg))), set_of
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will return NULL and set_rtx will be NULL.
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In this case report a 'not found'. result.insn will always be non-null
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at this point, so no need to check it. */
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if (result.set_src != NULL && result.set_rtx == NULL)
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result.set_src = NULL;
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return result;
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}
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/* FIXME: Move to rtlh.h. */
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template <typename F> inline rtx_insn*
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rx_find_use_of_reg (rtx reg, rtx_insn* insn, F stepfunc)
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{
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if (!REG_P (reg) || insn == NULL_RTX)
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return NULL;
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for (rtx_insn* i = stepfunc (insn); i != NULL_RTX; i = stepfunc (i))
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{
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if (BARRIER_P (i))
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break;
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if (!INSN_P (i) || DEBUG_INSN_P (i))
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continue;
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if (reg_overlap_mentioned_p (reg, PATTERN (i))
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|| (CALL_P (i) && find_reg_fusage (i, USE, reg)))
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return i;
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}
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return NULL;
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}
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#endif
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#endif /* GCC_RX_PROTOS_H */
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@ -3439,6 +3439,88 @@ rx_atomic_sequence::~rx_atomic_sequence (void)
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emit_insn (gen_mvtc (GEN_INT (CTRLREG_PSW), m_prev_psw_reg));
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}
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/* Given an insn and a reg number, tell whether the reg dies or is unused
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after the insn. */
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bool
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rx_reg_dead_or_unused_after_insn (const rtx_insn* i, int regno)
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{
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return find_regno_note (i, REG_DEAD, regno) != NULL
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|| find_regno_note (i, REG_UNUSED, regno) != NULL;
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}
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/* Copy dead and unused notes from SRC to DST for the specified REGNO. */
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void
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rx_copy_reg_dead_or_unused_notes (rtx reg, const rtx_insn* src, rtx_insn* dst)
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{
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int regno = REGNO (SUBREG_P (reg) ? SUBREG_REG (reg) : reg);
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if (rtx note = find_regno_note (src, REG_DEAD, regno))
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add_shallow_copy_of_reg_note (dst, note);
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if (rtx note = find_regno_note (src, REG_UNUSED, regno))
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add_shallow_copy_of_reg_note (dst, note);
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}
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/* Try to fuse the current bit-operation insn with the surrounding memory load
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and store. */
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bool
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rx_fuse_in_memory_bitop (rtx* operands, rtx_insn* curr_insn,
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rtx (*gen_insn)(rtx, rtx))
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{
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rtx op2_reg = SUBREG_P (operands[2]) ? SUBREG_REG (operands[2]) : operands[2];
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set_of_reg op2_def = rx_find_set_of_reg (op2_reg, curr_insn,
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prev_nonnote_nondebug_insn_bb);
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if (op2_def.set_src == NULL_RTX
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|| !MEM_P (op2_def.set_src)
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|| GET_MODE (op2_def.set_src) != QImode
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|| !rx_is_restricted_memory_address (XEXP (op2_def.set_src, 0),
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GET_MODE (op2_def.set_src))
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|| reg_used_between_p (operands[2], op2_def.insn, curr_insn)
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|| !rx_reg_dead_or_unused_after_insn (curr_insn, REGNO (op2_reg))
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)
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return false;
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/* The register operand originates from a memory load and the memory load
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could be fused with the bitop insn.
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Look for the following memory store with the same memory operand. */
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rtx mem = op2_def.set_src;
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/* If the memory is an auto-mod address, it can't be fused. */
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if (GET_CODE (XEXP (mem, 0)) == POST_INC
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|| GET_CODE (XEXP (mem, 0)) == PRE_INC
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|| GET_CODE (XEXP (mem, 0)) == POST_DEC
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|| GET_CODE (XEXP (mem, 0)) == PRE_DEC)
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return false;
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rtx_insn* op0_use = rx_find_use_of_reg (operands[0], curr_insn,
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next_nonnote_nondebug_insn_bb);
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if (op0_use == NULL
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|| !(GET_CODE (PATTERN (op0_use)) == SET
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&& RX_REG_P (XEXP (PATTERN (op0_use), 1))
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&& reg_overlap_mentioned_p (operands[0], XEXP (PATTERN (op0_use), 1))
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&& rtx_equal_p (mem, XEXP (PATTERN (op0_use), 0)))
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|| !rx_reg_dead_or_unused_after_insn (op0_use, REGNO (operands[0]))
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|| reg_set_between_p (operands[2], curr_insn, op0_use))
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return false;
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/* If the load-modify-store operation is fused it could potentially modify
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load/store ordering if there are other memory accesses between the load
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and the store for this insn. If there are volatile mems between the load
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and store it's better not to change the ordering. If there is a call
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between the load and store, it's also not safe to fuse it. */
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for (rtx_insn* i = next_nonnote_nondebug_insn_bb (op2_def.insn);
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i != NULL && i != op0_use;
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i = next_nonnote_nondebug_insn_bb (i))
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if (volatile_insn_p (PATTERN (i)) || CALL_P (i))
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return false;
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emit_insn (gen_insn (mem, operands[1]));
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set_insn_deleted (op2_def.insn);
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set_insn_deleted (op0_use);
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return true;
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}
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/* Implement TARGET_HARD_REGNO_NREGS. */
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static unsigned int
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@ -1094,7 +1094,7 @@
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DONE;
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})
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(define_insn "andsi3"
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(define_insn_and_split "andsi3"
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[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r")
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(and:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0")
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(match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q")))
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@ -1110,6 +1110,21 @@
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and\t%1, %0
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and\t%2, %1, %0
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and\t%Q2, %0"
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"&& RX_REG_P (operands[1]) && CONST_INT_P (operands[2])
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&& pow2p_hwi (~UINTVAL (operands[2]))"
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[(const_int 0)]
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{
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/* For negated single bit constants use the bclr insn for smaller code. */
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if (!rx_reg_dead_or_unused_after_insn (curr_insn, CC_REG))
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FAIL;
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rx_copy_reg_dead_or_unused_notes (operands[1], curr_insn,
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emit_insn (gen_bitclr (operands[0],
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GEN_INT (exact_log2 (~UINTVAL (operands[2]))),
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operands[1])));
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DONE;
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}
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[(set_attr "timings" "11,11,11,11,11,11,11,11,33")
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(set_attr "length" "2,2,3,4,5,6,2,5,5")]
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)
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@ -1383,7 +1398,7 @@
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[(set_attr "length" "2,3")]
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)
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(define_insn "iorsi3"
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(define_insn_and_split "iorsi3"
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[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r")
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(ior:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0")
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(match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q")))
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@ -1399,6 +1414,21 @@
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or\t%1, %0
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or\t%2, %1, %0
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or\t%Q2, %0"
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"&& RX_REG_P (operands[1]) && CONST_INT_P (operands[2])
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&& pow2p_hwi (UINTVAL (operands[2]))"
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[(const_int 0)]
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{
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/* For single bit constants use the bset insn for smaller code. */
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if (!rx_reg_dead_or_unused_after_insn (curr_insn, CC_REG))
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FAIL;
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rx_copy_reg_dead_or_unused_notes (operands[1], curr_insn,
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emit_insn (gen_bitset (operands[0],
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GEN_INT (exact_log2 (UINTVAL (operands[2]))),
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operands[1])));
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DONE;
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}
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[(set_attr "timings" "11,11,11,11,11,11,11,11,33")
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(set_attr "length" "2,2,3,4,5,6,2,3,5")]
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)
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@ -1704,7 +1734,7 @@
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DONE;
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})
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(define_insn "xorsi3"
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(define_insn_and_split "xorsi3"
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[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
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(xor:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
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(match_operand:SI 2 "rx_source_operand"
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@ -1712,6 +1742,21 @@
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(clobber (reg:CC CC_REG))]
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""
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"xor\t%Q2, %0"
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"&& RX_REG_P (operands[1]) && CONST_INT_P (operands[2])
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&& pow2p_hwi (UINTVAL (operands[2]))"
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[(const_int 0)]
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{
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/* For single bit constants use the bnot insn for smaller code. */
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if (!rx_reg_dead_or_unused_after_insn (curr_insn, CC_REG))
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FAIL;
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rx_copy_reg_dead_or_unused_notes (operands[1], curr_insn,
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emit_insn (gen_bitinvert (operands[0],
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GEN_INT (exact_log2 (UINTVAL (operands[2]))),
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operands[1])));
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DONE;
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}
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[(set_attr "timings" "11,11,11,11,11,33")
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(set_attr "length" "3,4,5,6,7,6")]
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)
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@ -1960,50 +2005,63 @@
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;; Bit manipulation instructions.
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;; ??? The *_in_memory patterns will not be matched without further help.
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;; At one time we had the insv expander generate them, but I suspect that
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;; in general we get better performance by exposing the register load to
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;; the optimizers.
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;;
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;; An alternate solution would be to re-organize these patterns such
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;; that allow both register and memory operands. This would allow the
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;; register allocator to spill and not load the register operand. This
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;; would be possible only for operations for which we have a constant
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;; bit offset, so that we can adjust the address by ofs/8 and replace
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;; the offset in the insn by ofs%8.
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;; The *_in_memory patterns will not be matched automatically, not even with
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;; combiner bridge patterns. Especially when the memory operands have a
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;; displacement, the resulting patterns look too complex.
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;; Instead we manually look around the matched insn to see if there is a
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;; preceeding memory load and a following memory store of the modified register
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;; which can be fused into the single *_in_memory insn.
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;; Do that before register allocation, as it can eliminate one temporary
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;; register that needs to be allocated.
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(define_insn "*bitset"
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(define_insn_and_split "bitset"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(ior:SI (ashift:SI (const_int 1)
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(match_operand:SI 1 "rx_shift_operand" "ri"))
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(match_operand:SI 2 "register_operand" "0")))]
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""
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"bset\t%1, %0"
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"&& can_create_pseudo_p ()"
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[(const_int 0)]
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{
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if (rx_fuse_in_memory_bitop (operands, curr_insn, &gen_bitset_in_memory))
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DONE;
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else
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FAIL;
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}
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[(set_attr "length" "3")]
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)
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(define_insn "*bitset_in_memory"
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(define_insn "bitset_in_memory"
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[(set (match_operand:QI 0 "rx_restricted_mem_operand" "+Q")
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(ior:QI (ashift:QI (const_int 1)
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(match_operand:QI 1 "nonmemory_operand" "ri"))
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(match_dup 0)))]
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""
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"bset\t%1, %0.B"
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[(set_attr "length" "3")
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[(set_attr "length" "5")
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(set_attr "timings" "33")]
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)
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(define_insn "*bitinvert"
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(define_insn_and_split "bitinvert"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(xor:SI (ashift:SI (const_int 1)
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(match_operand:SI 1 "rx_shift_operand" "ri"))
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(match_operand:SI 2 "register_operand" "0")))]
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""
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"bnot\t%1, %0"
|
||||
"&& can_create_pseudo_p ()"
|
||||
[(const_int 0)]
|
||||
{
|
||||
if (rx_fuse_in_memory_bitop (operands, curr_insn, &gen_bitinvert_in_memory))
|
||||
DONE;
|
||||
else
|
||||
FAIL;
|
||||
}
|
||||
[(set_attr "length" "3")]
|
||||
)
|
||||
|
||||
(define_insn "*bitinvert_in_memory"
|
||||
(define_insn "bitinvert_in_memory"
|
||||
[(set (match_operand:QI 0 "rx_restricted_mem_operand" "+Q")
|
||||
(xor:QI (ashift:QI (const_int 1)
|
||||
(match_operand:QI 1 "nonmemory_operand" "ri"))
|
||||
@ -2014,7 +2072,7 @@
|
||||
(set_attr "timings" "33")]
|
||||
)
|
||||
|
||||
(define_insn "*bitclr"
|
||||
(define_insn_and_split "bitclr"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(and:SI (not:SI
|
||||
(ashift:SI
|
||||
@ -2023,10 +2081,18 @@
|
||||
(match_operand:SI 2 "register_operand" "0")))]
|
||||
""
|
||||
"bclr\t%1, %0"
|
||||
"&& can_create_pseudo_p ()"
|
||||
[(const_int 0)]
|
||||
{
|
||||
if (rx_fuse_in_memory_bitop (operands, curr_insn, &gen_bitclr_in_memory))
|
||||
DONE;
|
||||
else
|
||||
FAIL;
|
||||
}
|
||||
[(set_attr "length" "3")]
|
||||
)
|
||||
|
||||
(define_insn "*bitclr_in_memory"
|
||||
(define_insn "bitclr_in_memory"
|
||||
[(set (match_operand:QI 0 "rx_restricted_mem_operand" "+Q")
|
||||
(and:QI (not:QI
|
||||
(ashift:QI
|
||||
@ -2035,7 +2101,7 @@
|
||||
(match_dup 0)))]
|
||||
""
|
||||
"bclr\t%1, %0.B"
|
||||
[(set_attr "length" "3")
|
||||
[(set_attr "length" "5")
|
||||
(set_attr "timings" "33")]
|
||||
)
|
||||
|
||||
|
||||
@ -1,3 +1,8 @@
|
||||
2018-02-14 Oleg Endo <olegendo@gcc.gnu.org>
|
||||
|
||||
PR target/83831
|
||||
* gcc.target/rx/pr83831.c: New tests.
|
||||
|
||||
2018-02-14 Jozef Lawrynowicz <jozefl.gcc@gmail.com>
|
||||
|
||||
PR target/79242
|
||||
|
||||
77
gcc/testsuite/gcc.target/rx/pr83831.c
Normal file
77
gcc/testsuite/gcc.target/rx/pr83831.c
Normal file
@ -0,0 +1,77 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-O1" } */
|
||||
/* { dg-final { scan-assembler-times "bclr" 6 } } */
|
||||
/* { dg-final { scan-assembler-times "bset" 6 } } */
|
||||
/* { dg-final { scan-assembler-times "bnot" 6 } } */
|
||||
|
||||
void
|
||||
test_0 (char* x, unsigned int y)
|
||||
{
|
||||
/* Expect 4x bclr here. */
|
||||
x[0] &= 0xFE;
|
||||
x[1] = y & ~(1 << 1);
|
||||
x[2] &= 0xFE;
|
||||
x[65000] &= 0xFE;
|
||||
}
|
||||
|
||||
unsigned int
|
||||
test_1 (unsigned int x, unsigned int y)
|
||||
{
|
||||
/* Expect 1x bclr here. */
|
||||
return x & ~(1 << y);
|
||||
}
|
||||
|
||||
unsigned int
|
||||
test_2 (unsigned int x)
|
||||
{
|
||||
/* Expect 1x bclr here. */
|
||||
return x & ~(1 << 1);
|
||||
}
|
||||
|
||||
void
|
||||
test_3 (char* x, unsigned int y)
|
||||
{
|
||||
/* Expect 4x bset here. */
|
||||
x[0] |= 0x10;
|
||||
x[1] = y | (1 << 1);
|
||||
x[2] |= 0x10;
|
||||
x[65000] |= 0x10;
|
||||
}
|
||||
|
||||
unsigned int
|
||||
test_4 (unsigned int x, unsigned int y)
|
||||
{
|
||||
/* Expect 1x bset here. */
|
||||
return x | (1 << y);
|
||||
}
|
||||
|
||||
unsigned int
|
||||
test_5 (unsigned int x)
|
||||
{
|
||||
/* Expect 1x bset here. */
|
||||
return x | (1 << 8);
|
||||
}
|
||||
|
||||
void
|
||||
test_6 (char* x, unsigned int y)
|
||||
{
|
||||
/* Expect 4x bnot here. */
|
||||
x[0] ^= 0x10;
|
||||
x[1] = y ^ (1 << 1);
|
||||
x[2] ^= 0x10;
|
||||
x[65000] ^= 0x10;
|
||||
}
|
||||
|
||||
unsigned int
|
||||
test_7 (unsigned int x, unsigned int y)
|
||||
{
|
||||
/* Expect 1x bnot here. */
|
||||
return x ^ (1 << y);
|
||||
}
|
||||
|
||||
unsigned int
|
||||
test_8 (unsigned int x)
|
||||
{
|
||||
/* Expect 1x bnot here. */
|
||||
return x ^ (1 << 8);
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user