re PR target/48250 (ICE in reload_cse_simplify_operands, at postreload.c:403)
2011-04-11 Chung-Lin Tang <cltang@codesourcery.com> Richard Earnshaw <rearnsha@arm.com> PR target/48250 * config/arm/arm.c (arm_legitimize_reload_address): Update cases to use sign-magnitude offsets. Reject unsupported unaligned cases. Add detailed description in comments. * config/arm/arm.md (reload_outdf): Disable for ARM mode; change condition from TARGET_32BIT to TARGET_ARM. Co-Authored-By: Richard Earnshaw <rearnsha@arm.com> From-SVN: r172297
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Chung-Lin Tang
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@ -1,3 +1,13 @@
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2011-04-11 Chung-Lin Tang <cltang@codesourcery.com>
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Richard Earnshaw <rearnsha@arm.com>
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PR target/48250
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* config/arm/arm.c (arm_legitimize_reload_address): Update cases
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to use sign-magnitude offsets. Reject unsupported unaligned
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cases. Add detailed description in comments.
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* config/arm/arm.md (reload_outdf): Disable for ARM mode; change
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condition from TARGET_32BIT to TARGET_ARM.
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2011-04-11 Nathan Froyd <froydnj@codesourcery.com>
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* tree.h (struct typed_tree): New.
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@ -6262,23 +6262,126 @@ arm_legitimize_reload_address (rtx *p,
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HOST_WIDE_INT val = INTVAL (XEXP (*p, 1));
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HOST_WIDE_INT low, high;
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if (mode == DImode || (mode == DFmode && TARGET_SOFT_FLOAT))
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low = ((val & 0xf) ^ 0x8) - 0x8;
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else if (TARGET_MAVERICK && TARGET_HARD_FLOAT)
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/* Need to be careful, -256 is not a valid offset. */
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low = val >= 0 ? (val & 0xff) : -((-val) & 0xff);
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else if (mode == SImode
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|| (mode == SFmode && TARGET_SOFT_FLOAT)
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|| ((mode == HImode || mode == QImode) && ! arm_arch4))
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/* Need to be careful, -4096 is not a valid offset. */
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low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff);
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else if ((mode == HImode || mode == QImode) && arm_arch4)
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/* Need to be careful, -256 is not a valid offset. */
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low = val >= 0 ? (val & 0xff) : -((-val) & 0xff);
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else if (GET_MODE_CLASS (mode) == MODE_FLOAT
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&& TARGET_HARD_FLOAT && TARGET_FPA)
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/* Need to be careful, -1024 is not a valid offset. */
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low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff);
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/* Detect coprocessor load/stores. */
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bool coproc_p = ((TARGET_HARD_FLOAT
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&& (TARGET_VFP || TARGET_FPA || TARGET_MAVERICK)
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&& (mode == SFmode || mode == DFmode
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|| (mode == DImode && TARGET_MAVERICK)))
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|| (TARGET_REALLY_IWMMXT
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&& VALID_IWMMXT_REG_MODE (mode))
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|| (TARGET_NEON
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&& (VALID_NEON_DREG_MODE (mode)
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|| VALID_NEON_QREG_MODE (mode))));
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/* For some conditions, bail out when lower two bits are unaligned. */
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if ((val & 0x3) != 0
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/* Coprocessor load/store indexes are 8-bits + '00' appended. */
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&& (coproc_p
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/* For DI, and DF under soft-float: */
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|| ((mode == DImode || mode == DFmode)
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/* Without ldrd, we use stm/ldm, which does not
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fair well with unaligned bits. */
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&& (! TARGET_LDRD
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/* Thumb-2 ldrd/strd is [-1020,+1020] in steps of 4. */
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|| TARGET_THUMB2))))
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return false;
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/* When breaking down a [reg+index] reload address into [(reg+high)+low],
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of which the (reg+high) gets turned into a reload add insn,
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we try to decompose the index into high/low values that can often
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also lead to better reload CSE.
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For example:
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ldr r0, [r2, #4100] // Offset too large
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ldr r1, [r2, #4104] // Offset too large
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is best reloaded as:
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add t1, r2, #4096
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ldr r0, [t1, #4]
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add t2, r2, #4096
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ldr r1, [t2, #8]
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which post-reload CSE can simplify in most cases to eliminate the
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second add instruction:
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add t1, r2, #4096
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ldr r0, [t1, #4]
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ldr r1, [t1, #8]
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The idea here is that we want to split out the bits of the constant
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as a mask, rather than as subtracting the maximum offset that the
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respective type of load/store used can handle.
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When encountering negative offsets, we can still utilize it even if
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the overall offset is positive; sometimes this may lead to an immediate
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that can be constructed with fewer instructions.
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For example:
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ldr r0, [r2, #0x3FFFFC]
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This is best reloaded as:
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add t1, r2, #0x400000
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ldr r0, [t1, #-4]
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The trick for spotting this for a load insn with N bits of offset
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(i.e. bits N-1:0) is to look at bit N; if it is set, then chose a
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negative offset that is going to make bit N and all the bits below
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it become zero in the remainder part.
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The SIGN_MAG_LOW_ADDR_BITS macro below implements this, with respect
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to sign-magnitude addressing (i.e. separate +- bit, or 1's complement),
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used in most cases of ARM load/store instructions. */
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#define SIGN_MAG_LOW_ADDR_BITS(VAL, N) \
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(((VAL) & ((1 << (N)) - 1)) \
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? (((VAL) & ((1 << ((N) + 1)) - 1)) ^ (1 << (N))) - (1 << (N)) \
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: 0)
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if (coproc_p)
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low = SIGN_MAG_LOW_ADDR_BITS (val, 10);
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else if (GET_MODE_SIZE (mode) == 8)
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{
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if (TARGET_LDRD)
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low = (TARGET_THUMB2
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? SIGN_MAG_LOW_ADDR_BITS (val, 10)
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: SIGN_MAG_LOW_ADDR_BITS (val, 8));
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else
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/* For pre-ARMv5TE (without ldrd), we use ldm/stm(db/da/ib)
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to access doublewords. The supported load/store offsets are
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-8, -4, and 4, which we try to produce here. */
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low = ((val & 0xf) ^ 0x8) - 0x8;
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}
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else if (GET_MODE_SIZE (mode) < 8)
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{
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/* NEON element load/stores do not have an offset. */
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if (TARGET_NEON_FP16 && mode == HFmode)
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return false;
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if (TARGET_THUMB2)
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{
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/* Thumb-2 has an asymmetrical index range of (-256,4096).
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Try the wider 12-bit range first, and re-try if the result
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is out of range. */
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low = SIGN_MAG_LOW_ADDR_BITS (val, 12);
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if (low < -255)
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low = SIGN_MAG_LOW_ADDR_BITS (val, 8);
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}
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else
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{
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if (mode == HImode || mode == HFmode)
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{
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if (arm_arch4)
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low = SIGN_MAG_LOW_ADDR_BITS (val, 8);
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else
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{
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/* The storehi/movhi_bytes fallbacks can use only
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[-4094,+4094] of the full ldrb/strb index range. */
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low = SIGN_MAG_LOW_ADDR_BITS (val, 12);
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if (low == 4095 || low == -4095)
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return false;
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}
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}
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else
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low = SIGN_MAG_LOW_ADDR_BITS (val, 12);
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}
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}
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else
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return false;
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@ -6188,7 +6188,7 @@
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[(match_operand:DF 0 "arm_reload_memory_operand" "=o")
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(match_operand:DF 1 "s_register_operand" "r")
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(match_operand:SI 2 "s_register_operand" "=&r")]
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"TARGET_32BIT"
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"TARGET_THUMB2"
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"
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{
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enum rtx_code code = GET_CODE (XEXP (operands[0], 0));
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