gcc/
* common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512DQ_SET): Define. (OPTION_MASK_ISA_AVX512DQ_UNSET): Ditto. (ix86_handle_option): Handle OPT_mavx512dq. * config/i386/cpuid.h (bit_AVX512DQ): Define. * config/i386/driver-i386.c (host_detect_local_cpu): Detect avx512dq, set -mavx512dq accordingly. * config/i386/i386-c.c (ix86_target_macros_internal): Handle OPTION_MASK_ISA_AVX512DQ. * config/i386/i386.c (ix86_target_string): Handle -mavx512dq. (ix86_option_override_internal): Define PTA_AVX512DQ, handle PTA_AVX512DQ and OPTION_MASK_ISA_AVX512DQ. (ix86_valid_target_attribute_inner_p): Handle OPT_mavx512dq. * config/i386/i386.h (TARGET_AVX512DQ): Define. (TARGET_AVX512DQ_P(x)): Ditto. * config/i386/i386.opt: Add mavx512dq. Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com> Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com> Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com> Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com> Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com> Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com> Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com> From-SVN: r213757
This commit is contained in:
Alexander Ivchenko
Kirill Yukhin
parent
7c581d613c
commit
07165dd72c
@ -1,3 +1,29 @@
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2014-08-08 Alexander Ivchenko <alexander.ivchenko@intel.com>
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Maxim Kuznetsov <maxim.kuznetsov@intel.com>
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Anna Tikhonova <anna.tikhonova@intel.com>
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Ilya Tocar <ilya.tocar@intel.com>
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Andrey Turetskiy <andrey.turetskiy@intel.com>
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Ilya Verbin <ilya.verbin@intel.com>
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Kirill Yukhin <kirill.yukhin@intel.com>
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Michael Zolotukhin <michael.v.zolotukhin@intel.com>
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* common/config/i386/i386-common.c
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(OPTION_MASK_ISA_AVX512DQ_SET): Define.
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(OPTION_MASK_ISA_AVX512DQ_UNSET): Ditto.
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(ix86_handle_option): Handle OPT_mavx512dq.
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* config/i386/cpuid.h (bit_AVX512DQ): Define.
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* config/i386/driver-i386.c (host_detect_local_cpu): Detect avx512dq,
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set -mavx512dq accordingly.
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* config/i386/i386-c.c (ix86_target_macros_internal): Handle
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OPTION_MASK_ISA_AVX512DQ.
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* config/i386/i386.c (ix86_target_string): Handle -mavx512dq.
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(ix86_option_override_internal): Define PTA_AVX512DQ, handle
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PTA_AVX512DQ and OPTION_MASK_ISA_AVX512DQ.
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(ix86_valid_target_attribute_inner_p): Handle OPT_mavx512dq.
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* config/i386/i386.h (TARGET_AVX512DQ): Define.
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(TARGET_AVX512DQ_P(x)): Ditto.
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* config/i386/i386.opt: Add mavx512dq.
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2014-08-08 Richard Biener <rguenther@suse.de>
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* builtins.c (c_getstr, readonly_data_expr, init_target_chars,
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@ -65,6 +65,8 @@ along with GCC; see the file COPYING3. If not see
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(OPTION_MASK_ISA_AVX512PF | OPTION_MASK_ISA_AVX512F_SET)
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#define OPTION_MASK_ISA_AVX512ER_SET \
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(OPTION_MASK_ISA_AVX512ER | OPTION_MASK_ISA_AVX512F_SET)
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#define OPTION_MASK_ISA_AVX512DQ_SET \
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(OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512F_SET)
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#define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM
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#define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW
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#define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED
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@ -156,6 +158,7 @@ along with GCC; see the file COPYING3. If not see
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#define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD
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#define OPTION_MASK_ISA_AVX512PF_UNSET OPTION_MASK_ISA_AVX512PF
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#define OPTION_MASK_ISA_AVX512ER_UNSET OPTION_MASK_ISA_AVX512ER
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#define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ
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#define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM
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#define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW
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#define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED
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@ -393,6 +396,19 @@ ix86_handle_option (struct gcc_options *opts,
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}
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return true;
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case OPT_mavx512dq:
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if (value)
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{
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opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ_SET;
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opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_SET;
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}
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else
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{
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opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512DQ_UNSET;
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opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_UNSET;
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}
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return true;
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case OPT_mfma:
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if (value)
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{
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@ -73,6 +73,7 @@
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#define bit_BMI2 (1 << 8)
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#define bit_RTM (1 << 11)
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#define bit_AVX512F (1 << 16)
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#define bit_AVX512DQ (1 << 17)
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#define bit_RDSEED (1 << 18)
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#define bit_ADX (1 << 19)
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#define bit_CLFLUSHOPT (1 << 23)
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@ -411,6 +411,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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unsigned int has_avx512er = 0, has_avx512pf = 0, has_avx512cd = 0;
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unsigned int has_avx512f = 0, has_sha = 0, has_prefetchwt1 = 0;
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unsigned int has_clflushopt = 0, has_xsavec = 0, has_xsaves = 0;
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unsigned int has_avx512dq = 0;
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bool arch;
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@ -489,6 +490,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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has_avx512cd = ebx & bit_AVX512CD;
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has_sha = ebx & bit_SHA;
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has_clflushopt = ebx & bit_CLFLUSHOPT;
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has_avx512dq = ebx & bit_AVX512DQ;
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has_prefetchwt1 = ecx & bit_PREFETCHWT1;
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}
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@ -901,6 +903,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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const char *clflushopt = has_clflushopt ? " -mclflushopt" : " -mno-clflushopt";
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const char *xsavec = has_xsavec ? " -mxsavec" : " -mno-xsavec";
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const char *xsaves = has_xsaves ? " -mxsaves" : " -mno-xsaves";
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const char *avx512dq = has_avx512dq ? " -mavx512dq" : " -mno-avx512dq";
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options = concat (options, mmx, mmx3dnow, sse, sse2, sse3, ssse3,
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sse4a, cx16, sahf, movbe, aes, sha, pclmul,
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@ -909,7 +912,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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hle, rdrnd, f16c, fsgsbase, rdseed, prfchw, adx,
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fxsr, xsave, xsaveopt, avx512f, avx512er,
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avx512cd, avx512pf, prefetchwt1, clflushopt,
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xsavec, xsaves, NULL);
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xsavec, xsaves, avx512dq, NULL);
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}
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done:
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@ -345,6 +345,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
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def_or_undef (parse_in, "__AVX512CD__");
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if (isa_flag & OPTION_MASK_ISA_AVX512PF)
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def_or_undef (parse_in, "__AVX512PF__");
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if (isa_flag & OPTION_MASK_ISA_AVX512DQ)
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def_or_undef (parse_in, "__AVX512DQ__");
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if (isa_flag & OPTION_MASK_ISA_FMA)
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def_or_undef (parse_in, "__FMA__");
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if (isa_flag & OPTION_MASK_ISA_RTM)
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@ -2592,6 +2592,7 @@ ix86_target_string (HOST_WIDE_INT isa, int flags, const char *arch,
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{ "-mavx512er", OPTION_MASK_ISA_AVX512ER },
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{ "-mavx512cd", OPTION_MASK_ISA_AVX512CD },
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{ "-mavx512pf", OPTION_MASK_ISA_AVX512PF },
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{ "-mavx512dq", OPTION_MASK_ISA_AVX512DQ },
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{ "-msse4a", OPTION_MASK_ISA_SSE4A },
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{ "-msse4.2", OPTION_MASK_ISA_SSE4_2 },
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{ "-msse4.1", OPTION_MASK_ISA_SSE4_1 },
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@ -3122,6 +3123,7 @@ ix86_option_override_internal (bool main_args_p,
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#define PTA_CLFLUSHOPT (HOST_WIDE_INT_1 << 47)
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#define PTA_XSAVEC (HOST_WIDE_INT_1 << 48)
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#define PTA_XSAVES (HOST_WIDE_INT_1 << 49)
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#define PTA_AVX512DQ (HOST_WIDE_INT_1 << 50)
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#define PTA_CORE2 \
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(PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
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@ -3689,6 +3691,9 @@ ix86_option_override_internal (bool main_args_p,
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if (processor_alias_table[i].flags & PTA_XSAVES
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&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_XSAVES))
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opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVES;
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if (processor_alias_table[i].flags & PTA_AVX512DQ
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&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512DQ))
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opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ;
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if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
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x86_prefetch_sse = true;
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@ -4545,6 +4550,7 @@ ix86_valid_target_attribute_inner_p (tree args, char *p_strings[],
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IX86_ATTR_ISA ("avx512pf", OPT_mavx512pf),
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IX86_ATTR_ISA ("avx512er", OPT_mavx512er),
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IX86_ATTR_ISA ("avx512cd", OPT_mavx512cd),
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IX86_ATTR_ISA ("avx512dq", OPT_mavx512dq),
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IX86_ATTR_ISA ("mmx", OPT_mmmx),
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IX86_ATTR_ISA ("pclmul", OPT_mpclmul),
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IX86_ATTR_ISA ("popcnt", OPT_mpopcnt),
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@ -71,6 +71,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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#define TARGET_AVX512ER_P(x) TARGET_ISA_AVX512ER_P(x)
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#define TARGET_AVX512CD TARGET_ISA_AVX512CD
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#define TARGET_AVX512CD_P(x) TARGET_ISA_AVX512CD_P(x)
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#define TARGET_AVX512DQ TARGET_ISA_AVX512DQ
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#define TARGET_AVX512DQ_P(x) TARGET_ISA_AVX512DQ_P(x)
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#define TARGET_FMA TARGET_ISA_FMA
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#define TARGET_FMA_P(x) TARGET_ISA_FMA_P(x)
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#define TARGET_SSE4A TARGET_ISA_SSE4A
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@ -641,6 +641,10 @@ mavx512cd
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Target Report Mask(ISA_AVX512CD) Var(ix86_isa_flags) Save
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Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512CD built-in functions and code generation
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mavx512dq
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Target Report Mask(ISA_AVX512DQ) Var(ix86_isa_flags) Save
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Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512DQ built-in functions and code generation
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mfma
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Target Report Mask(ISA_FMA) Var(ix86_isa_flags) Save
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Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation
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