LANGUAGES: Fix typos.

* LANGUAGES: Fix typos.
	* Makefile.in: Fix typos.
	* alias.c: Fix typos.
	* auto-inc-dec.c: Fix typos.
	* bb-reorder.c: Fix typos.
	* cfgcleanup.c: Fix typos.
	* cgraph.c: Fix typos.
	* cgraph.h: Fix typos.
	* cgraphunit.c: Fix typos.
	* collect2-aix.h: Fix typos.
	* collect2.c: Fix typos.
	* compare-elim.c: Fix typos.
	* config/alpha/vms.h: Fix typos.
	* config/arm/README-interworking: Fix typos.
	* config/arm/arm.c: Fix typos.
	* config/arm/iterators.md: Fix typos.
	* config/arm/vxworks.h: Fix typos.
	* config/avr/avr.c: Fix typos.
	* config/avr/avr.h: Fix typos.
	* config/avr/avr.md: Fix typos.
	* config/avr/builtins.def: Fix typos.
	* config/c6x/c6x.c: Fix typos.
	* config/cr16/cr16.c: Fix typos.
	* config/cr16/cr16.md: Fix typos.
	* config/cris/cris.md: Fix typos.
	* config/darwin.c: Fix typos.
	* config/darwin.opt: Fix typos.
	* config/i386/i386-c.c: Fix typos.
	* config/i386/i386.c: Fix typos.
	* config/ia64/ia64.c: Fix typos.
	* config/m68k/cf.md: Fix typos.
	* config/mep/mep.c: Fix typos.
	* config/microblaze/microblaze.c: Fix typos.
	* config/microblaze/microblaze.h: Fix typos.
	* config/mn10300/mn10300.c: Fix typos.
	* config/mn10300/mn10300.md: Fix typos.
	* config/pa/pa.c: Fix typos.
	* config/picochip/picochip.h: Fix typos.
	* config/rs6000/a2.md: Fix typos.
	* config/rs6000/rs6000.c: Fix typos.
	* config/rs6000/vector.md: Fix typos.
	* config/rx/rx.md: Fix typos.
	* config/rx/rx.opt: Fix typos.
	* config/s390/2097.md: Fix typos.
	* config/s390/s390.c: Fix typos.
	* config/s390/s390.h: Fix typos.
	* config/sh/sh.c: Fix typos.
	* config/sh/sh.md: Fix typos.
	* config/sparc/sync.md: Fix typos.
	* config/spu/spu.c: Fix typos.
	* config/spu/spu.md: Fix typos.
	* config/vms/vms.c: Fix typos.
	* config/vxworks-dummy.h: Fix typos.
	* config/vxworks.h: Fix typos.
	* cselib.c: Fix typos.
	* df-scan.c: Fix typos.
	* df.h: Fix typos.
	* doc/extend.texi: Fix typos.
	* doc/install.texi: Fix typos.
	* doc/invoke.texi: Fix typos.
	* doc/md.texi: Fix typos.
	* doc/plugins.texi: Fix typos.
	* doc/rtl.texi: Fix typos.
	* dse.c: Fix typos.
	* dwarf2asm.c: Fix typos.
	* dwarf2out.c: Fix typos.
	* except.h: Fix typos.
	* expr.c: Fix typos.
	* fold-const.c: Fix typos.
	* gcc.c: Fix typos.
	* gcse.c: Fix typos.
	* genautomata.c: Fix typos.
	* gengtype-state.c: Fix typos.
	* gengtype.c: Fix typos.
	* genhooks.c: Fix typos.
	* gimple-fold.c: Fix typos.
	* gimple-pretty-print.c: Fix typos.
	* gimple.c: Fix typos.
	* gimple.h: Fix typos.
	* gimplify.c: Fix typos.
	* graphite-interchange.c: Fix typos.
	* graphite-sese-to-poly.c: Fix typos.
	* ifcvt.c: Fix typos.
	* input.c: Fix typos.
	* ipa-cp.c: Fix typos.
	* ipa-inline-analysis.c: Fix typos.
	* ipa-inline-transform.c: Fix typos.
	* ipa-inline.c: Fix typos.
	* ipa-pure-const.c: Fix typos.
	* ipa-ref.h: Fix typos.
	* ipa-reference.c: Fix typos.
	* ipa-utils.c: Fix typos.
	* ipa.c: Fix typos.
	* ira-emit.c: Fix typos.
	* ira-lives.c: Fix typos.
	* lto-streamer.c: Fix typos.
	* lto-streamer.h: Fix typos.
	* lto-wrapper.c: Fix typos.
	* mcf.c: Fix typos.
	* mode-switching.c: Fix typos.
	* modulo-sched.c: Fix typos.
	* plugin.c: Fix typos.
	* postreload.c: Fix typos.
	* sched-deps.c: Fix typos.
	* sel-sched-ir.c: Fix typos.
	* sel-sched-ir.h: Fix typos.
	* sel-sched.c: Fix typos.
	* sese.c: Fix typos.
	* stor-layout.c: Fix typos.
	* target-hooks-macros.h: Fix typos.
	* target.def: Fix typos.
	* trans-mem.c: Fix typos.
	* tree-eh.c: Fix typos.
	* tree-predcom.c: Fix typos.
	* tree-sra.c: Fix typos.
	* tree-ssa-address.c: Fix typos.
	* tree-ssa-loop-ivopts.c: Fix typos.
	* tree-ssa-loop-niter.c: Fix typos.
	* tree-ssa-math-opts.c: Fix typos.
	* tree-ssa-pre.c: Fix typos.
	* tree-ssa-propagate.c: Fix typos.
	* tree-ssa-reassoc.c: Fix typos.
	* tree-ssa-sccvn.c: Fix typos.
	* tree-ssa-ter.c: Fix typos.
	* tree-ssa-uninit.c: Fix typos.
	* tree-ssanames.c: Fix typos.
	* tree-vect-generic.c: Fix typos.
	* tree-vect-slp.c: Fix typos.
	* tree.c: Fix typos.
	* tree.h: Fix typos.
	* varasm.c: Fix typos.
	* varpool.c: Fix typos.

From-SVN: r187959
This commit is contained in:
Joseph Myers 2012-05-29 15:14:06 +01:00 committed by Joseph Myers
parent aba6f2c2a9
commit 073a899888
133 changed files with 367 additions and 232 deletions

View File

@ -1,3 +1,138 @@
2012-05-29 Joseph Myers <joseph@codesourcery.com>
* LANGUAGES: Fix typos.
* Makefile.in: Fix typos.
* alias.c: Fix typos.
* auto-inc-dec.c: Fix typos.
* bb-reorder.c: Fix typos.
* cfgcleanup.c: Fix typos.
* cgraph.c: Fix typos.
* cgraph.h: Fix typos.
* cgraphunit.c: Fix typos.
* collect2-aix.h: Fix typos.
* collect2.c: Fix typos.
* compare-elim.c: Fix typos.
* config/alpha/vms.h: Fix typos.
* config/arm/README-interworking: Fix typos.
* config/arm/arm.c: Fix typos.
* config/arm/iterators.md: Fix typos.
* config/arm/vxworks.h: Fix typos.
* config/avr/avr.c: Fix typos.
* config/avr/avr.h: Fix typos.
* config/avr/avr.md: Fix typos.
* config/avr/builtins.def: Fix typos.
* config/c6x/c6x.c: Fix typos.
* config/cr16/cr16.c: Fix typos.
* config/cr16/cr16.md: Fix typos.
* config/cris/cris.md: Fix typos.
* config/darwin.c: Fix typos.
* config/darwin.opt: Fix typos.
* config/i386/i386-c.c: Fix typos.
* config/i386/i386.c: Fix typos.
* config/ia64/ia64.c: Fix typos.
* config/m68k/cf.md: Fix typos.
* config/mep/mep.c: Fix typos.
* config/microblaze/microblaze.c: Fix typos.
* config/microblaze/microblaze.h: Fix typos.
* config/mn10300/mn10300.c: Fix typos.
* config/mn10300/mn10300.md: Fix typos.
* config/pa/pa.c: Fix typos.
* config/picochip/picochip.h: Fix typos.
* config/rs6000/a2.md: Fix typos.
* config/rs6000/rs6000.c: Fix typos.
* config/rs6000/vector.md: Fix typos.
* config/rx/rx.md: Fix typos.
* config/rx/rx.opt: Fix typos.
* config/s390/2097.md: Fix typos.
* config/s390/s390.c: Fix typos.
* config/s390/s390.h: Fix typos.
* config/sh/sh.c: Fix typos.
* config/sh/sh.md: Fix typos.
* config/sparc/sync.md: Fix typos.
* config/spu/spu.c: Fix typos.
* config/spu/spu.md: Fix typos.
* config/vms/vms.c: Fix typos.
* config/vxworks-dummy.h: Fix typos.
* config/vxworks.h: Fix typos.
* cselib.c: Fix typos.
* df-scan.c: Fix typos.
* df.h: Fix typos.
* doc/extend.texi: Fix typos.
* doc/install.texi: Fix typos.
* doc/invoke.texi: Fix typos.
* doc/md.texi: Fix typos.
* doc/plugins.texi: Fix typos.
* doc/rtl.texi: Fix typos.
* dse.c: Fix typos.
* dwarf2asm.c: Fix typos.
* dwarf2out.c: Fix typos.
* except.h: Fix typos.
* expr.c: Fix typos.
* fold-const.c: Fix typos.
* gcc.c: Fix typos.
* gcse.c: Fix typos.
* genautomata.c: Fix typos.
* gengtype-state.c: Fix typos.
* gengtype.c: Fix typos.
* genhooks.c: Fix typos.
* gimple-fold.c: Fix typos.
* gimple-pretty-print.c: Fix typos.
* gimple.c: Fix typos.
* gimple.h: Fix typos.
* gimplify.c: Fix typos.
* graphite-interchange.c: Fix typos.
* graphite-sese-to-poly.c: Fix typos.
* ifcvt.c: Fix typos.
* input.c: Fix typos.
* ipa-cp.c: Fix typos.
* ipa-inline-analysis.c: Fix typos.
* ipa-inline-transform.c: Fix typos.
* ipa-inline.c: Fix typos.
* ipa-pure-const.c: Fix typos.
* ipa-ref.h: Fix typos.
* ipa-reference.c: Fix typos.
* ipa-utils.c: Fix typos.
* ipa.c: Fix typos.
* ira-emit.c: Fix typos.
* ira-lives.c: Fix typos.
* lto-streamer.c: Fix typos.
* lto-streamer.h: Fix typos.
* lto-wrapper.c: Fix typos.
* mcf.c: Fix typos.
* mode-switching.c: Fix typos.
* modulo-sched.c: Fix typos.
* plugin.c: Fix typos.
* postreload.c: Fix typos.
* sched-deps.c: Fix typos.
* sel-sched-ir.c: Fix typos.
* sel-sched-ir.h: Fix typos.
* sel-sched.c: Fix typos.
* sese.c: Fix typos.
* stor-layout.c: Fix typos.
* target-hooks-macros.h: Fix typos.
* target.def: Fix typos.
* trans-mem.c: Fix typos.
* tree-eh.c: Fix typos.
* tree-predcom.c: Fix typos.
* tree-sra.c: Fix typos.
* tree-ssa-address.c: Fix typos.
* tree-ssa-loop-ivopts.c: Fix typos.
* tree-ssa-loop-niter.c: Fix typos.
* tree-ssa-math-opts.c: Fix typos.
* tree-ssa-pre.c: Fix typos.
* tree-ssa-propagate.c: Fix typos.
* tree-ssa-reassoc.c: Fix typos.
* tree-ssa-sccvn.c: Fix typos.
* tree-ssa-ter.c: Fix typos.
* tree-ssa-uninit.c: Fix typos.
* tree-ssanames.c: Fix typos.
* tree-vect-generic.c: Fix typos.
* tree-vect-slp.c: Fix typos.
* tree.c: Fix typos.
* tree.h: Fix typos.
* varasm.c: Fix typos.
* varpool.c: Fix typos.
2012-05-29 Joseph Myers <joseph@codesourcery.com>
* doc/include/texinfo.tex: Update to version 2012-05-16.16.

View File

@ -3,7 +3,7 @@ Right now there is no documentation for the GCC tree -> rtl interfaces
Such documentation would be of great benefit to the project. Until such
time as we can formally start documenting the interface this file will
serve as a repository for information on these interface and any incompatable
serve as a repository for information on these interface and any incompatible
changes we've made.
2004-09-09:

View File

@ -293,7 +293,7 @@ mkinstalldirs=$(SHELL) $(srcdir)/../mkinstalldirs
# write_entries_to_file - writes each entry in a list
# to the specified file. Entries are written in chunks of
# $(write_entries_to_file_split) to accomodate systems with
# $(write_entries_to_file_split) to accommodate systems with
# severe command-line-length limitations.
# Parameters:
# $(1): variable containing entries to iterate over
@ -461,7 +461,7 @@ NATIVE_SYSTEM_HEADER_DIR = @NATIVE_SYSTEM_HEADER_DIR@
CROSS_SYSTEM_HEADER_DIR = @CROSS_SYSTEM_HEADER_DIR@
# autoconf sets SYSTEM_HEADER_DIR to one of the above.
# Purge it of unneccessary internal relative paths
# Purge it of unnecessary internal relative paths
# to directories that might not exist yet.
# The sed idiom for this is to repeat the search-and-replace until it doesn't match, using :a ... ta.
# Use single quotes here to avoid nested double- and backquotes, this

View File

@ -76,7 +76,7 @@ along with GCC; see the file COPYING3. If not see
The first two questions can be answered with a simple examination
of the type system. If structure X contains a field of type Y then
a store thru a pointer to an X can overwrite any field that is
a store through a pointer to an X can overwrite any field that is
contained (recursively) in an X (unless we know that px1 != px2).
The last two of the questions can be solved in the same way as the

View File

@ -495,7 +495,7 @@ attempt_change (rtx new_addr, rtx inc_reg)
return false;
}
/* Jump thru a lot of hoops to keep the attributes up to date. We
/* Jump through a lot of hoops to keep the attributes up to date. We
do not want to call one of the change address variants that take
an offset even though we know the offset in many cases. These
assume you are changing where the address is pointing by the

View File

@ -1524,7 +1524,7 @@ fix_up_fall_thru_edges (void)
/* We know the fall-thru edge crosses; if the cond
jump edge does NOT cross, and its destination is the
next block in the bb order, invert the jump
(i.e. fix it so the fall thru does not cross and
(i.e. fix it so the fall through does not cross and
the cond jump does). */
if (!cond_jump_crosses
@ -2251,7 +2251,7 @@ partition_hot_cold_basic_blocks (void)
/* Convert all crossing fall_thru edges to non-crossing fall
thrus to unconditional jumps (that jump to the original fall
thru dest). */
through dest). */
fix_up_fall_thru_edges ();
/* If the architecture does not have conditional branches that can

View File

@ -62,7 +62,7 @@ along with GCC; see the file COPYING3. If not see
/* Set to true when we are running first pass of try_optimize_cfg loop. */
static bool first_pass;
/* Set to true if crossjumps occured in the latest run of try_optimize_cfg. */
/* Set to true if crossjumps occurred in the latest run of try_optimize_cfg. */
static bool crossjumps_occured;
/* Set to true if we couldn't run an optimization due to stale liveness

View File

@ -413,7 +413,7 @@ cgraph_get_create_node (tree decl)
}
/* Mark ALIAS as an alias to DECL. DECL_NODE is cgraph node representing
the function body is associated with (not neccesarily cgraph_node (DECL). */
the function body is associated with (not necessarily cgraph_node (DECL). */
struct cgraph_node *
cgraph_create_function_alias (tree alias, tree decl)
@ -1581,7 +1581,7 @@ cgraph_node_can_be_local_p (struct cgraph_node *node)
NULL, true));
}
/* Call calback on NODE, thunks and aliases asociated to NODE.
/* Call calback on NODE, thunks and aliases associated to NODE.
When INCLUDE_OVERWRITABLE is false, overwritable aliases and thunks are
skipped. */
@ -1617,7 +1617,7 @@ cgraph_for_node_thunks_and_aliases (struct cgraph_node *node,
return false;
}
/* Call calback on NODE and aliases asociated to NODE.
/* Call calback on NODE and aliases associated to NODE.
When INCLUDE_OVERWRITABLE is false, overwritable aliases and thunks are
skipped. */
@ -2087,7 +2087,7 @@ verify_edge_count_and_frequency (struct cgraph_edge *e)
if (gimple_has_body_p (e->caller->symbol.decl)
&& !e->caller->global.inlined_to
/* FIXME: Inline-analysis sets frequency to 0 when edge is optimized out.
Remove this once edges are actualy removed from the function at that time. */
Remove this once edges are actually removed from the function at that time. */
&& (e->frequency
|| (inline_edge_summary_vec
&& ((VEC_length(inline_edge_summary_t, inline_edge_summary_vec)

View File

@ -1181,7 +1181,7 @@ varpool_alias_aliased_node (struct varpool_node *n)
/* Given NODE, walk the alias chain to return the function NODE is alias of.
Walk through thunk, too.
When AVAILABILITY is non-NULL, get minimal availablity in the chain. */
When AVAILABILITY is non-NULL, get minimal availability in the chain. */
static inline struct cgraph_node *
cgraph_function_node (struct cgraph_node *node, enum availability *availability)
@ -1211,7 +1211,7 @@ cgraph_function_node (struct cgraph_node *node, enum availability *availability)
/* Given NODE, walk the alias chain to return the function NODE is alias of.
Do not walk through thunks.
When AVAILABILITY is non-NULL, get minimal availablity in the chain. */
When AVAILABILITY is non-NULL, get minimal availability in the chain. */
static inline struct cgraph_node *
cgraph_function_or_thunk_node (struct cgraph_node *node, enum availability *availability)
@ -1239,7 +1239,7 @@ cgraph_function_or_thunk_node (struct cgraph_node *node, enum availability *avai
/* Given NODE, walk the alias chain to return the function NODE is alias of.
Do not walk through thunks.
When AVAILABILITY is non-NULL, get minimal availablity in the chain. */
When AVAILABILITY is non-NULL, get minimal availability in the chain. */
static inline struct varpool_node *
varpool_variable_node (struct varpool_node *node, enum availability *availability)

View File

@ -51,7 +51,7 @@ along with GCC; see the file COPYING3. If not see
The symbol table is constructed starting from the trivially needed
symbols finalized by the frontend. Functions are lowered into
GIMPLE representation and callgraph/reference lists are constructed.
Those are used to discover other neccesary functions and variables.
Those are used to discover other necessary functions and variables.
At the end the bodies of unreachable functions are removed.
@ -220,7 +220,7 @@ static GTY (()) tree vtable_entry_type;
/* Determine if function DECL is trivially needed and should stay in the
compilation unit. This is used at the symbol table construction time
and differs from later logic removing unnecesary functions that can
and differs from later logic removing unnecessary functions that can
take into account results of analysis, whole program info etc. */
static bool
@ -385,7 +385,7 @@ referred_to_p (symtab_node node)
{
struct ipa_ref *ref;
/* See if there are any refrences at all. */
/* See if there are any references at all. */
if (ipa_ref_list_referring_iterate (&node->symbol.ref_list, 0, ref))
return true;
/* For functions check also calls. */
@ -1534,7 +1534,7 @@ assemble_thunk (struct cgraph_node *node)
/* Assemble thunks and aliases asociated to NODE. */
/* Assemble thunks and aliases associated to NODE. */
static void
assemble_thunks_and_aliases (struct cgraph_node *node)
@ -1903,7 +1903,7 @@ get_alias_symbol (tree decl)
/* Weakrefs may be associated to external decls and thus not output
at expansion time. Emit all neccesary aliases. */
at expansion time. Emit all necessary aliases. */
static void
output_weakrefs (void)

View File

@ -29,7 +29,7 @@ along with GCC; see the file COPYING3. If not see
Definitions adapted from bfd. (Fairly heavily adapted in some cases.)
------------------------------------------------------------------------- */
/* Compatiblity types for bfd. */
/* Compatibility types for bfd. */
typedef unsigned HOST_WIDE_INT bfd_vma;
/* The size of an archive's fl_magic field. */
@ -135,7 +135,7 @@ struct external_filehdr_32
/* The number of entries in the symbol table. */
char f_nsyms[4];
/* The size of the auxillary header. */
/* The size of the auxiliary header. */
char f_opthdr[2];
/* Flags. */
@ -157,7 +157,7 @@ struct external_filehdr_64
/* The offset of the symbol table from the start of the file. */
char f_symptr[8];
/* The size of the auxillary header. */
/* The size of the auxiliary header. */
char f_opthdr[2];
/* Flags. */
@ -222,7 +222,7 @@ struct external_syment
/* The class of symbol (a C_* value). */
char n_sclass[1];
/* The number of auxillary symbols attached to this entry. */
/* The number of auxiliary symbols attached to this entry. */
char n_numaux[1];
};

View File

@ -842,7 +842,7 @@ add_lto_object (struct lto_object_list *list, const char *name)
files contain LTO info. The linker command line LTO_LD_ARGV
represents the linker command that would produce a final executable
without the use of LTO. OBJECT_LST is a vector of object file names
appearing in LTO_LD_ARGV that are to be considerd for link-time
appearing in LTO_LD_ARGV that are to be considered for link-time
recompilation, where OBJECT is a pointer to the last valid element.
(This awkward convention avoids an impedance mismatch with the
usage of similarly-named variables in main().) The elements of
@ -2567,7 +2567,7 @@ scan_prog_file (const char *prog_name, scanpass which_pass,
/* LTO objects must be in a known format. This check prevents
us from accepting an archive containing LTO objects, which
gcc cannnot currently handle. */
gcc cannot currently handle. */
if (which_pass == PASS_LTOINFO && !maybe_lto_object_file (prog_name))
return;

View File

@ -494,7 +494,7 @@ try_eliminate_compare (struct comparison *cmp)
{
rtx x, insn, bb_head, flags, in_a, cmp_src;
/* We must have found an interesting "clobber" preceeding the compare. */
/* We must have found an interesting "clobber" preceding the compare. */
if (cmp->prev_clobber == NULL)
return false;

View File

@ -153,7 +153,7 @@ typedef struct {int num_args; enum avms_arg_type atypes[6];} avms_arg_info;
#define DEFAULT_PCC_STRUCT_RETURN 0
/* Eventhough pointers are 64bits, only 32bit ever remain significant in code
/* Even though pointers are 64bits, only 32bit ever remain significant in code
addresses. */
#define MASK_RETURN_ADDR \
(flag_vms_pointer_size == VMS_POINTER_SIZE_NONE \

View File

@ -227,7 +227,7 @@ considerations when building programs and DLLs:
Switching between the ARM and Thumb instruction sets is accomplished
via the BX instruction which takes as an argument a register name.
Control is transfered to the address held in this register (with the
Control is transferred to the address held in this register (with the
bottom bit masked out), and if the bottom bit is set, then Thumb
instruction processing is enabled, otherwise ARM instruction
processing is enabled.

View File

@ -2588,7 +2588,7 @@ optimal_immediate_sequence (enum rtx_code code, unsigned HOST_WIDE_INT val,
int insns1, insns2;
struct four_ints tmp_sequence;
/* If we aren't targetting ARM, the best place to start is always at
/* If we aren't targeting ARM, the best place to start is always at
the bottom, otherwise look more closely. */
if (TARGET_ARM)
{
@ -8473,7 +8473,7 @@ cortex_a9_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost)
&& reg_overlap_mentioned_p (SET_DEST (PATTERN (insn)),
SET_DEST (PATTERN (dep))))
{
/* FMACS is a special case where the dependant
/* FMACS is a special case where the dependent
instruction can be issued 3 cycles before
the normal latency in case of an output
dependency. */
@ -16187,7 +16187,7 @@ arm_output_epilogue (rtx sibling)
now we have to use add/sub in those cases. However, the value
of that would be marginal, as both mov and add/sub are 32-bit
in ARM mode, and it would require extra conditionals
in arm_expand_prologue to distingish ARM-apcs-frame case
in arm_expand_prologue to distinguish ARM-apcs-frame case
(where frame pointer is required to point at first register)
and ARM-non-apcs-frame. Therefore, such change is postponed
until real need arise. */

View File

@ -36,7 +36,7 @@
;; A list of integer modes that are less than a word
(define_mode_iterator NARROW [QI HI])
;; A list of all the integer modes upto 64bit
;; A list of all the integer modes up to 64bit
(define_mode_iterator QHSD [QI HI SI DI])
;; A list of the 32bit and 64bit integer modes

View File

@ -1,5 +1,5 @@
/* Definitions of target machine for GCC,
for ARM with targetting the VXWorks run time environment.
for ARM with targeting the VXWorks run time environment.
Copyright (C) 1999, 2000, 2003, 2004, 2007, 2008, 2009, 2010, 2011
Free Software Foundation, Inc.

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@ -6840,7 +6840,7 @@ avr_progmem_p (tree decl, tree attributes)
/* Scan type TYP for pointer references to address space ASn.
Return ADDR_SPACE_GENERIC (i.e. 0) if all pointers targeting
the AS are also declared to be CONST.
Otherwise, return the respective addres space, i.e. a value != 0. */
Otherwise, return the respective address space, i.e. a value != 0. */
static addr_space_t
avr_nonconst_pointer_addrspace (tree typ)
@ -6884,7 +6884,7 @@ avr_nonconst_pointer_addrspace (tree typ)
}
/* Sanity check NODE so that all pointers targeting non-generic addres spaces
/* Sanity check NODE so that all pointers targeting non-generic address spaces
go along with CONST qualifier. Writing to these address spaces should
be detected and complained about as early as possible. */
@ -9727,7 +9727,7 @@ avr_emit_movmemhi (rtx *xop)
/* FIXME: Register allocator does a bad job and might spill address
register(s) inside the loop leading to additional move instruction
to/from stack which could clobber tmp_reg. Thus, do *not* emit
load and store as seperate insns. Instead, we perform the copy
load and store as separate insns. Instead, we perform the copy
by means of one monolithic insn. */
gcc_assert (TMP_REGNO == LPM_REGNO);

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@ -713,7 +713,7 @@ struct GTY(()) machine_function
int attributes_checked_p;
};
/* AVR does not round pushes, but the existance of this macro is
/* AVR does not round pushes, but the existence of this macro is
required in order for pushes to be generated. */
#define PUSH_ROUNDING(X) (X)

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@ -29,7 +29,7 @@
;; k Reverse branch condition.
;;..m..Constant Direct Data memory address.
;; i Print the SFR address quivalent of a CONST_INT or a CONST_INT
;; RAM address. The resulting addres is suitable to be used in IN/OUT.
;; RAM address. The resulting address is suitable to be used in IN/OUT.
;; o Displacement for (mem (plus (reg) (const_int))) operands.
;; p POST_INC or PRE_DEC address as a pointer (X, Y, Z)
;; r POST_INC or PRE_DEC address as a register (r26, r28, r30)

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@ -38,7 +38,7 @@ DEF_BUILTIN ("__builtin_avr_cli", 0, AVR_BUILTIN_CLI, void_ftype_void, CODE_FO
DEF_BUILTIN ("__builtin_avr_wdr", 0, AVR_BUILTIN_WDR, void_ftype_void, CODE_FOR_wdr)
DEF_BUILTIN ("__builtin_avr_sleep", 0, AVR_BUILTIN_SLEEP, void_ftype_void, CODE_FOR_sleep)
/* Mapped to respective instruction but might alse be folded away
/* Mapped to respective instruction but might also be folded away
or emit as libgcc call if ISA does not provide the instruction. */
DEF_BUILTIN ("__builtin_avr_swap", 1, AVR_BUILTIN_SWAP, uchar_ftype_uchar, CODE_FOR_rotlqi3_4)
DEF_BUILTIN ("__builtin_avr_fmul", 2, AVR_BUILTIN_FMUL, uint_ftype_uchar_uchar, CODE_FOR_fmul)

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@ -3630,7 +3630,7 @@ typedef struct c6x_sched_context
/* The current scheduling state. */
static struct c6x_sched_context ss;
/* The following variable value is DFA state before issueing the first insn
/* The following variable value is DFA state before issuing the first insn
in the current clock cycle. This is used in c6x_variable_issue for
comparison with the state after issuing the last insn in a cycle. */
static state_t prev_cycle_state;

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@ -61,7 +61,7 @@
#define FUNC_IS_NORETURN_P(decl) (TREE_THIS_VOLATILE (decl))
/* Predicate that holds when we need to save registers even for 'noreturn'
functions, to accomodate for unwinding. */
functions, to accommodate for unwinding. */
#define MUST_SAVE_REGS_P() \
(flag_unwind_tables || (flag_exceptions && !UI_SJLJ))

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@ -144,7 +144,7 @@
[(set_attr "length" "2")]
)
;; Arithmetic Instuction Patterns
;; Arithmetic Instruction Patterns
;; Addition-Subtraction "adddi3/subdi3" insns.
(define_insn "<plusminus_insn>di3"

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@ -1530,7 +1530,7 @@
"movs<m> %1,%0"
[(set_attr "slottable" "yes,yes,no")])
;; To do a byte->word extension, extend to dword, exept that the top half
;; To do a byte->word extension, extend to dword, except that the top half
;; of the register will be clobbered. FIXME: Perhaps this is not needed.
(define_insn "extendqihi2"

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@ -3461,7 +3461,7 @@ darwin_function_section (tree decl, enum node_frequency freq,
/* Startup code should go to startup subsection unless it is
unlikely executed (this happens especially with function splitting
where we can split away unnecesary parts of static constructors). */
where we can split away unnecessary parts of static constructors). */
if (startup && freq != NODE_FREQUENCY_UNLIKELY_EXECUTED)
return (weak)
? darwin_sections[text_startup_coal_section]

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@ -224,7 +224,7 @@ Generate code suitable for fast turn around debugging
; and cc1plus don't crash if no -mmacosx-version-min is passed. The
; driver will always pass a -mmacosx-version-min, so in normal use the
; Init is never used. Useful for setting the OS on which people
; ususally debug.
; usually debug.
mmacosx-version-min=
Target Joined Report Var(darwin_macosx_version_min) Init("10.6")
The earliest MacOS X version on which this program will run

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@ -48,7 +48,7 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
void (*def_or_undef) (cpp_reader *,
const char *))
{
/* For some of the k6/pentium varients there weren't seperate ISA bits to
/* For some of the k6/pentium varients there weren't separate ISA bits to
identify which tune/arch flag was passed, so figure it out here. */
size_t arch_len = strlen (ix86_arch_string);
size_t tune_len = strlen (ix86_tune_string);

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@ -9185,7 +9185,7 @@ choose_baseaddr (HOST_WIDE_INT cfa_offset)
if (m->use_fast_prologue_epilogue)
{
/* Choose the base register most likely to allow the most scheduling
opportunities. Generally FP is valid througout the function,
opportunities. Generally FP is valid throughout the function,
while DRAP must be reloaded within the epilogue. But choose either
over the SP due to increased encoding size. */
@ -33112,7 +33112,7 @@ ix86_count_insn (basic_block bb)
return min_prev_count;
}
/* Pad short funtion to 4 instructions. */
/* Pad short function to 4 instructions. */
static void
ix86_pad_short_function (void)
@ -36909,7 +36909,7 @@ expand_vec_perm_interleave2 (struct expand_vec_perm_d *d)
{
if (d->perm[0] / nelt2 == nonzero_halves[1])
{
/* Attempt to increase the likelyhood that dfinal
/* Attempt to increase the likelihood that dfinal
shuffle will be intra-lane. */
char tmph = nonzero_halves[0];
nonzero_halves[0] = nonzero_halves[1];
@ -38985,7 +38985,7 @@ fits_dispatch_window (rtx insn)
/* Make disp_cmp and disp_jcc get scheduled at the latest. These
instructions should be given the lowest priority in the
scheduling process in Haifa scheduler to make sure they will be
scheduled in the same dispatch window as the refrence to them. */
scheduled in the same dispatch window as the reference to them. */
if (group == disp_jcc || group == disp_cmp)
return false;

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@ -3454,7 +3454,7 @@ output_probe_stack_range (rtx reg1, rtx reg2)
Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
so that the debug info generation code can handle them properly.
The register save area is layed out like so:
The register save area is laid out like so:
cfa+16
[ varargs spill area ]
[ fr register spill area ]

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@ -52,7 +52,7 @@
(define_cpu_unit "cf_dsoc,cf_agex" "cfv123_oep")
;; A memory unit that is reffered to as 'certain hardware resources' in
;; A memory unit that is referred to as 'certain hardware resources' in
;; ColdFire reference manuals. This unit remains occupied for two cycles
;; after last dsoc cycle of a store - hence there is a 2 cycle delay between
;; two consecutive stores.

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@ -3869,7 +3869,7 @@ static int prev_opcode = 0;
/* This isn't as optimal as it could be, because we don't know what
control register the STC opcode is storing in. We only need to add
the nop if it's the relevent register, but we add it for irrelevent
the nop if it's the relevant register, but we add it for irrelevant
registers also. */
void
@ -6993,7 +6993,7 @@ core_insn_p (rtx insn)
}
/* Mark coprocessor instructions that can be bundled together with
the immediately preceeding core instruction. This is later used
the immediately preceding core instruction. This is later used
to emit the "+" that tells the assembler to create a VLIW insn.
For unbundled insns, the assembler will automatically add coprocessor

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@ -190,7 +190,7 @@ enum reg_class microblaze_regno_to_class[] =
/* MicroBlaze specific machine attributes.
interrupt_handler - Interrupt handler attribute to add interrupt prologue
and epilogue and use appropriate interrupt return.
save_volatiles - Similiar to interrupt handler, but use normal return. */
save_volatiles - Similar to interrupt handler, but use normal return. */
int interrupt_handler;
int save_volatiles;

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@ -546,7 +546,7 @@ typedef struct microblaze_args
#define FUNCTION_MODE SImode
/* Mode should alwasy be SImode */
/* Mode should always be SImode */
#define REGISTER_MOVE_COST(MODE, FROM, TO) \
( GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? 2 \
: (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4 \

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@ -2762,7 +2762,7 @@ mn10300_adjust_sched_cost (rtx insn, rtx link, rtx dep, int cost)
Chapter 3 of the MN103E Series Instruction Manual
where it says:
"When the preceeding instruction is a CPU load or
"When the preceding instruction is a CPU load or
store instruction, a following FPU instruction
cannot be executed until the CPU completes the
latency period even though there are no register
@ -2788,7 +2788,7 @@ mn10300_adjust_sched_cost (rtx insn, rtx link, rtx dep, int cost)
return cost;
/* XXX: Verify: The text of 1-7-4 implies that the restriction
only applies when an INTEGER load/store preceeds an FPU
only applies when an INTEGER load/store precedes an FPU
instruction, but is this true ? For now we assume that it is. */
if (GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (insn)))) != MODE_INT)
return cost;

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@ -999,7 +999,7 @@
;; ??? Note that AM33 has a third multiply variant that puts the high part
;; into the MDRQ register, however this variant also constrains the inputs
;; to be in DATA_REGS and thus isn't as helpful as it might be considering
;; the existance of the 4-operand multiply. Nor is there a set of divide
;; the existence of the 4-operand multiply. Nor is there a set of divide
;; insns that use MDRQ. Given that there is an IMM->MDRQ insn, this would
;; have been very handy for starting udivmodsi4...
@ -1808,7 +1808,7 @@
)
;; ----------------------------------------------------------------------
;; MISCELANEOUS
;; MISCELLANEOUS
;; ----------------------------------------------------------------------
;; Note the use of the (const_int 0) when generating the insn that matches

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@ -5939,7 +5939,7 @@ pa_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
}
/* Request a secondary reload with a general scratch register
for everthing else. ??? Could symbolic operands be handled
for everything else. ??? Could symbolic operands be handled
directly when generating non-pic PA 2.0 code? */
sri->icode = (in_p
? direct_optab_handler (reload_in_optab, mode)

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@ -221,7 +221,7 @@ extern enum picochip_dfa_type picochip_schedule_type;
#define CALL_USED_REGISTERS {1,1,1,1,1,1,0,0, 0,0,0,0,1,1,0,1, 1,1,1,1}
#define CALL_REALLY_USED_REGISTERS {1,1,1,1,1,1,0,0, 0,0,0,0,1,1,0,0, 0,1,0,0}
/* Define the number of the picoChip link and condition psuedo registers. */
/* Define the number of the picoChip link and condition pseudo registers. */
#define LINK_REGNUM 12
#define CC_REGNUM 17
#define ACC_REGNUM 16

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@ -25,7 +25,7 @@
;; The multiplier pipeline.
(define_cpu_unit "mult" "ppca2")
;; The auxillary processor unit (FP/vector unit).
;; The auxiliary processor unit (FP/vector unit).
(define_cpu_unit "axu" "ppca2")
;; D.4.6

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@ -2077,7 +2077,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
/* TODO add SPE and paired floating point vector support. */
/* Register class constaints for the constraints that depend on compile
/* Register class constraints for the constraints that depend on compile
switches. */
if (TARGET_HARD_FLOAT && TARGET_FPRS)
rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS;
@ -2328,7 +2328,7 @@ darwin_rs6000_override_options (void)
/* Unless the user (not the configurer) has explicitly overridden
it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
G4 unless targetting the kernel. */
G4 unless targeting the kernel. */
if (!flag_mkernel
&& !flag_apple_kext
&& strverscmp (darwin_macosx_version_min, "10.5") >= 0

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@ -172,7 +172,7 @@
;; Reload patterns for vector operations. We may need an addtional base
;; Reload patterns for vector operations. We may need an additional base
;; register to convert the reg+offset addressing to reg+reg for vector
;; registers and reg+reg or (reg+reg)&(-16) addressing to just an index
;; register for gpr registers.

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@ -408,7 +408,7 @@
;; Note - the following set of patterns do not use the "memory_operand"
;; predicate or an "m" constraint because we do not allow symbol_refs
;; or label_refs as legitmate memory addresses. This matches the
;; or label_refs as legitimate memory addresses. This matches the
;; behaviour of most of the RX instructions. Only the call/branch
;; instructions are allowed to refer to symbols/labels directly.
;; The call operands are in QImode because that is the value of

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@ -87,7 +87,7 @@ Use the simulator runtime.
mas100-syntax
Target Mask(AS100_SYNTAX) Report
Generate assembler output that is compatible with the Renesas AS100 assembler. This may restrict some of the compiler's capabilities. The default is to generate GAS compatable syntax.
Generate assembler output that is compatible with the Renesas AS100 assembler. This may restrict some of the compiler's capabilities. The default is to generate GAS compatible syntax.
;---------------------------------------------------

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@ -703,11 +703,11 @@
; Declaration for some pseudo-pipeline stages that reflect the
; dispatch gap when issueing an INT/FXU/BFU-executed instruction after
; dispatch gap when issuing an INT/FXU/BFU-executed instruction after
; an instruction executed by a different unit has been executed. The
; approach is that we pretend a pipelined execution of BFU operations
; with as many stages as the gap is long and request that none of
; these stages is busy when issueing a FXU- or DFU-executed
; these stages is busy when issuing a FXU- or DFU-executed
; instruction. Similar for FXU- and DFU-executed instructions.
; Declaration for FPU stages.

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@ -10533,7 +10533,7 @@ s390_z10_prevent_earlyload_conflicts (rtx *ready, int *nready_p)
}
/* This function is called via hook TARGET_SCHED_REORDER before
issueing one insn from list READY which contains *NREADYP entries.
issuing one insn from list READY which contains *NREADYP entries.
For target z10 it reorders load instructions to avoid early load
conflicts in the floating point pipeline */
static int

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@ -762,7 +762,7 @@ do { \
/* This value is used in tree-sra to decide whether it might benefical
to split a struct move into several word-size moves. For S/390
only small values make sense here since struct moves are relatively
cheap thanks to mvc so the small default value choosen for archs
cheap thanks to mvc so the small default value chosen for archs
with memmove patterns should be ok. But this value is multiplied
in tree-sra with UNITS_PER_WORD to make a decision so we adjust it
here to compensate for that factor since mvc costs exactly the same

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@ -393,7 +393,7 @@ static const struct attribute_spec sh_attribute_table[] =
The insn that frees registers is most likely to be the insn with lowest
LUID (original insn order); but such an insn might be there in the stalled
queue (Q) instead of the ready queue (R). To solve this, we skip cycles
upto a max of 8 cycles so that such insns may move from Q -> R.
up to a max of 8 cycles so that such insns may move from Q -> R.
The description of the hooks are as below:
@ -11478,7 +11478,7 @@ sh_expand_binop_v2sf (enum rtx_code code, rtx op0, rtx op1, rtx op2)
We could hold SFmode / SCmode values in XD registers, but that
would require a tertiary reload when reloading from / to memory,
and a secondary reload to reload from / to general regs; that
seems to be a loosing proposition.
seems to be a losing proposition.
We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
it won't be ferried through GP registers first. */

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@ -577,7 +577,7 @@
(and (eq_attr "type" "cbranch")
(match_test "TARGET_SH2"))
;; SH2e has a hardware bug that pretty much prohibits the use of
;; annuled delay slots.
;; annulled delay slots.
[(eq_attr "cond_delay_slot" "yes") (and (eq_attr "cond_delay_slot" "yes")
(not (eq_attr "cpu" "sh2e"))) (nil)])
@ -631,7 +631,7 @@
[(set_attr "type" "mt_group")])
;; Test low QI subreg against zero.
;; This avoids unecessary zero extension before the test.
;; This avoids unnecessary zero extension before the test.
(define_insn "tstqi_t_zero"
[(set (reg:SI T_REG)
@ -5470,7 +5470,7 @@ label:
;; selected to copy QImode regs. If one of them happens to be allocated
;; on the stack, reload will stick to movqi insn and generate wrong
;; displacement addressing because of the generic m alternatives.
;; With the movqi_reg_reg being specified before movqi it will be intially
;; With the movqi_reg_reg being specified before movqi it will be initially
;; picked to load/store regs. If the regs regs are on the stack reload will
;; try other insns and not stick to movqi_reg_reg.
;; The same applies to the movhi variants.

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@ -45,7 +45,7 @@
})
;; A compiler-only memory barrier. Generic code, when checking for the
;; existance of various named patterns, uses asm("":::"memory") when we
;; existence of various named patterns, uses asm("":::"memory") when we
;; don't need an actual instruction. Here, it's easiest to pretend that
;; membar 0 is such a barrier. Further, this gives us a nice hook to
;; ignore all such barriers on Sparc V7.

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@ -2870,7 +2870,7 @@ spu_machine_dependent_reorg (void)
prop = prev;
/* If this is the JOIN block of a simple IF-THEN then
propogate the hint to the HEADER block. */
propagate the hint to the HEADER block. */
else if (prev && prev2
&& EDGE_COUNT (bb->preds) == 2
&& EDGE_COUNT (prev->preds) == 1
@ -3124,7 +3124,7 @@ spu_sched_variable_issue (FILE *file ATTRIBUTE_UNUSED,
prev_priority = INSN_PRIORITY (insn);
}
/* Always try issueing more insns. spu_sched_reorder will decide
/* Always try issuing more insns. spu_sched_reorder will decide
when the cycle should be advanced. */
return 1;
}
@ -3231,7 +3231,7 @@ spu_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
used to effect it. */
if (in_spu_reorg && spu_dual_nops < 10)
{
/* When we are at an even address and we are not issueing nops to
/* When we are at an even address and we are not issuing nops to
improve scheduling then we need to advance the cycle. */
if ((spu_sched_length & 7) == 0 && prev_clock_var == clock
&& (spu_dual_nops == 0

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@ -4209,7 +4209,7 @@ selb\t%0,%4,%0,%3"
""
{ spu_expand_prologue (); DONE; })
;; "blockage" is only emited in epilogue. This is what it took to
;; "blockage" is only emitted in epilogue. This is what it took to
;; make "basic block reordering" work with the insns sequence
;; generated by the spu_expand_epilogue (taken from mips.md)

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@ -99,12 +99,12 @@ static const struct vms_crtl_name vms_crtl_names[] =
#define NBR_CRTL_NAMES (sizeof (vms_crtl_names) / sizeof (*vms_crtl_names))
/* List of aliased identifiers. They must be persistant accross gc. */
/* List of aliased identifiers. They must be persistent across gc. */
static GTY(()) VEC(tree,gc) *aliases_id;
/* Add a CRTL translation. This simply use the transparent alias
mechanism, which is platform independant and works with the
mechanism, which is platform independent and works with the
#pragma extern_prefix (which set the assembler name). */
static void

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@ -22,7 +22,7 @@ a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* True if we're targetting VxWorks. */
/* True if we're targeting VxWorks. */
#ifndef TARGET_VXWORKS
#define TARGET_VXWORKS 0
#endif

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@ -20,7 +20,7 @@ You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* Assert that we are targetting VxWorks. */
/* Assert that we are targeting VxWorks. */
#undef TARGET_VXWORKS
#define TARGET_VXWORKS 1

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@ -1374,7 +1374,7 @@ cselib_lookup_mem (rtx x, int create)
return mem_elt;
}
/* Search thru the possible substitutions in P. We prefer a non reg
/* Search through the possible substitutions in P. We prefer a non reg
substitution because this allows us to expand the tree further. If
we find, just a reg, take the lowest regno. There may be several
non-reg results, we just take the first one because they will all

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@ -3734,7 +3734,7 @@ df_get_eh_block_artificial_uses (bitmap eh_block_artificial_uses)
{
bitmap_clear (eh_block_artificial_uses);
/* The following code (down thru the arg_pointer setting APPEARS
/* The following code (down through the arg_pointer setting APPEARS
to be necessary because there is nothing that actually
describes what the exception handling code may actually need
to keep alive. */
@ -4539,7 +4539,7 @@ df_scan_verify (void)
/* Verification is a 4 step process. */
/* (1) All of the refs are marked by going thru the reg chains. */
/* (1) All of the refs are marked by going through the reg chains. */
for (i = 0; i < DF_REG_SIZE (df); i++)
{
gcc_assert (df_reg_chain_mark (DF_REG_DEF_CHAIN (i), i, true, false)

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@ -367,7 +367,7 @@ struct df_base_ref
when FUDs are added. */
struct df_insn_info *insn_info;
/* For each regno, there are three chains of refs, one for the uses,
the eq_uses and the defs. These chains go thru the refs
the eq_uses and the defs. These chains go through the refs
themselves rather than using an external structure. */
union df_ref_d *next_reg; /* Next ref with same regno and type. */
union df_ref_d *prev_reg; /* Prev ref with same regno and type. */

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@ -3736,7 +3736,7 @@ the PowerPC V2.05 architecture.
@cindex @code{target("dlmzb")} attribute
Generate code that uses (does not use) the string-search @samp{dlmzb}
instruction on the IBM 405, 440, 464 and 476 processors. This instruction is
generated by default when targetting those processors.
generated by default when targeting those processors.
@item fprnd
@itemx no-fprnd
@ -3775,7 +3775,7 @@ other processors that support the extended PowerPC V2.05 architecture.
@cindex @code{target("mulhw")} attribute
Generate code that uses (does not use) the half-word multiply and
multiply-accumulate instructions on the IBM 405, 440, 464 and 476 processors.
These instructions are generated by default when targetting those
These instructions are generated by default when targeting those
processors.
@item multiple
@ -9558,7 +9558,7 @@ else
@end deftypefn
@deftypefn {Built-in Function} int __builtin_cpu_supports (const char *@var{feature})
This function returns a postive integer if the runtime cpu supports @var{feature}
This function returns a positive integer if the runtime cpu supports @var{feature}
and returns @code{0} otherwise. The following features can be detected:
@table @samp

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@ -305,9 +305,9 @@ systems' @command{tar} programs will also work, only try GNU
@item Perl version 5.6.1 (or later)
Necessary when targetting Darwin, building @samp{libstdc++},
Necessary when targeting Darwin, building @samp{libstdc++},
and not using @option{--disable-symvers}.
Necessary when targetting Solaris 2 with Sun @command{ld} and not using
Necessary when targeting Solaris 2 with Sun @command{ld} and not using
@option{--disable-symvers}. The bundled @command{perl} in Solaris@tie{}8
and up works.

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@ -15376,7 +15376,7 @@ Equivalent to @option{-march=mips64r2}.
@itemx -mno-mips16
@opindex mips16
@opindex mno-mips16
Generate (do not generate) MIPS16 code. If GCC is targetting a
Generate (do not generate) MIPS16 code. If GCC is targeting a
MIPS32 or MIPS64 architecture, it makes use of the MIPS16e ASE@.
MIPS16 code generation can also be controlled on a per-function basis
@ -16929,7 +16929,7 @@ Generate code that tries to avoid (not avoid) the use of indexed load
or store instructions. These instructions can incur a performance
penalty on Power6 processors in certain situations, such as when
stepping through large arrays that cross a 16M boundary. This option
is enabled by default when targetting Power6 and disabled otherwise.
is enabled by default when targeting Power6 and disabled otherwise.
@item -mfused-madd
@itemx -mno-fused-madd
@ -16948,7 +16948,7 @@ mapped to @option{-ffp-contract=off}.
@opindex mno-mulhw
Generate code that uses (does not use) the half-word multiply and
multiply-accumulate instructions on the IBM 405, 440, 464 and 476 processors.
These instructions are generated by default when targetting those
These instructions are generated by default when targeting those
processors.
@item -mdlmzb
@ -16957,7 +16957,7 @@ processors.
@opindex mno-dlmzb
Generate code that uses (does not use) the string-search @samp{dlmzb}
instruction on the IBM 405, 440, 464 and 476 processors. This instruction is
generated by default when targetting those processors.
generated by default when targeting those processors.
@item -mno-bit-align
@itemx -mbit-align
@ -18506,7 +18506,7 @@ Visual Instruction Set extensions. The default is @option{-mno-vis}.
@opindex mno-vis2
With @option{-mvis2}, GCC generates code that takes advantage of
version 2.0 of the UltraSPARC Visual Instruction Set extensions. The
default is @option{-mvis2} when targetting a cpu that supports such
default is @option{-mvis2} when targeting a cpu that supports such
instructions, such as UltraSPARC-III and later. Setting @option{-mvis2}
also sets @option{-mvis}.
@ -18516,7 +18516,7 @@ also sets @option{-mvis}.
@opindex mno-vis3
With @option{-mvis3}, GCC generates code that takes advantage of
version 3.0 of the UltraSPARC Visual Instruction Set extensions. The
default is @option{-mvis3} when targetting a cpu that supports such
default is @option{-mvis3} when targeting a cpu that supports such
instructions, such as niagara-3 and later. Setting @option{-mvis3}
also sets @option{-mvis2} and @option{-mvis}.
@ -18526,7 +18526,7 @@ also sets @option{-mvis2} and @option{-mvis}.
@opindex mno-popc
With @option{-mpopc}, GCC generates code that takes advantage of the UltraSPARC
population count instruction. The default is @option{-mpopc}
when targetting a cpu that supports such instructions, such as Niagara-2 and
when targeting a cpu that supports such instructions, such as Niagara-2 and
later.
@item -mfmaf
@ -18535,7 +18535,7 @@ later.
@opindex mno-fmaf
With @option{-mfmaf}, GCC generates code that takes advantage of the UltraSPARC
Fused Multiply-Add Floating-point extensions. The default is @option{-mfmaf}
when targetting a cpu that supports such instructions, such as Niagara-3 and
when targeting a cpu that supports such instructions, such as Niagara-3 and
later.
@item -mfix-at697f

View File

@ -5683,7 +5683,7 @@ built-in setjmp that isn't needed at the site of a nonlocal goto. You
will not normally need to define this pattern. A typical reason why you
might need this pattern is if some value, such as a pointer to a global
table, must be restored. It takes one argument, which is the label
to which builtin_longjmp transfered control; this pattern may be emitted
to which builtin_longjmp transferred control; this pattern may be emitted
at a small offset from that label.
@cindex @code{builtin_longjmp} instruction pattern

View File

@ -276,7 +276,7 @@ the start or end of the GCC garbage collection.
Some plugins may need to have GGC mark additional data. This can be
done by registering a callback (called with a null @code{gcc_data})
for the @code{PLUGIN_GGC_MARKING} event. Such callbacks can call the
@code{ggc_set_mark} routine, preferably thru the @code{ggc_mark} macro
@code{ggc_set_mark} routine, preferably through the @code{ggc_mark} macro
(and conversely, these routines should usually not be used in plugins
outside of the @code{PLUGIN_GGC_MARKING} event).

View File

@ -775,7 +775,7 @@ Read-only in this context means never modified during the lifetime of the
program, not necessarily in ROM or in write-disabled pages. A common
example of the later is a shared library's global offset table. This
table is initialized by the runtime loader, so the memory is technically
writable, but after control is transfered from the runtime loader to the
writable, but after control is transferred from the runtime loader to the
application, this memory will never be subsequently modified.
Stored in the @code{unchanging} field and printed as @samp{/u}.

View File

@ -95,7 +95,7 @@ along with GCC; see the file COPYING3. If not see
5) Delete the insns that the global analysis has indicated are
unnecessary.
6) Delete insns that store the same value as preceeding store
6) Delete insns that store the same value as preceding store
where the earlier store couldn't be eliminated.
7) Cleanup.
@ -388,7 +388,7 @@ struct insn_info
struct insn_info * prev_insn;
/* The linked list of insns that are in consideration for removal in
the forwards pass thru the basic block. This pointer may be
the forwards pass through the basic block. This pointer may be
trash as it is not cleared when a wild read occurs. The only
time it is guaranteed to be correct is when the traversal starts
at active_local_stores. */
@ -457,7 +457,7 @@ struct bb_info
being processed. While it contains info for all of the
registers, only the hard registers are actually examined. It is used
to assure that shift and/or add sequences that are inserted do not
accidently clobber live hard regs. */
accidentally clobber live hard regs. */
bitmap regs_live;
};

View File

@ -161,7 +161,7 @@ dw2_asm_output_vms_delta (int size ATTRIBUTE_UNUSED,
va_start (ap, comment);
#ifndef ASM_OUTPUT_DWARF_VMS_DELTA
/* VMS Delta is only special on ia64-vms, but this funtion also gets
/* VMS Delta is only special on ia64-vms, but this function also gets
called on alpha-vms so it has to do something sane. */
dw2_asm_output_delta (size, lab1, lab2, comment);
#else

View File

@ -4504,7 +4504,7 @@ adjust_piece_list (rtx *dest, rtx *src, rtx *inner,
if (copy)
{
/* First copy all nodes preceeding the current bitpos. */
/* First copy all nodes preceding the current bitpos. */
while (src != inner)
{
*dest = decl_piece_node (*decl_piece_varloc_ptr (*src),
@ -12686,7 +12686,7 @@ add_loc_descr_to_each (dw_loc_list_ref list, dw_loc_descr_ref ref)
/* Given two lists RET and LIST
produce location list that is result of adding expression in LIST
to expression in RET on each possition in program.
to expression in RET on each position in program.
Might be destructive on both RET and LIST.
TODO: We handle only simple cases of RET or LIST having at most one
@ -19989,7 +19989,7 @@ dwarf2out_source_line (unsigned int line, const char *filename,
/* Recall that this end-of-prologue indication is *not* the same thing
as the end_prologue debug hook. The NOTE_INSN_PROLOGUE_END note,
to which the hook corresponds, follows the last insn that was
emitted by gen_prologue. What we need is to preceed the first insn
emitted by gen_prologue. What we need is to precede the first insn
that had been emitted after NOTE_INSN_FUNCTION_BEG, i.e. the first
insn that corresponds to something the user wrote. These may be
very different locations once scheduling is enabled. */

View File

@ -46,7 +46,7 @@ enum eh_region_type
/* TRY regions implement catching an exception. The list of types associated
with the attached catch handlers is examined in order by the runtime and
control is transfered to the appropriate handler. Note that a NULL type
control is transferred to the appropriate handler. Note that a NULL type
list is a catch-all handler, and that it will catch *all* exceptions
including those originating from a different language. */
ERT_TRY,
@ -80,7 +80,7 @@ struct GTY(()) eh_landing_pad_d
/* The region with which this landing pad is associated. */
struct eh_region_d *region;
/* At the gimple level, the location to which control will be transfered
/* At the gimple level, the location to which control will be transferred
for this landing pad. There can be both EH and normal edges into the
block containing the post-landing-pad label. */
tree post_landing_pad;

View File

@ -7374,7 +7374,7 @@ highest_pow2_factor_for_target (const_tree target, const_tree exp)
}
#ifdef HAVE_conditional_move
/* Convert the tree comparision code TCODE to the rtl one where the
/* Convert the tree comparison code TCODE to the rtl one where the
signedness is UNSIGNEDP. */
static enum rtx_code

View File

@ -2567,7 +2567,7 @@ operand_equal_p (const_tree arg0, const_tree arg1, unsigned int flags)
return OP_SAME (0);
case TARGET_MEM_REF:
/* Require equal extra operands and then fall thru to MEM_REF
/* Require equal extra operands and then fall through to MEM_REF
handling of the two common operands. */
if (!OP_SAME_WITH_NULL (2)
|| !OP_SAME_WITH_NULL (3)
@ -12018,7 +12018,7 @@ fold_binary_loc (location_t loc,
}
}
/* Fall thru */
/* Fall through */
case FLOOR_DIV_EXPR:
/* Simplify A / (B << N) where A and B are positive and B is
@ -12061,7 +12061,7 @@ fold_binary_loc (location_t loc,
&& code == FLOOR_DIV_EXPR)
return fold_build2_loc (loc, TRUNC_DIV_EXPR, type, op0, op1);
/* Fall thru */
/* Fall through */
case ROUND_DIV_EXPR:
case CEIL_DIV_EXPR:

View File

@ -8071,7 +8071,7 @@ include_spec_function (int argc, const char **argv)
}
/* %:find-file spec function. This function replaces its argument by
the file found thru find_file, that is the -print-file-name gcc
the file found through find_file, that is the -print-file-name gcc
program option. */
static const char *
find_file_spec_function (int argc, const char **argv)
@ -8087,7 +8087,7 @@ find_file_spec_function (int argc, const char **argv)
/* %:find-plugindir spec function. This function replaces its argument
by the -iplugindir=<dir> option. `dir' is found thru find_file, that
by the -iplugindir=<dir> option. `dir' is found through find_file, that
is the -print-file-name gcc program option. */
static const char *
find_plugindir_spec_function (int argc, const char **argv ATTRIBUTE_UNUSED)

View File

@ -2906,7 +2906,7 @@ hoist_expr_reaches_here_p (basic_block expr_bb, int expr_index, basic_block bb,
return (pred == NULL);
}
/* Find occurence in BB. */
/* Find occurrence in BB. */
static struct occr *
find_occr_in_bb (struct occr *occr, basic_block bb)
@ -2990,11 +2990,11 @@ hoist_code (void)
{
/* Current expression. */
struct expr *expr = index_map[i];
/* Number of occurences of EXPR that can be hoisted to BB. */
/* Number of occurrences of EXPR that can be hoisted to BB. */
int hoistable = 0;
/* Basic blocks that have occurences reachable from BB. */
/* Basic blocks that have occurrences reachable from BB. */
bitmap_head _from_bbs, *from_bbs = &_from_bbs;
/* Occurences reachable from BB. */
/* Occurrences reachable from BB. */
VEC (occr_t, heap) *occrs_to_hoist = NULL;
/* We want to insert the expression into BB only once, so
note when we've inserted it. */
@ -3004,14 +3004,14 @@ hoist_code (void)
bitmap_initialize (from_bbs, 0);
/* If an expression is computed in BB and is available at end of
BB, hoist all occurences dominated by BB to BB. */
BB, hoist all occurrences dominated by BB to BB. */
if (TEST_BIT (comp[bb->index], i))
{
occr = find_occr_in_bb (expr->antic_occr, bb);
if (occr)
{
/* An occurence might've been already deleted
/* An occurrence might've been already deleted
while processing a dominator of BB. */
if (!occr->deleted_p)
{
@ -3042,7 +3042,7 @@ hoist_code (void)
occr = find_occr_in_bb (expr->antic_occr, dominated);
gcc_assert (occr);
/* An occurence might've been already deleted
/* An occurrence might've been already deleted
while processing a dominator of BB. */
if (occr->deleted_p)
continue;
@ -3084,7 +3084,7 @@ hoist_code (void)
if (hoistable > 1 && dbg_cnt (hoist_insn))
{
/* If (hoistable != VEC_length), then there is
an occurence of EXPR in BB itself. Don't waste
an occurrence of EXPR in BB itself. Don't waste
time looking for LCA in this case. */
if ((unsigned) hoistable
== VEC_length (occr_t, occrs_to_hoist))
@ -3094,7 +3094,7 @@ hoist_code (void)
lca = nearest_common_dominator_for_set (CDI_DOMINATORS,
from_bbs);
if (lca != bb)
/* Punt, it's better to hoist these occurences to
/* Punt, it's better to hoist these occurrences to
LCA. */
VEC_free (occr_t, heap, occrs_to_hoist);
}
@ -3105,7 +3105,7 @@ hoist_code (void)
insn_inserted_p = 0;
/* Walk through occurences of I'th expressions we want
/* Walk through occurrences of I'th expressions we want
to hoist to BB and make the transformations. */
FOR_EACH_VEC_ELT (occr_t, occrs_to_hoist, j, occr)
{

View File

@ -2390,7 +2390,7 @@ add_presence_absence (unit_set_el_t dest_list,
/* The function inserts BYPASS in the list of bypasses of the
corresponding output insn. The order of bypasses in the list is
decribed in a comment for member `bypass_list' (see above). If
described in a comment for member `bypass_list' (see above). If
there is already the same bypass in the list the function reports
this and does nothing. */
static void

View File

@ -65,7 +65,7 @@ type_lineloc (const_type_p ty)
}
/* The state file has simplistic lispy lexical tokens. Its lexer gives
a linked list of struct state_token_st, thru the peek_state_token
a linked list of struct state_token_st, through the peek_state_token
function. Lexical tokens are consumed with next_state_tokens. */
@ -818,7 +818,7 @@ write_state_lang_struct_type (type_p current)
type_p hty = NULL;
const char *homoname = 0;
write_state_struct_union_type (current, "lang_struct");
/* lang_struct-ures are particularily tricky, since their
/* lang_struct-ures are particularly tricky, since their
u.s.lang_struct field gives a list of homonymous struct-s or
union-s! */
DBGPRINTF ("lang_struct @ %p #%d", (void *) current, current->state_number);

View File

@ -159,7 +159,7 @@ static outf_p *base_files;
#if ENABLE_CHECKING
/* Utility debugging function, printing the various type counts within
a list of types. Called thru the DBGPRINT_COUNT_TYPE macro. */
a list of types. Called through the DBGPRINT_COUNT_TYPE macro. */
void
dbgprint_count_type_at (const char *fil, int lin, const char *msg, type_p t)
{
@ -1828,7 +1828,7 @@ struct file_rule_st files_rules[] = {
/* Source *.c files are using get_file_gtfilename to compute their
output_name and get_file_basename to compute their for_name
thru the source_dot_c_frul action. */
through the source_dot_c_frul action. */
{ DIR_PREFIX_REGEX "([[:alnum:]_-]*)\\.c$",
REG_EXTENDED, NULL_REGEX, "gt-$3.h", "$3.c", source_dot_c_frul},
/* Common header files get "gtype-desc.c" as their output_name,
@ -2004,7 +2004,7 @@ get_output_file_with_visibility (input_file *inpf)
/* Try each rule in sequence in files_rules until one is triggered. */
{
int rulix = 0;
DBGPRINTF ("passing input file @ %p named %s thru the files_rules",
DBGPRINTF ("passing input file @ %p named %s through the files_rules",
(void*) inpf, inpfname);
for (; files_rules[rulix].frul_srcexpr != NULL; rulix++)

View File

@ -91,7 +91,7 @@ s_hook_eq_p (const void *p1, const void *p2)
}
/* Read the documentation file with name IN_FNAME, perform substitutions
to incorporate informtion from hook_array, and emit the result on stdout.
to incorporate information from hook_array, and emit the result on stdout.
Hooks defined with DEFHOOK / DEFHOOKPOD are emitted at the place of a
matching @hook in the input file; if there is no matching @hook, the
hook is emitted after the hook that precedes it in target.def .

View File

@ -94,7 +94,7 @@ can_refer_decl_in_current_unit_p (tree decl, tree from_decl)
produced.
As observed in PR20991 for already optimized out comdat virtual functions
it may be tempting to not neccesarily give up because the copy will be
it may be tempting to not necessarily give up because the copy will be
output elsewhere when corresponding vtable is output.
This is however not possible - ABI specify that COMDATs are output in
units where they are used and when the other unit was compiled with LTO
@ -1054,7 +1054,7 @@ gimple_extract_devirt_binfo_from_cst (tree cst)
type = TREE_TYPE (fld);
offset -= pos;
}
/* Artifical sub-objects are ancestors, we do not want to use them for
/* Artificial sub-objects are ancestors, we do not want to use them for
devirtualization, at least not here. */
if (last_artificial)
return NULL_TREE;

View File

@ -156,7 +156,7 @@ debug_gimple_seq (gimple_seq seq)
/* A simple helper to pretty-print some of the gimple tuples in the printf
style. The format modifiers are preceeded by '%' and are:
style. The format modifiers are preceded by '%' and are:
'G' - outputs a string corresponding to the code of the given gimple,
'S' - outputs a gimple_seq with indent of spc + 2,
'T' - outputs the tree t,

View File

@ -3333,7 +3333,7 @@ gtc_visit (tree t1, tree t2,
|| FIXED_POINT_TYPE_P (t1))
return true;
/* For other types fall thru to more complex checks. */
/* For other types fall through to more complex checks. */
}
/* If the types have been previously registered and found equal
@ -3755,7 +3755,7 @@ gimple_types_compatible_p (tree t1, tree t2)
|| FIXED_POINT_TYPE_P (t1))
return true;
/* For other types fall thru to more complex checks. */
/* For other types fall through to more complex checks. */
}
/* If the types have been previously registered and found equal

View File

@ -4800,7 +4800,7 @@ gimple_return_set_retval (gimple gs, tree retval)
}
/* Returns true when the gimple statment STMT is any of the OpenMP types. */
/* Returns true when the gimple statement STMT is any of the OpenMP types. */
#define CASE_GIMPLE_OMP \
case GIMPLE_OMP_PARALLEL: \

View File

@ -2811,7 +2811,7 @@ shortcut_cond_r (tree pred, tree *true_label_p, tree *false_label_p,
/* Given a conditional expression EXPR with short-circuit boolean
predicates using TRUTH_ANDIF_EXPR or TRUTH_ORIF_EXPR, break the
predicate appart into the equivalent sequence of conditionals. */
predicate apart into the equivalent sequence of conditionals. */
static tree
shortcut_cond_expr (tree expr)

View File

@ -144,7 +144,7 @@ build_partial_difference (ppl_Pointset_Powerset_C_Polyhedron_t *p,
This means that all the time dimensions are equal except for
time_depth, where the constraint is t_{depth} = t'_{depth} + 1
step. More to this: we should be carefull not to add equalities
step. More to this: we should be careful not to add equalities
to the 'coupled' dimensions, which happens when the one dimension
is stripmined dimension, and the other dimension corresponds
to the point loop inside stripmined dimension. */

View File

@ -1223,7 +1223,7 @@ add_condition_to_domain (ppl_Pointset_Powerset_C_Polyhedron_t ps, gimple stmt,
ppl_delete_Linear_Expression (right);
}
/* Add conditional statement STMT to pbb. CODE is used as the comparision
/* Add conditional statement STMT to pbb. CODE is used as the comparison
operator. This allows us to invert the condition or to handle
inequalities. */
@ -2840,7 +2840,7 @@ follow_inital_value_to_phi (tree arg, tree lhs)
}
/* Return the argument of the loop PHI that is the inital value coming
/* Return the argument of the loop PHI that is the initial value coming
from outside the loop. */
static edge
@ -2860,7 +2860,7 @@ edge_initial_value_for_loop_phi (gimple phi)
return NULL;
}
/* Return the argument of the loop PHI that is the inital value coming
/* Return the argument of the loop PHI that is the initial value coming
from outside the loop. */
static tree

View File

@ -3877,7 +3877,7 @@ find_if_case_1 (basic_block test_bb, edge then_edge, edge else_edge)
/* We can avoid creating a new basic block if then_bb is immediately
followed by else_bb, i.e. deleting then_bb allows test_bb to fall
thru to else_bb. */
through to else_bb. */
if (then_bb->next_bb == else_bb
&& then_bb->prev_bb == test_bb

View File

@ -155,7 +155,7 @@ expand_location_to_spelling_point (source_location loc)
return expand_location_1 (loc, /*expansion_piont_p=*/false);
}
/* If LOCATION is in a sytem header and if it's a virtual location for
/* If LOCATION is in a system header and if it's a virtual location for
a token coming from the expansion of a macro M, unwind it to the
location of the expansion point of M. Otherwise, just return
LOCATION.

View File

@ -82,7 +82,7 @@ along with GCC; see the file COPYING3. If not see
for each strongly connected component (SCC), we propagate constants
according to previously computed jump functions. We also record what known
values depend on other known values and estimate local effects. Finally, we
propagate cumulative information about these effects from dependant values
propagate cumulative information about these effects from dependent values
to those on which they depend.
Second, we again traverse the call graph in the same topological order and
@ -1588,7 +1588,7 @@ safe_add (int a, int b)
/* Propagate the estimated effects of individual values along the topological
from the dependant values to those they depend on. */
from the dependent values to those they depend on. */
static void
propagate_effects (void)

View File

@ -2010,7 +2010,7 @@ estimate_function_body_sizes (struct cgraph_node *node, bool early)
p = true_predicate ();
/* We account everything but the calls. Calls have their own
size/time info attached to cgraph edges. This is neccesary
size/time info attached to cgraph edges. This is necessary
in order to make the cost disappear after inlining. */
if (!is_gimple_call (stmt))
{

View File

@ -264,7 +264,7 @@ inline_call (struct cgraph_edge *e, bool update_original,
This is done before inline plan is applied to NODE when there are
still some inline clones if it.
This is neccesary because inline decisions are not really transitive
This is necessary because inline decisions are not really transitive
and the other inline clones may have different bodies. */
static struct cgraph_node *

View File

@ -777,7 +777,7 @@ edge_badness (struct cgraph_edge *edge, bool dump)
edge_growth
badness = -goodness
The fraction is upside down, becuase on edge counts and time beneits
The fraction is upside down, because on edge counts and time beneits
the bounds are known. Edge growth is essentially unlimited. */
else if (max_count)
@ -1369,7 +1369,7 @@ inline_small_functions (void)
continue;
/* Be sure that caches are maintained consistent.
We can not make this ENABLE_CHECKING only because it cause differnt
We can not make this ENABLE_CHECKING only because it cause different
updates of the fibheap queue. */
cached_badness = edge_badness (edge, false);
reset_edge_growth_cache (edge);

View File

@ -1109,7 +1109,7 @@ propagate_pure_const (void)
ipa_print_order(dump_file, "reduced", order, order_pos);
}
/* Propagate the local information thru the call graph to produce
/* Propagate the local information through the call graph to produce
the global information. All the nodes within a cycle will have
the same info so we collapse cycles first. Then we can do the
propagation in one pass from the leaves to the roots. */
@ -1381,7 +1381,7 @@ propagate_nothrow (void)
ipa_print_order (dump_file, "reduced for nothrow", order, order_pos);
}
/* Propagate the local information thru the call graph to produce
/* Propagate the local information through the call graph to produce
the global information. All the nodes within a cycle will have
the same info so we collapse cycles first. Then we can do the
propagation in one pass from the leaves to the roots. */

View File

@ -58,7 +58,7 @@ struct GTY(()) ipa_ref_list
{
/* Store actual references in references vector. */
VEC(ipa_ref_t,gc) *references;
/* Refering is vector of pointers to references. It must not live in GGC space
/* Referring is vector of pointers to references. It must not live in GGC space
or GGC will try to mark middle of references vectors. */
VEC(ipa_ref_ptr,heap) * GTY((skip)) referring;
};

View File

@ -615,7 +615,7 @@ propagate (void)
ipa_discover_readonly_nonaddressable_vars ();
generate_summary ();
/* Now we know what vars are realy statics; prune out those that aren't. */
/* Now we know what vars are really statics; prune out those that aren't. */
FOR_EACH_VARIABLE (vnode)
if (vnode->symbol.externally_visible
|| TREE_ADDRESSABLE (vnode->symbol.decl)
@ -637,7 +637,7 @@ propagate (void)
bitmap_and_into (node_l->statics_written, all_module_statics);
}
/* Propagate the local information thru the call graph to produce
/* Propagate the local information through the call graph to produce
the global information. All the nodes within a cycle will have
the same info so we collapse cycles first. Then we can do the
propagation in one pass from the leaves to the roots. */

View File

@ -325,7 +325,7 @@ ipa_reverse_postorder (struct cgraph_node **order)
/* Given a memory reference T, will return the variable at the bottom
of the access. Unlike get_base_address, this will recurse thru
of the access. Unlike get_base_address, this will recurse through
INDIRECT_REFS. */
tree

View File

@ -683,7 +683,7 @@ varpool_externally_visible_p (struct varpool_node *vnode, bool aliased)
if (vnode->symbol.resolution == LDPR_PREVAILING_DEF_IRONLY)
return false;
/* As a special case, the COMDAT virutal tables can be unshared.
/* As a special case, the COMDAT virtual tables can be unshared.
In LTO mode turn vtables into static variables. The variable is readonly,
so this does not enable more optimization, but referring static var
is faster for dynamic linking. Also this match logic hidding vtables
@ -791,7 +791,7 @@ function_and_variable_visibility (bool whole_program)
/* C++ FE on lack of COMDAT support create local COMDAT functions
(that ought to be shared but can not due to object format
limitations). It is neccesary to keep the flag to make rest of C++ FE
limitations). It is necessary to keep the flag to make rest of C++ FE
happy. Clear the flag here to avoid confusion in middle-end. */
if (DECL_COMDAT (node->symbol.decl) && !TREE_PUBLIC (node->symbol.decl))
DECL_COMDAT (node->symbol.decl) = 0;
@ -974,7 +974,7 @@ gate_whole_program_function_and_variable_visibility (void)
return !flag_ltrans;
}
/* Bring functionss local at LTO time whith -fwhole-program. */
/* Bring functionss local at LTO time with -fwhole-program. */
static unsigned int
whole_program_function_and_variable_visibility (void)
@ -1350,7 +1350,7 @@ build_cdtor_fns (void)
/* Look for constructors and destructors and produce function calling them.
This is needed for targets not supporting ctors or dtors, but we perform the
transformation also at linktime to merge possibly numberous
transformation also at linktime to merge possibly numerous
constructors/destructors into single function to improve code locality and
reduce size. */

View File

@ -160,7 +160,7 @@ create_new_allocno (int regno, ira_loop_tree_node_t loop_tree_node)
typedef struct move *move_t;
/* The structure represents an allocno move. Both allocnos have the
same origional regno but different allocation. */
same original regno but different allocation. */
struct move
{
/* The allocnos involved in the move. */
@ -446,7 +446,7 @@ setup_entered_from_non_parent_p (void)
}
/* Return TRUE if move of SRC_ALLOCNO (assigned to hard register) to
DEST_ALLOCNO (assigned to memory) can be removed beacuse it does
DEST_ALLOCNO (assigned to memory) can be removed because it does
not change value of the destination. One possible reason for this
is the situation when SRC_ALLOCNO is not modified in the
corresponding loop. */

View File

@ -528,7 +528,7 @@ mark_ref_dead (df_ref def)
/* If REG is a pseudo or a subreg of it, and the class of its allocno
intersects CL, make a conflict with pseudo DREG. ORIG_DREG is the
rtx actually accessed, it may be indentical to DREG or a subreg of it.
rtx actually accessed, it may be identical to DREG or a subreg of it.
Advance the current program point before making the conflict if
ADVANCE_P. Return TRUE if we will need to advance the current
program point. */
@ -562,7 +562,7 @@ make_pseudo_conflict (rtx reg, enum reg_class cl, rtx dreg, rtx orig_dreg,
/* Check and make if necessary conflicts for pseudo DREG of class
DEF_CL of the current insn with input operand USE of class USE_CL.
ORIG_DREG is the rtx actually accessed, it may be indentical to
ORIG_DREG is the rtx actually accessed, it may be identical to
DREG or a subreg of it. Advance the current program point before
making the conflict if ADVANCE_P. Return TRUE if we will need to
advance the current program point. */

View File

@ -39,7 +39,7 @@ along with GCC; see the file COPYING3. If not see
/* Statistics gathered during LTO, WPA and LTRANS. */
struct lto_stats_d lto_stats;
/* LTO uses bitmaps with different life-times. So use a seperate
/* LTO uses bitmaps with different life-times. So use a separate
obstack for all LTO bitmaps. */
static bitmap_obstack lto_obstack;
static bool lto_obstack_initialized;

View File

@ -300,7 +300,7 @@ typedef const char* (lto_get_section_data_f) (struct lto_file_decl_data *,
/* Return the data found from the above call. The first three
parameters are the same as above. The fourth parameter is the data
itself and the fifth is the lenght of the data. */
itself and the fifth is the length of the data. */
typedef void (lto_free_section_data_f) (struct lto_file_decl_data *,
enum lto_section_type,
const char *,
@ -987,7 +987,7 @@ lto_init_tree_ref_encoder (struct lto_tree_ref_encoder *encoder,
}
/* Destory an lto_tree_ref_encoder ENCODER by freeing its contents. The
/* Destroy an lto_tree_ref_encoder ENCODER by freeing its contents. The
memory used by ENCODER is not freed by this function. */
static inline void
lto_destroy_tree_ref_encoder (struct lto_tree_ref_encoder *encoder)

View File

@ -727,7 +727,7 @@ run_gcc (unsigned argc, char *argv[])
obstack_ptr_grow (&argv_obstack, "-fwpa");
}
/* Append the input objects and possible preceeding arguments. */
/* Append the input objects and possible preceding arguments. */
for (i = 1; i < argc; ++i)
obstack_ptr_grow (&argv_obstack, argv[i]);
obstack_ptr_grow (&argv_obstack, NULL);

View File

@ -1385,7 +1385,7 @@ sum_edge_counts (VEC (edge, gc) *to_edges)
}
/* Main routine. Smoothes the intial assigned basic block and edge counts using
/* Main routine. Smoothes the initial assigned basic block and edge counts using
a minimum cost flow algorithm, to ensure that the flow consistency rule is
obeyed: sum of outgoing edges = sum of incoming edges for each basic
block. */

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