Strengthen memory order for atomic<T>::wait/notify
This matches the memory order in libc++. libstdc++-v3/ChangeLog: * include/bits/atomic_wait.h: Change memory order from Acquire/Release with relaxed loads to SeqCst+Release for accesses to the waiter's count.
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@ -209,18 +209,18 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
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void
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_M_enter_wait() noexcept
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{ __atomic_fetch_add(&_M_wait, 1, __ATOMIC_ACQ_REL); }
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{ __atomic_fetch_add(&_M_wait, 1, __ATOMIC_SEQ_CST); }
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void
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_M_leave_wait() noexcept
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{ __atomic_fetch_sub(&_M_wait, 1, __ATOMIC_ACQ_REL); }
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{ __atomic_fetch_sub(&_M_wait, 1, __ATOMIC_RELEASE); }
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bool
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_M_waiting() const noexcept
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{
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__platform_wait_t __res;
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__atomic_load(&_M_wait, &__res, __ATOMIC_ACQUIRE);
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return __res > 0;
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__atomic_load(&_M_wait, &__res, __ATOMIC_SEQ_CST);
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return __res != 0;
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}
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void
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@ -258,7 +258,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
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__platform_wait(__addr, __old);
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#else
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__platform_wait_t __val;
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__atomic_load(__addr, &__val, __ATOMIC_RELAXED);
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__atomic_load(__addr, &__val, __ATOMIC_SEQ_CST);
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if (__val == __old)
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{
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lock_guard<mutex> __l(_M_mtx);
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@ -309,7 +309,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
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{
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if (_M_laundered())
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{
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__atomic_fetch_add(_M_addr, 1, __ATOMIC_ACQ_REL);
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__atomic_fetch_add(_M_addr, 1, __ATOMIC_SEQ_CST);
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__all = true;
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}
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_M_w._M_notify(_M_addr, __all, __bare);
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