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rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.

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gcc/ChangeLog

	    2020-08-19  Carl Love  <cel@us.ibm.com>
	* config/rs6000/rs6000-builtin.def (BU_P10V_0, BU_P10V_1,
	BU_P10V_2, BU_P10V_3): Rename BU_P10V_VSX_0, BU_P10V_VSX_1,
	BU_P10V_VSX_2, BU_P10V_VSX_3 respectively.
	(BU_P10V_4): Remove.
	(BU_P10V_AV_0, BU_P10V_AV_1, BU_P10V_AV_2, BU_P10V_AV_3, BU_P10V_AV_4):
	New definitions for Power 10 Altivec macros.
	(VSTRIBR, VSTRIHR, VSTRIBL, VSTRIHL, VSTRIBR_P, VSTRIHR_P,
	VSTRIBL_P, VSTRIHL_P, MTVSRBM, MTVSRHM, MTVSRWM, MTVSRDM, MTVSRQM,
	VEXPANDMB, VEXPANDMH, VEXPANDMW, VEXPANDMD, VEXPANDMQ, VEXTRACTMB,
	VEXTRACTMH, VEXTRACTMW, VEXTRACTMD, VEXTRACTMQ): Replace macro
	expansion BU_P10V_1 with BU_P10V_AV_1.
	(VCLRLB, VCLRRB, VCFUGED, VCLZDM, VCTZDM, VPDEPD, VPEXTD, VGNB,
	VCNTMBB, VCNTMBH, VCNTMBW, VCNTMBD): Replace macro expansion
	BU_P10V_2 with	BU_P10V_AV_2.
	(VEXTRACTBL, VEXTRACTHL, VEXTRACTWL, VEXTRACTDL, VEXTRACTBR, VEXTRACTHR,
	VEXTRACTWR, VEXTRACTDR, VINSERTGPRBL, VINSERTGPRHL, VINSERTGPRWL,
	VINSERTGPRDL, VINSERTVPRBL, VINSERTVPRHL, VINSERTVPRWL, VINSERTGPRBR,
	VINSERTGPRHR, VINSERTGPRWR, VINSERTGPRDR, VINSERTVPRBR, VINSERTVPRHR,
	VINSERTVPRWR, VREPLACE_ELT_V4SI, VREPLACE_ELT_UV4SI, VREPLACE_ELT_V2DF,
	VREPLACE_ELT_V4SF, VREPLACE_ELT_V2DI, VREPLACE_ELT_UV2DI, VREPLACE_UN_V4SI,
	VREPLACE_UN_UV4SI, VREPLACE_UN_V4SF, VREPLACE_UN_V2DI, VREPLACE_UN_UV2DI,
	VREPLACE_UN_V2DF, VSLDB_V16QI, VSLDB_V8HI, VSLDB_V4SI, VSLDB_V2DI,
	VSRDB_V16QI, VSRDB_V8HI, VSRDB_V4SI, VSRDB_V2DI): Replace macro expansion
	BU_P10V_3 with BU_P10V_AV_3.
	(VXXSPLTIW_V4SI, VXXSPLTIW_V4SF, VXXSPLTID): Replace macro expansion
	BU_P10V_1 with BU_P10V_AV_1.
	(XXGENPCVM_V16QI, XXGENPCVM_V8HI, XXGENPCVM_V4SI, XXGENPCVM_V2DI):
	Replace macro expansion BU_P10V_2 with BU_P10V_VSX_2.
	(VXXSPLTI32DX_V4SI, VXXSPLTI32DX_V4SF, VXXBLEND_V16QI, VXXBLEND_V8HI,
	VXXBLEND_V4SI, VXXBLEND_V2DI, VXXBLEND_V4SF, VXXBLEND_V2DF): Replace macor
	expansion BU_P10V_3 with BU_P10V_VSX_3.
	(XXEVAL, VXXPERMX): Replace macro expansion BU_P10V_4 with BU_P10V_VSX_4.
	(XVCVBF16SP, XVCVSPBF16): Replace macro expansion BU_VSX_1 with
	BU_P10V_VSX_1. Also change MISC to CONST.
	* config/rs6000/rs6000-c.c: (P10_BUILTIN_VXXPERMX): Replace with
	P10V_BUILTIN_VXXPERMX.
	(P10_BUILTIN_VCLRLB, P10_BUILTIN_VCLRLB, P10_BUILTIN_VCLRRB,
	P10_BUILTIN_VGNB, P10_BUILTIN_XXEVAL, P10_BUILTIN_VXXPERMX,
	P10_BUILTIN_VEXTRACTBL, P10_BUILTIN_VEXTRACTHL, P10_BUILTIN_VEXTRACTWL,
	P10_BUILTIN_VEXTRACTDL, P10_BUILTIN_VINSERTGPRHL,
	P10_BUILTIN_VINSERTGPRWL, P10_BUILTIN_VINSERTGPRDL,
	P10_BUILTIN_VINSERTVPRBL, P10_BUILTIN_VINSERTVPRHL,
	P10_BUILTIN_VEXTRACTBR, P10_BUILTIN_VEXTRACTHR,
	P10_BUILTIN_VEXTRACTWR, P10_BUILTIN_VEXTRACTDR,
	P10_BUILTIN_VINSERTGPRBR, P10_BUILTIN_VINSERTGPRHR,
	P10_BUILTIN_VINSERTGPRWR, P10_BUILTIN_VINSERTGPRDR,
	P10_BUILTIN_VINSERTVPRBR, P10_BUILTIN_VINSERTVPRHR,
	P10_BUILTIN_VINSERTVPRWR, P10_BUILTIN_VREPLACE_ELT_UV4SI,
	P10_BUILTIN_VREPLACE_ELT_V4SI, P10_BUILTIN_VREPLACE_ELT_UV2DI,
	P10_BUILTIN_VREPLACE_ELT_V2DI, P10_BUILTIN_VREPLACE_ELT_V2DF,
	P10_BUILTIN_VREPLACE_UN_UV4SI, P10_BUILTIN_VREPLACE_UN_V4SI,
	P10_BUILTIN_VREPLACE_UN_V4SF, P10_BUILTIN_VREPLACE_UN_UV2DI,
	P10_BUILTIN_VREPLACE_UN_V2DI, P10_BUILTIN_VREPLACE_UN_V2DF,
	P10_BUILTIN_VSLDB_V16QI, P10_BUILTIN_VSLDB_V16QI,
	P10_BUILTIN_VSLDB_V8HI, P10_BUILTIN_VSLDB_V4SI,
	P10_BUILTIN_VSLDB_V2DI, P10_BUILTIN_VXXSPLTIW_V4SI,
	P10_BUILTIN_VXXSPLTIW_V4SF, P10_BUILTIN_VXXSPLTID,
	P10_BUILTIN_VXXSPLTI32DX_V4SI, P10_BUILTIN_VXXSPLTI32DX_V4SF,
	P10_BUILTIN_VXXBLEND_V16QI, P10_BUILTIN_VXXBLEND_V8HI,
	P10_BUILTIN_VXXBLEND_V4SI, P10_BUILTIN_VXXBLEND_V2DI,
	P10_BUILTIN_VXXBLEND_V4SF, P10_BUILTIN_VXXBLEND_V2DF,
	P10_BUILTIN_VSRDB_V16QI, P10_BUILTIN_VSRDB_V8HI,
	P10_BUILTIN_VSRDB_V4SI, P10_BUILTIN_VSRDB_V2DI,
	P10_BUILTIN_VSTRIBL, P10_BUILTIN_VSTRIHL,
	P10_BUILTIN_VSTRIBL_P, P10_BUILTIN_VSTRIHL_P,
	P10_BUILTIN_VSTRIBR, P10_BUILTIN_VSTRIHR,
	P10_BUILTIN_VSTRIBR_P, P10_BUILTIN_VSTRIHR_P,
	P10_BUILTIN_MTVSRBM, P10_BUILTIN_MTVSRHM,
	P10_BUILTIN_MTVSRWM, P10_BUILTIN_MTVSRDM,
	P10_BUILTIN_MTVSRQM, P10_BUILTIN_VCNTMBB,
	P10_BUILTIN_VCNTMBH, P10_BUILTIN_VCNTMBW,
	P10_BUILTIN_VCNTMBD, P10_BUILTIN_VEXPANDMB,
	P10_BUILTIN_VEXPANDMH, P10_BUILTIN_VEXPANDMW,
	P10_BUILTIN_VEXPANDMD, P10_BUILTIN_VEXPANDMQ,
	P10_BUILTIN_VEXTRACTMB, P10_BUILTIN_VEXTRACTMH,
	P10_BUILTIN_VEXTRACTMW, P10_BUILTIN_VEXTRACTMD,
	P10_BUILTIN_VEXTRACTMQ, P10_BUILTIN_XVTLSBB_ZEROS,
	P10_BUILTIN_XVTLSBB_ONES): Replace with
	P10V_BUILTIN_VCLRLB, P10V_BUILTIN_VCLRLB, P10V_BUILTIN_VCLRRB,
	P10V_BUILTIN_VGNB, P10V_BUILTIN_XXEVAL, P10V_BUILTIN_VXXPERMX,
	P10V_BUILTIN_VEXTRACTBL, P10V_BUILTIN_VEXTRACTHL, P10V_BUILTIN_VEXTRACTWL,
	P10V_BUILTIN_VEXTRACTDL, P10V_BUILTIN_VINSERTGPRHL,
	P10V_BUILTIN_VINSERTGPRWL, P10V_BUILTIN_VINSERTGPRDL,
	P10V_BUILTIN_VINSERTVPRBL,P10V_BUILTIN_VINSERTVPRHL,
	P10V_BUILTIN_VEXTRACTBR, P10V_BUILTIN_VEXTRACTHR
	P10V_BUILTIN_VEXTRACTWR, P10V_BUILTIN_VEXTRACTDR,
	P10V_BUILTIN_VINSERTGPRBR, P10V_BUILTIN_VINSERTGPRHR,
	P10V_BUILTIN_VINSERTGPRWR, P10V_BUILTIN_VINSERTGPRDR,
	P10V_BUILTIN_VINSERTVPRBR, P10V_BUILTIN_VINSERTVPRHR,
	P10V_BUILTIN_VINSERTVPRWR, P10V_BUILTIN_VREPLACE_ELT_UV4SI,
	P10V_BUILTIN_VREPLACE_ELT_V4SI, P10V_BUILTIN_VREPLACE_ELT_UV2DI,
	P10V_BUILTIN_VREPLACE_ELT_V2DI, P10V_BUILTIN_VREPLACE_ELT_V2DF,
	P10V_BUILTIN_VREPLACE_UN_UV4SI, P10V_BUILTIN_VREPLACE_UN_V4SI,
	P10V_BUILTIN_VREPLACE_UN_V4SF, P10V_BUILTIN_VREPLACE_UN_UV2DI,
	P10V_BUILTIN_VREPLACE_UN_V2DI, P10V_BUILTIN_VREPLACE_UN_V2DF,
	P10V_BUILTIN_VSLDB_V16QI, P10V_BUILTIN_VSLDB_V16QI,
	P10V_BUILTIN_VSLDB_V8HI, P10V_BUILTIN_VSLDB_V4SI,
	P10V_BUILTIN_VSLDB_V2DI, P10V_BUILTIN_VXXSPLTIW_V4SI,
	P10V_BUILTIN_VXXSPLTIW_V4SF, P10V_BUILTIN_VXXSPLTID,
	P10V_BUILTIN_VXXSPLTI32DX_V4SI, P10V_BUILTIN_VXXSPLTI32DX_V4SF,
	P10V_BUILTIN_VXXBLEND_V16QI, P10V_BUILTIN_VXXBLEND_V8HI,
	P10V_BUILTIN_VXXBLEND_V4SI, P10V_BUILTIN_VXXBLEND_V2DI,
	P10V_BUILTIN_VXXBLEND_V4SF, P10V_BUILTIN_VXXBLEND_V2DF,
	P10V_BUILTIN_VSRDB_V16QI, P10V_BUILTIN_VSRDB_V8HI,
	P10V_BUILTIN_VSRDB_V4SI, P10V_BUILTIN_VSRDB_V2DI,
	P10V_BUILTIN_VSTRIBL, P10V_BUILTIN_VSTRIHL,
	P10V_BUILTIN_VSTRIBL_P, P10V_BUILTIN_VSTRIHL_P,
	P10V_BUILTIN_VSTRIBR, P10V_BUILTIN_VSTRIHR,
	P10V_BUILTIN_VSTRIBR_P, P10V_BUILTIN_VSTRIHR_P,
	P10V_BUILTIN_MTVSRBM, P10V_BUILTIN_MTVSRHM,
	P10V_BUILTIN_MTVSRWM, P10V_BUILTIN_MTVSRDM,
	P10V_BUILTIN_MTVSRQM, P10V_BUILTIN_VCNTMBB,
	P10V_BUILTIN_VCNTMBH, P10V_BUILTIN_VCNTMBW,
	P10V_BUILTIN_VCNTMBD, P10V_BUILTIN_VEXPANDMB,
	P10V_BUILTIN_VEXPANDMH, P10V_BUILTIN_VEXPANDMW,
	P10V_BUILTIN_VEXPANDMD, P10V_BUILTIN_VEXPANDMQ,
	P10V_BUILTIN_VEXTRACTMB, P10V_BUILTIN_VEXTRACTMH,
	P10V_BUILTIN_VEXTRACTMW, P10V_BUILTIN_VEXTRACTMD,
	P10V_BUILTIN_VEXTRACTMQ, P10V_BUILTIN_XVTLSBB_ZEROS,
	P10V_BUILTIN_XVTLSBB_ONES respectively.
	* config/rs6000/rs6000-call.c: Ditto above, change P10_BUILTIN_name to
	P10V_BUILTIN_name.
	(P10_BUILTIN_XVCVSPBF16, P10_BUILTIN_XVCVBF16SP): Change to
	P10V_BUILTIN_XVCVSPBF16, P10V_BUILTIN_XVCVBF16SP respectively.
This commit is contained in:
Carl Love 2020-08-10 19:37:41 -05:00
parent 95f17e2611
commit 07d456bb80
3 changed files with 330 additions and 305 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

269
gcc/config/rs6000/rs6000-builtin.def
View File

@ -1019,55 +1019,46 @@
| RS6000_BTC_BINARY), \
CODE_FOR_ ## ICODE) /* ICODE */
/* For builtins for power10 vector instructions that are encoded as altivec
instructions, use __builtin_altivec_ as the builtin name. */
/* Power 10 VSX builtins */
#define BU_P10V_0(ENUM, NAME, ATTR, ICODE) \
#define BU_P10V_VSX_0(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_0 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_altivec_" NAME, /* NAME */ \
"__builtin_vsx_" NAME, /* NAME */ \
RS6000_BTM_P10, /* MASK */ \
(RS6000_BTC_ ## ATTR /* ATTR */ \
| RS6000_BTC_SPECIAL), \
CODE_FOR_ ## ICODE) /* ICODE */
#define BU_P10V_1(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_1 (P10_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_altivec_" NAME, /* NAME */ \
#define BU_P10V_VSX_1(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_1 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_vsx_" NAME, /* NAME */ \
RS6000_BTM_P10, /* MASK */ \
(RS6000_BTC_ ## ATTR /* ATTR */ \
| RS6000_BTC_UNARY), \
CODE_FOR_ ## ICODE) /* ICODE */
#define BU_P10V_2(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_2 (P10_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_altivec_" NAME, /* NAME */ \
#define BU_P10V_VSX_2(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_2 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_vsx_" NAME, /* NAME */ \
RS6000_BTM_P10, /* MASK */ \
(RS6000_BTC_ ## ATTR /* ATTR */ \
| RS6000_BTC_BINARY), \
CODE_FOR_ ## ICODE) /* ICODE */
#define BU_P10V_3(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_3 (P10_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_altivec_" NAME, /* NAME */ \
#define BU_P10V_VSX_3(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_3 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_vsx_" NAME, /* NAME */ \
RS6000_BTM_P10, /* MASK */ \
(RS6000_BTC_ ## ATTR /* ATTR */ \
| RS6000_BTC_TERNARY), \
CODE_FOR_ ## ICODE) /* ICODE */
#define BU_P10V_4(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_4 (P10_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_altivec_" NAME, /* NAME */ \
RS6000_BTM_P10, /* MASK */ \
(RS6000_BTC_ ## ATTR /* ATTR */ \
| RS6000_BTC_QUATERNARY), \
CODE_FOR_ ## ICODE) /* ICODE */
#define BU_P10_VSX_1(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_1 (P10_BUILTIN_ ## ENUM, /* ENUM */ \
#define BU_P10V_VSX_4(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_4 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_vsx_" NAME, /* NAME */ \
RS6000_BTM_P10, /* MASK */ \
(RS6000_BTC_ ## ATTR /* ATTR */ \
| RS6000_BTC_UNARY), \
| RS6000_BTC_QUATERNARY), \
CODE_FOR_ ## ICODE) /* ICODE */
#define BU_P10_OVERLOAD_1(ENUM, NAME) \
@ -1154,6 +1145,40 @@
CODE_FOR_ ## ICODE) /* ICODE */
#endif
/* Power 10 Altivec builtins */
#define BU_P10V_AV_0(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_0 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_altivec_" NAME, /* NAME */ \
RS6000_BTM_P10, /* MASK */ \
(RS6000_BTC_ ## ATTR /* ATTR */ \
| RS6000_BTC_SPECIAL), \
CODE_FOR_ ## ICODE) /* ICODE */
#define BU_P10V_AV_1(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_1 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_altivec_" NAME, /* NAME */ \
RS6000_BTM_P10, /* MASK */ \
(RS6000_BTC_ ## ATTR /* ATTR */ \
| RS6000_BTC_UNARY), \
CODE_FOR_ ## ICODE) /* ICODE */
#define BU_P10V_AV_2(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_2 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_altivec_" NAME, /* NAME */ \
RS6000_BTM_P10, /* MASK */ \
(RS6000_BTC_ ## ATTR /* ATTR */ \
| RS6000_BTC_BINARY), \
CODE_FOR_ ## ICODE) /* ICODE */
#define BU_P10V_AV_3(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_3 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_altivec_" NAME, /* NAME */ \
RS6000_BTM_P10, /* MASK */ \
(RS6000_BTC_ ## ATTR /* ATTR */ \
| RS6000_BTC_TERNARY), \
CODE_FOR_ ## ICODE) /* ICODE */
/* Insure 0 is not a legitimate index. */
BU_SPECIAL_X (RS6000_BUILTIN_NONE, NULL, 0, RS6000_BTC_MISC)
@ -2710,119 +2735,119 @@ BU_P10_MISC_2 (PDEPD, "pdepd", CONST, pdepd)
BU_P10_MISC_2 (PEXTD, "pextd", CONST, pextd)
/* Builtins for vector instructions added in ISA 3.1 (power10). */
BU_P10V_2 (VCLRLB, "vclrlb", CONST, vclrlb)
BU_P10V_2 (VCLRRB, "vclrrb", CONST, vclrrb)
BU_P10V_2 (VCFUGED, "vcfuged", CONST, vcfuged)
BU_P10V_2 (VCLZDM, "vclzdm", CONST, vclzdm)
BU_P10V_2 (VCTZDM, "vctzdm", CONST, vctzdm)
BU_P10V_2 (VPDEPD, "vpdepd", CONST, vpdepd)
BU_P10V_2 (VPEXTD, "vpextd", CONST, vpextd)
BU_P10V_2 (VGNB, "vgnb", CONST, vgnb)
BU_P10V_4 (XXEVAL, "xxeval", CONST, xxeval)
BU_P10V_2 (XXGENPCVM_V16QI, "xxgenpcvm_v16qi", CONST, xxgenpcvm_v16qi)
BU_P10V_2 (XXGENPCVM_V8HI, "xxgenpcvm_v8hi", CONST, xxgenpcvm_v8hi)
BU_P10V_2 (XXGENPCVM_V4SI, "xxgenpcvm_v4si", CONST, xxgenpcvm_v4si)
BU_P10V_2 (XXGENPCVM_V2DI, "xxgenpcvm_v2di", CONST, xxgenpcvm_v2di)
BU_P10V_AV_2 (VCLRLB, "vclrlb", CONST, vclrlb)
BU_P10V_AV_2 (VCLRRB, "vclrrb", CONST, vclrrb)
BU_P10V_AV_2 (VCFUGED, "vcfuged", CONST, vcfuged)
BU_P10V_AV_2 (VCLZDM, "vclzdm", CONST, vclzdm)
BU_P10V_AV_2 (VCTZDM, "vctzdm", CONST, vctzdm)
BU_P10V_AV_2 (VPDEPD, "vpdepd", CONST, vpdepd)
BU_P10V_AV_2 (VPEXTD, "vpextd", CONST, vpextd)
BU_P10V_AV_2 (VGNB, "vgnb", CONST, vgnb)
BU_P10V_VSX_4 (XXEVAL, "xxeval", CONST, xxeval)
BU_P10V_VSX_2 (XXGENPCVM_V16QI, "xxgenpcvm_v16qi", CONST, xxgenpcvm_v16qi)
BU_P10V_VSX_2 (XXGENPCVM_V8HI, "xxgenpcvm_v8hi", CONST, xxgenpcvm_v8hi)
BU_P10V_VSX_2 (XXGENPCVM_V4SI, "xxgenpcvm_v4si", CONST, xxgenpcvm_v4si)
BU_P10V_VSX_2 (XXGENPCVM_V2DI, "xxgenpcvm_v2di", CONST, xxgenpcvm_v2di)
BU_P10V_3 (VEXTRACTBL, "vextdubvlx", CONST, vextractlv16qi)
BU_P10V_3 (VEXTRACTHL, "vextduhvlx", CONST, vextractlv8hi)
BU_P10V_3 (VEXTRACTWL, "vextduwvlx", CONST, vextractlv4si)
BU_P10V_3 (VEXTRACTDL, "vextddvlx", CONST, vextractlv2di)
BU_P10V_AV_3 (VEXTRACTBL, "vextdubvlx", CONST, vextractlv16qi)
BU_P10V_AV_3 (VEXTRACTHL, "vextduhvlx", CONST, vextractlv8hi)
BU_P10V_AV_3 (VEXTRACTWL, "vextduwvlx", CONST, vextractlv4si)
BU_P10V_AV_3 (VEXTRACTDL, "vextddvlx", CONST, vextractlv2di)
BU_P10V_3 (VEXTRACTBR, "vextdubvhx", CONST, vextractrv16qi)
BU_P10V_3 (VEXTRACTHR, "vextduhvhx", CONST, vextractrv8hi)
BU_P10V_3 (VEXTRACTWR, "vextduwvhx", CONST, vextractrv4si)
BU_P10V_3 (VEXTRACTDR, "vextddvhx", CONST, vextractrv2di)
BU_P10V_AV_3 (VEXTRACTBR, "vextdubvhx", CONST, vextractrv16qi)
BU_P10V_AV_3 (VEXTRACTHR, "vextduhvhx", CONST, vextractrv8hi)
BU_P10V_AV_3 (VEXTRACTWR, "vextduwvhx", CONST, vextractrv4si)
BU_P10V_AV_3 (VEXTRACTDR, "vextddvhx", CONST, vextractrv2di)
BU_P10V_3 (VINSERTGPRBL, "vinsgubvlx", CONST, vinsertgl_v16qi)
BU_P10V_3 (VINSERTGPRHL, "vinsguhvlx", CONST, vinsertgl_v8hi)
BU_P10V_3 (VINSERTGPRWL, "vinsguwvlx", CONST, vinsertgl_v4si)
BU_P10V_3 (VINSERTGPRDL, "vinsgudvlx", CONST, vinsertgl_v2di)
BU_P10V_3 (VINSERTVPRBL, "vinsvubvlx", CONST, vinsertvl_v16qi)
BU_P10V_3 (VINSERTVPRHL, "vinsvuhvlx", CONST, vinsertvl_v8hi)
BU_P10V_3 (VINSERTVPRWL, "vinsvuwvlx", CONST, vinsertvl_v4si)
BU_P10V_AV_3 (VINSERTGPRBL, "vinsgubvlx", CONST, vinsertgl_v16qi)
BU_P10V_AV_3 (VINSERTGPRHL, "vinsguhvlx", CONST, vinsertgl_v8hi)
BU_P10V_AV_3 (VINSERTGPRWL, "vinsguwvlx", CONST, vinsertgl_v4si)
BU_P10V_AV_3 (VINSERTGPRDL, "vinsgudvlx", CONST, vinsertgl_v2di)
BU_P10V_AV_3 (VINSERTVPRBL, "vinsvubvlx", CONST, vinsertvl_v16qi)
BU_P10V_AV_3 (VINSERTVPRHL, "vinsvuhvlx", CONST, vinsertvl_v8hi)
BU_P10V_AV_3 (VINSERTVPRWL, "vinsvuwvlx", CONST, vinsertvl_v4si)
BU_P10V_3 (VINSERTGPRBR, "vinsgubvrx", CONST, vinsertgr_v16qi)
BU_P10V_3 (VINSERTGPRHR, "vinsguhvrx", CONST, vinsertgr_v8hi)
BU_P10V_3 (VINSERTGPRWR, "vinsguwvrx", CONST, vinsertgr_v4si)
BU_P10V_3 (VINSERTGPRDR, "vinsgudvrx", CONST, vinsertgr_v2di)
BU_P10V_3 (VINSERTVPRBR, "vinsvubvrx", CONST, vinsertvr_v16qi)
BU_P10V_3 (VINSERTVPRHR, "vinsvuhvrx", CONST, vinsertvr_v8hi)
BU_P10V_3 (VINSERTVPRWR, "vinsvuwvrx", CONST, vinsertvr_v4si)
BU_P10V_AV_3 (VINSERTGPRBR, "vinsgubvrx", CONST, vinsertgr_v16qi)
BU_P10V_AV_3 (VINSERTGPRHR, "vinsguhvrx", CONST, vinsertgr_v8hi)
BU_P10V_AV_3 (VINSERTGPRWR, "vinsguwvrx", CONST, vinsertgr_v4si)
BU_P10V_AV_3 (VINSERTGPRDR, "vinsgudvrx", CONST, vinsertgr_v2di)
BU_P10V_AV_3 (VINSERTVPRBR, "vinsvubvrx", CONST, vinsertvr_v16qi)
BU_P10V_AV_3 (VINSERTVPRHR, "vinsvuhvrx", CONST, vinsertvr_v8hi)
BU_P10V_AV_3 (VINSERTVPRWR, "vinsvuwvrx", CONST, vinsertvr_v4si)
BU_P10V_3 (VREPLACE_ELT_V4SI, "vreplace_v4si", CONST, vreplace_elt_v4si)
BU_P10V_3 (VREPLACE_ELT_UV4SI, "vreplace_uv4si", CONST, vreplace_elt_v4si)
BU_P10V_3 (VREPLACE_ELT_V4SF, "vreplace_v4sf", CONST, vreplace_elt_v4sf)
BU_P10V_3 (VREPLACE_ELT_V2DI, "vreplace_v2di", CONST, vreplace_elt_v2di)
BU_P10V_3 (VREPLACE_ELT_UV2DI, "vreplace_uv2di", CONST, vreplace_elt_v2di)
BU_P10V_3 (VREPLACE_ELT_V2DF, "vreplace_v2df", CONST, vreplace_elt_v2df)
BU_P10V_AV_3 (VREPLACE_ELT_V4SI, "vreplace_v4si", CONST, vreplace_elt_v4si)
BU_P10V_AV_3 (VREPLACE_ELT_UV4SI, "vreplace_uv4si", CONST, vreplace_elt_v4si)
BU_P10V_AV_3 (VREPLACE_ELT_V4SF, "vreplace_v4sf", CONST, vreplace_elt_v4sf)
BU_P10V_AV_3 (VREPLACE_ELT_V2DI, "vreplace_v2di", CONST, vreplace_elt_v2di)
BU_P10V_AV_3 (VREPLACE_ELT_UV2DI, "vreplace_uv2di", CONST, vreplace_elt_v2di)
BU_P10V_AV_3 (VREPLACE_ELT_V2DF, "vreplace_v2df", CONST, vreplace_elt_v2df)
BU_P10V_3 (VREPLACE_UN_V4SI, "vreplace_un_v4si", CONST, vreplace_un_v4si)
BU_P10V_3 (VREPLACE_UN_UV4SI, "vreplace_un_uv4si", CONST, vreplace_un_v4si)
BU_P10V_3 (VREPLACE_UN_V4SF, "vreplace_un_v4sf", CONST, vreplace_un_v4sf)
BU_P10V_3 (VREPLACE_UN_V2DI, "vreplace_un_v2di", CONST, vreplace_un_v2di)
BU_P10V_3 (VREPLACE_UN_UV2DI, "vreplace_un_uv2di", CONST, vreplace_un_v2di)
BU_P10V_3 (VREPLACE_UN_V2DF, "vreplace_un_v2df", CONST, vreplace_un_v2df)
BU_P10V_AV_3 (VREPLACE_UN_V4SI, "vreplace_un_v4si", CONST, vreplace_un_v4si)
BU_P10V_AV_3 (VREPLACE_UN_UV4SI, "vreplace_un_uv4si", CONST, vreplace_un_v4si)
BU_P10V_AV_3 (VREPLACE_UN_V4SF, "vreplace_un_v4sf", CONST, vreplace_un_v4sf)
BU_P10V_AV_3 (VREPLACE_UN_V2DI, "vreplace_un_v2di", CONST, vreplace_un_v2di)
BU_P10V_AV_3 (VREPLACE_UN_UV2DI, "vreplace_un_uv2di", CONST, vreplace_un_v2di)
BU_P10V_AV_3 (VREPLACE_UN_V2DF, "vreplace_un_v2df", CONST, vreplace_un_v2df)
BU_P10V_3 (VSLDB_V16QI, "vsldb_v16qi", CONST, vsldb_v16qi)
BU_P10V_3 (VSLDB_V8HI, "vsldb_v8hi", CONST, vsldb_v8hi)
BU_P10V_3 (VSLDB_V4SI, "vsldb_v4si", CONST, vsldb_v4si)
BU_P10V_3 (VSLDB_V2DI, "vsldb_v2di", CONST, vsldb_v2di)
BU_P10V_AV_3 (VSLDB_V16QI, "vsldb_v16qi", CONST, vsldb_v16qi)
BU_P10V_AV_3 (VSLDB_V8HI, "vsldb_v8hi", CONST, vsldb_v8hi)
BU_P10V_AV_3 (VSLDB_V4SI, "vsldb_v4si", CONST, vsldb_v4si)
BU_P10V_AV_3 (VSLDB_V2DI, "vsldb_v2di", CONST, vsldb_v2di)
BU_P10V_3 (VSRDB_V16QI, "vsrdb_v16qi", CONST, vsrdb_v16qi)
BU_P10V_3 (VSRDB_V8HI, "vsrdb_v8hi", CONST, vsrdb_v8hi)
BU_P10V_3 (VSRDB_V4SI, "vsrdb_v4si", CONST, vsrdb_v4si)
BU_P10V_3 (VSRDB_V2DI, "vsrdb_v2di", CONST, vsrdb_v2di)
BU_P10V_AV_3 (VSRDB_V16QI, "vsrdb_v16qi", CONST, vsrdb_v16qi)
BU_P10V_AV_3 (VSRDB_V8HI, "vsrdb_v8hi", CONST, vsrdb_v8hi)
BU_P10V_AV_3 (VSRDB_V4SI, "vsrdb_v4si", CONST, vsrdb_v4si)
BU_P10V_AV_3 (VSRDB_V2DI, "vsrdb_v2di", CONST, vsrdb_v2di)
BU_P10V_1 (VXXSPLTIW_V4SI, "vxxspltiw_v4si", CONST, xxspltiw_v4si)
BU_P10V_1 (VXXSPLTIW_V4SF, "vxxspltiw_v4sf", CONST, xxspltiw_v4sf)
BU_P10V_VSX_1 (VXXSPLTIW_V4SI, "vxxspltiw_v4si", CONST, xxspltiw_v4si)
BU_P10V_VSX_1 (VXXSPLTIW_V4SF, "vxxspltiw_v4sf", CONST, xxspltiw_v4sf)
BU_P10V_1 (VXXSPLTID, "vxxspltidp", CONST, xxspltidp_v2df)
BU_P10V_VSX_1 (VXXSPLTID, "vxxspltidp", CONST, xxspltidp_v2df)
BU_P10V_3 (VXXSPLTI32DX_V4SI, "vxxsplti32dx_v4si", CONST, xxsplti32dx_v4si)
BU_P10V_3 (VXXSPLTI32DX_V4SF, "vxxsplti32dx_v4sf", CONST, xxsplti32dx_v4sf)
BU_P10V_VSX_3 (VXXSPLTI32DX_V4SI, "vxxsplti32dx_v4si", CONST, xxsplti32dx_v4si)
BU_P10V_VSX_3 (VXXSPLTI32DX_V4SF, "vxxsplti32dx_v4sf", CONST, xxsplti32dx_v4sf)
BU_P10V_3 (VXXBLEND_V16QI, "xxblend_v16qi", CONST, xxblend_v16qi)
BU_P10V_3 (VXXBLEND_V8HI, "xxblend_v8hi", CONST, xxblend_v8hi)
BU_P10V_3 (VXXBLEND_V4SI, "xxblend_v4si", CONST, xxblend_v4si)
BU_P10V_3 (VXXBLEND_V2DI, "xxblend_v2di", CONST, xxblend_v2di)
BU_P10V_3 (VXXBLEND_V4SF, "xxblend_v4sf", CONST, xxblend_v4sf)
BU_P10V_3 (VXXBLEND_V2DF, "xxblend_v2df", CONST, xxblend_v2df)
BU_P10V_VSX_3 (VXXBLEND_V16QI, "xxblend_v16qi", CONST, xxblend_v16qi)
BU_P10V_VSX_3 (VXXBLEND_V8HI, "xxblend_v8hi", CONST, xxblend_v8hi)
BU_P10V_VSX_3 (VXXBLEND_V4SI, "xxblend_v4si", CONST, xxblend_v4si)
BU_P10V_VSX_3 (VXXBLEND_V2DI, "xxblend_v2di", CONST, xxblend_v2di)
BU_P10V_VSX_3 (VXXBLEND_V4SF, "xxblend_v4sf", CONST, xxblend_v4sf)
BU_P10V_VSX_3 (VXXBLEND_V2DF, "xxblend_v2df", CONST, xxblend_v2df)
BU_P10V_4 (VXXPERMX, "xxpermx", CONST, xxpermx)
BU_P10V_VSX_4 (VXXPERMX, "xxpermx", CONST, xxpermx)
BU_P10V_1 (VSTRIBR, "vstribr", CONST, vstrir_v16qi)
BU_P10V_1 (VSTRIHR, "vstrihr", CONST, vstrir_v8hi)
BU_P10V_1 (VSTRIBL, "vstribl", CONST, vstril_v16qi)
BU_P10V_1 (VSTRIHL, "vstrihl", CONST, vstril_v8hi)
BU_P10V_AV_1 (VSTRIBR, "vstribr", CONST, vstrir_v16qi)
BU_P10V_AV_1 (VSTRIHR, "vstrihr", CONST, vstrir_v8hi)
BU_P10V_AV_1 (VSTRIBL, "vstribl", CONST, vstril_v16qi)
BU_P10V_AV_1 (VSTRIHL, "vstrihl", CONST, vstril_v8hi)
BU_P10V_1 (VSTRIBR_P, "vstribr_p", CONST, vstrir_p_v16qi)
BU_P10V_1 (VSTRIHR_P, "vstrihr_p", CONST, vstrir_p_v8hi)
BU_P10V_1 (VSTRIBL_P, "vstribl_p", CONST, vstril_p_v16qi)
BU_P10V_1 (VSTRIHL_P, "vstrihl_p", CONST, vstril_p_v8hi)
BU_P10V_AV_1 (VSTRIBR_P, "vstribr_p", CONST, vstrir_p_v16qi)
BU_P10V_AV_1 (VSTRIHR_P, "vstrihr_p", CONST, vstrir_p_v8hi)
BU_P10V_AV_1 (VSTRIBL_P, "vstribl_p", CONST, vstril_p_v16qi)
BU_P10V_AV_1 (VSTRIHL_P, "vstrihl_p", CONST, vstril_p_v8hi)
BU_P10_VSX_1 (XVTLSBB_ZEROS, "xvtlsbb_all_zeros", CONST, xvtlsbbz)
BU_P10_VSX_1 (XVTLSBB_ONES, "xvtlsbb_all_ones", CONST, xvtlsbbo)
BU_P10V_VSX_1 (XVTLSBB_ZEROS, "xvtlsbb_all_zeros", CONST, xvtlsbbz)
BU_P10V_VSX_1 (XVTLSBB_ONES, "xvtlsbb_all_ones", CONST, xvtlsbbo)
BU_P10V_1 (MTVSRBM, "mtvsrbm", CONST, vec_mtvsr_v16qi)
BU_P10V_1 (MTVSRHM, "mtvsrhm", CONST, vec_mtvsr_v8hi)
BU_P10V_1 (MTVSRWM, "mtvsrwm", CONST, vec_mtvsr_v4si)
BU_P10V_1 (MTVSRDM, "mtvsrdm", CONST, vec_mtvsr_v2di)
BU_P10V_1 (MTVSRQM, "mtvsrqm", CONST, vec_mtvsr_v1ti)
BU_P10V_2 (VCNTMBB, "cntmbb", CONST, vec_cntmb_v16qi)
BU_P10V_2 (VCNTMBH, "cntmbh", CONST, vec_cntmb_v8hi)
BU_P10V_2 (VCNTMBW, "cntmbw", CONST, vec_cntmb_v4si)
BU_P10V_2 (VCNTMBD, "cntmbd", CONST, vec_cntmb_v2di)
BU_P10V_1 (VEXPANDMB, "vexpandmb", CONST, vec_expand_v16qi)
BU_P10V_1 (VEXPANDMH, "vexpandmh", CONST, vec_expand_v8hi)
BU_P10V_1 (VEXPANDMW, "vexpandmw", CONST, vec_expand_v4si)
BU_P10V_1 (VEXPANDMD, "vexpandmd", CONST, vec_expand_v2di)
BU_P10V_1 (VEXPANDMQ, "vexpandmq", CONST, vec_expand_v1ti)
BU_P10V_1 (VEXTRACTMB, "vextractmb", CONST, vec_extract_v16qi)
BU_P10V_1 (VEXTRACTMH, "vextractmh", CONST, vec_extract_v8hi)
BU_P10V_1 (VEXTRACTMW, "vextractmw", CONST, vec_extract_v4si)
BU_P10V_1 (VEXTRACTMD, "vextractmd", CONST, vec_extract_v2di)
BU_P10V_1 (VEXTRACTMQ, "vextractmq", CONST, vec_extract_v1ti)
BU_P10V_AV_1 (MTVSRBM, "mtvsrbm", CONST, vec_mtvsr_v16qi)
BU_P10V_AV_1 (MTVSRHM, "mtvsrhm", CONST, vec_mtvsr_v8hi)
BU_P10V_AV_1 (MTVSRWM, "mtvsrwm", CONST, vec_mtvsr_v4si)
BU_P10V_AV_1 (MTVSRDM, "mtvsrdm", CONST, vec_mtvsr_v2di)
BU_P10V_AV_1 (MTVSRQM, "mtvsrqm", CONST, vec_mtvsr_v1ti)
BU_P10V_AV_2 (VCNTMBB, "cntmbb", CONST, vec_cntmb_v16qi)
BU_P10V_AV_2 (VCNTMBH, "cntmbh", CONST, vec_cntmb_v8hi)
BU_P10V_AV_2 (VCNTMBW, "cntmbw", CONST, vec_cntmb_v4si)
BU_P10V_AV_2 (VCNTMBD, "cntmbd", CONST, vec_cntmb_v2di)
BU_P10V_AV_1 (VEXPANDMB, "vexpandmb", CONST, vec_expand_v16qi)
BU_P10V_AV_1 (VEXPANDMH, "vexpandmh", CONST, vec_expand_v8hi)
BU_P10V_AV_1 (VEXPANDMW, "vexpandmw", CONST, vec_expand_v4si)
BU_P10V_AV_1 (VEXPANDMD, "vexpandmd", CONST, vec_expand_v2di)
BU_P10V_AV_1 (VEXPANDMQ, "vexpandmq", CONST, vec_expand_v1ti)
BU_P10V_AV_1 (VEXTRACTMB, "vextractmb", CONST, vec_extract_v16qi)
BU_P10V_AV_1 (VEXTRACTMH, "vextractmh", CONST, vec_extract_v8hi)
BU_P10V_AV_1 (VEXTRACTMW, "vextractmw", CONST, vec_extract_v4si)
BU_P10V_AV_1 (VEXTRACTMD, "vextractmd", CONST, vec_extract_v2di)
BU_P10V_AV_1 (VEXTRACTMQ, "vextractmq", CONST, vec_extract_v1ti)
/* Overloaded vector builtins for ISA 3.1 (power10). */
BU_P10_OVERLOAD_2 (CLRL, "clrl")
@ -2998,8 +3023,8 @@ BU_SPECIAL_X (RS6000_BUILTIN_CFSTRING, "__builtin_cfstring", RS6000_BTM_ALWAYS,
RS6000_BTC_MISC)
/* POWER10 MMA builtins. */
BU_VSX_1 (XVCVBF16SPN, "xvcvbf16spn", MISC, vsx_xvcvbf16spn)
BU_VSX_1 (XVCVSPBF16, "xvcvspbf16", MISC, vsx_xvcvspbf16)
BU_P10V_VSX_1 (XVCVBF16SPN, "xvcvbf16spn", MISC, vsx_xvcvbf16spn)
BU_P10V_VSX_1 (XVCVSPBF16, "xvcvspbf16", MISC, vsx_xvcvspbf16)
BU_MMA_1 (XXMFACC, "xxmfacc", QUAD, mma_xxmfacc)
BU_MMA_1 (XXMTACC, "xxmtacc", QUAD, mma_xxmtacc)

6
gcc/config/rs6000/rs6000-c.c
View File

@ -1801,12 +1801,12 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
}
}
else if ((fcode == P10_BUILTIN_VEC_XXEVAL)
|| (fcode == P10_BUILTIN_VXXPERMX))
|| (fcode == P10V_BUILTIN_VXXPERMX))
{
signed char op3_type;
/* Need to special case P10_BUILTIN_VEC_XXEVAL and
P10_BUILTIN_VXXPERMX because they take 4 arguments and the
P10V_BUILTIN_VXXPERMX because they take 4 arguments and the
existing infrastructure only handles three. */
if (nargs != 4)
{
@ -1821,7 +1821,7 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
{
if (fcode == P10_BUILTIN_VEC_XXEVAL)
op3_type = desc->op3;
else /* P10_BUILTIN_VXXPERMX */
else /* P10V_BUILTIN_VXXPERMX */
op3_type = RS6000_BTI_V16QI;
if (rs6000_builtin_type_compatible (types[0], desc->op1)

360
gcc/config/rs6000/rs6000-call.c
View File

@ -5528,366 +5528,366 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
RS6000_BTI_INTSI, RS6000_BTI_INTSI },
/* Overloaded built-in functions for ISA3.1 (power10). */
{ P10_BUILTIN_VEC_CLRL, P10_BUILTIN_VCLRLB,
{ P10_BUILTIN_VEC_CLRL, P10V_BUILTIN_VCLRLB,
RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_UINTSI, 0 },
{ P10_BUILTIN_VEC_CLRL, P10_BUILTIN_VCLRLB,
{ P10_BUILTIN_VEC_CLRL, P10V_BUILTIN_VCLRLB,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
RS6000_BTI_UINTSI, 0 },
{ P10_BUILTIN_VEC_CLRR, P10_BUILTIN_VCLRRB,
{ P10_BUILTIN_VEC_CLRR, P10V_BUILTIN_VCLRRB,
RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_UINTSI, 0 },
{ P10_BUILTIN_VEC_CLRR, P10_BUILTIN_VCLRRB,
{ P10_BUILTIN_VEC_CLRR, P10V_BUILTIN_VCLRRB,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
RS6000_BTI_UINTSI, 0 },
{ P10_BUILTIN_VEC_GNB, P10_BUILTIN_VGNB, RS6000_BTI_unsigned_long_long,
{ P10_BUILTIN_VEC_GNB, P10V_BUILTIN_VGNB, RS6000_BTI_unsigned_long_long,
RS6000_BTI_unsigned_V1TI, RS6000_BTI_UINTQI, 0 },
{ P10_BUILTIN_VEC_XXGENPCVM, P10_BUILTIN_XXGENPCVM_V2DI,
{ P10_BUILTIN_VEC_XXGENPCVM, P10V_BUILTIN_XXGENPCVM_V2DI,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0 },
{ P10_BUILTIN_VEC_XXGENPCVM, P10_BUILTIN_XXGENPCVM_V4SI,
{ P10_BUILTIN_VEC_XXGENPCVM, P10V_BUILTIN_XXGENPCVM_V4SI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
{ P10_BUILTIN_VEC_XXGENPCVM, P10_BUILTIN_XXGENPCVM_V8HI,
{ P10_BUILTIN_VEC_XXGENPCVM, P10V_BUILTIN_XXGENPCVM_V8HI,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 },
{ P10_BUILTIN_VEC_XXGENPCVM, P10_BUILTIN_XXGENPCVM_V16QI,
{ P10_BUILTIN_VEC_XXGENPCVM, P10V_BUILTIN_XXGENPCVM_V16QI,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
RS6000_BTI_INTSI, 0 },
/* The overloaded XXEVAL definitions are handled specially because the
fourth unsigned char operand is not encoded in this table. */
{ P10_BUILTIN_VEC_XXEVAL, P10_BUILTIN_XXEVAL,
{ P10_BUILTIN_VEC_XXEVAL, P10V_BUILTIN_XXEVAL,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
{ P10_BUILTIN_VEC_XXEVAL, P10_BUILTIN_XXEVAL,
{ P10_BUILTIN_VEC_XXEVAL, P10V_BUILTIN_XXEVAL,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
{ P10_BUILTIN_VEC_XXEVAL, P10_BUILTIN_XXEVAL,
{ P10_BUILTIN_VEC_XXEVAL, P10V_BUILTIN_XXEVAL,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
{ P10_BUILTIN_VEC_XXEVAL, P10_BUILTIN_XXEVAL,
{ P10_BUILTIN_VEC_XXEVAL, P10V_BUILTIN_XXEVAL,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
{ P10_BUILTIN_VEC_XXEVAL, P10_BUILTIN_XXEVAL,
{ P10_BUILTIN_VEC_XXEVAL, P10V_BUILTIN_XXEVAL,
RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
/* The overloaded XXPERMX definitions are handled specially because the
fourth unsigned char operand is not encoded in this table. */
{ P10_BUILTIN_VEC_XXPERMX, P10_BUILTIN_VXXPERMX,
{ P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI,
RS6000_BTI_unsigned_V16QI },
{ P10_BUILTIN_VEC_XXPERMX, P10_BUILTIN_VXXPERMX,
{ P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
{ P10_BUILTIN_VEC_XXPERMX, P10_BUILTIN_VXXPERMX,
{ P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI,
RS6000_BTI_unsigned_V16QI },
{ P10_BUILTIN_VEC_XXPERMX, P10_BUILTIN_VXXPERMX,
{ P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI },
{ P10_BUILTIN_VEC_XXPERMX, P10_BUILTIN_VXXPERMX,
{ P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI,
RS6000_BTI_unsigned_V16QI },
{ P10_BUILTIN_VEC_XXPERMX, P10_BUILTIN_VXXPERMX,
{ P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI },
{ P10_BUILTIN_VEC_XXPERMX, P10_BUILTIN_VXXPERMX,
{ P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI,
RS6000_BTI_unsigned_V16QI },
{ P10_BUILTIN_VEC_XXPERMX, P10_BUILTIN_VXXPERMX,
{ P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI },
{ P10_BUILTIN_VEC_XXPERMX, P10_BUILTIN_VXXPERMX,
{ P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF,
RS6000_BTI_unsigned_V16QI },
{ P10_BUILTIN_VEC_XXPERMX, P10_BUILTIN_VXXPERMX,
{ P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF,
RS6000_BTI_unsigned_V16QI },
{ P10_BUILTIN_VEC_EXTRACTL, P10_BUILTIN_VEXTRACTBL,
{ P10_BUILTIN_VEC_EXTRACTL, P10V_BUILTIN_VEXTRACTBL,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI },
{ P10_BUILTIN_VEC_EXTRACTL, P10_BUILTIN_VEXTRACTHL,
{ P10_BUILTIN_VEC_EXTRACTL, P10V_BUILTIN_VEXTRACTHL,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V8HI,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI },
{ P10_BUILTIN_VEC_EXTRACTL, P10_BUILTIN_VEXTRACTWL,
{ P10_BUILTIN_VEC_EXTRACTL, P10V_BUILTIN_VEXTRACTWL,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI },
{ P10_BUILTIN_VEC_EXTRACTL, P10_BUILTIN_VEXTRACTDL,
{ P10_BUILTIN_VEC_EXTRACTL, P10V_BUILTIN_VEXTRACTDL,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTQI },
{ P10_BUILTIN_VEC_INSERTL, P10_BUILTIN_VINSERTGPRBL,
{ P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTGPRBL,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTSI },
{ P10_BUILTIN_VEC_INSERTL, P10_BUILTIN_VINSERTGPRHL,
{ P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTGPRHL,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTHI,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTSI },
{ P10_BUILTIN_VEC_INSERTL, P10_BUILTIN_VINSERTGPRWL,
{ P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTGPRWL,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTSI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTSI },
{ P10_BUILTIN_VEC_INSERTL, P10_BUILTIN_VINSERTGPRDL,
{ P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTGPRDL,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTDI,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTSI },
{ P10_BUILTIN_VEC_INSERTL, P10_BUILTIN_VINSERTVPRBL,
{ P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTVPRBL,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI },
{ P10_BUILTIN_VEC_INSERTL, P10_BUILTIN_VINSERTVPRHL,
{ P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTVPRHL,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI },
{ P10_BUILTIN_VEC_INSERTL, P10_BUILTIN_VINSERTVPRWL,
{ P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTVPRWL,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI },
{ P10_BUILTIN_VEC_EXTRACTH, P10_BUILTIN_VEXTRACTBR,
{ P10_BUILTIN_VEC_EXTRACTH, P10V_BUILTIN_VEXTRACTBR,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI },
{ P10_BUILTIN_VEC_EXTRACTH, P10_BUILTIN_VEXTRACTHR,
{ P10_BUILTIN_VEC_EXTRACTH, P10V_BUILTIN_VEXTRACTHR,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V8HI,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI },
{ P10_BUILTIN_VEC_EXTRACTH, P10_BUILTIN_VEXTRACTWR,
{ P10_BUILTIN_VEC_EXTRACTH, P10V_BUILTIN_VEXTRACTWR,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI },
{ P10_BUILTIN_VEC_EXTRACTH, P10_BUILTIN_VEXTRACTDR,
{ P10_BUILTIN_VEC_EXTRACTH, P10V_BUILTIN_VEXTRACTDR,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTQI },
{ P10_BUILTIN_VEC_INSERTH, P10_BUILTIN_VINSERTGPRBR,
{ P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTGPRBR,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTSI },
{ P10_BUILTIN_VEC_INSERTH, P10_BUILTIN_VINSERTGPRHR,
{ P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTGPRHR,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTHI,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTSI },
{ P10_BUILTIN_VEC_INSERTH, P10_BUILTIN_VINSERTGPRWR,
{ P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTGPRWR,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTSI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTSI },
{ P10_BUILTIN_VEC_INSERTH, P10_BUILTIN_VINSERTGPRDR,
{ P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTGPRDR,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTDI,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTSI },
{ P10_BUILTIN_VEC_INSERTH, P10_BUILTIN_VINSERTVPRBR,
{ P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTVPRBR,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI },
{ P10_BUILTIN_VEC_INSERTH, P10_BUILTIN_VINSERTVPRHR,
{ P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTVPRHR,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI },
{ P10_BUILTIN_VEC_INSERTH, P10_BUILTIN_VINSERTVPRWR,
{ P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTVPRWR,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI },
{ P10_BUILTIN_VEC_REPLACE_ELT, P10_BUILTIN_VREPLACE_ELT_UV4SI,
{ P10_BUILTIN_VEC_REPLACE_ELT, P10V_BUILTIN_VREPLACE_ELT_UV4SI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
RS6000_BTI_UINTSI, RS6000_BTI_UINTQI },
{ P10_BUILTIN_VEC_REPLACE_ELT, P10_BUILTIN_VREPLACE_ELT_V4SI,
{ P10_BUILTIN_VEC_REPLACE_ELT, P10V_BUILTIN_VREPLACE_ELT_V4SI,
RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTQI },
{ P10_BUILTIN_VEC_REPLACE_ELT, P10_BUILTIN_VREPLACE_ELT_V4SF,
{ P10_BUILTIN_VEC_REPLACE_ELT, P10V_BUILTIN_VREPLACE_ELT_V4SF,
RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_float, RS6000_BTI_INTQI },
{ P10_BUILTIN_VEC_REPLACE_ELT, P10_BUILTIN_VREPLACE_ELT_UV2DI,
{ P10_BUILTIN_VEC_REPLACE_ELT, P10V_BUILTIN_VREPLACE_ELT_UV2DI,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
RS6000_BTI_UINTDI, RS6000_BTI_UINTQI },
{ P10_BUILTIN_VEC_REPLACE_ELT, P10_BUILTIN_VREPLACE_ELT_V2DI,
{ P10_BUILTIN_VEC_REPLACE_ELT, P10V_BUILTIN_VREPLACE_ELT_V2DI,
RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTDI, RS6000_BTI_INTQI },
{ P10_BUILTIN_VEC_REPLACE_ELT, P10_BUILTIN_VREPLACE_ELT_V2DF,
{ P10_BUILTIN_VEC_REPLACE_ELT, P10V_BUILTIN_VREPLACE_ELT_V2DF,
RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_double, RS6000_BTI_INTQI },
{ P10_BUILTIN_VEC_REPLACE_UN, P10_BUILTIN_VREPLACE_UN_UV4SI,
{ P10_BUILTIN_VEC_REPLACE_UN, P10V_BUILTIN_VREPLACE_UN_UV4SI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
RS6000_BTI_UINTSI, RS6000_BTI_UINTQI },
{ P10_BUILTIN_VEC_REPLACE_UN, P10_BUILTIN_VREPLACE_UN_V4SI,
{ P10_BUILTIN_VEC_REPLACE_UN, P10V_BUILTIN_VREPLACE_UN_V4SI,
RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTQI },
{ P10_BUILTIN_VEC_REPLACE_UN, P10_BUILTIN_VREPLACE_UN_V4SF,
{ P10_BUILTIN_VEC_REPLACE_UN, P10V_BUILTIN_VREPLACE_UN_V4SF,
RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_float, RS6000_BTI_INTQI },
{ P10_BUILTIN_VEC_REPLACE_UN, P10_BUILTIN_VREPLACE_UN_UV2DI,
{ P10_BUILTIN_VEC_REPLACE_UN, P10V_BUILTIN_VREPLACE_UN_UV2DI,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
RS6000_BTI_UINTDI, RS6000_BTI_UINTQI },
{ P10_BUILTIN_VEC_REPLACE_UN, P10_BUILTIN_VREPLACE_UN_V2DI,
{ P10_BUILTIN_VEC_REPLACE_UN, P10V_BUILTIN_VREPLACE_UN_V2DI,
RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTDI, RS6000_BTI_INTQI },
{ P10_BUILTIN_VEC_REPLACE_UN, P10_BUILTIN_VREPLACE_UN_V2DF,
{ P10_BUILTIN_VEC_REPLACE_UN, P10V_BUILTIN_VREPLACE_UN_V2DF,
RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_double, RS6000_BTI_INTQI },
{ P10_BUILTIN_VEC_SLDB, P10_BUILTIN_VSLDB_V16QI,
{ P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V16QI,
RS6000_BTI_V16QI, RS6000_BTI_V16QI,
RS6000_BTI_V16QI, RS6000_BTI_UINTQI },
{ P10_BUILTIN_VEC_SLDB, P10_BUILTIN_VSLDB_V16QI,
{ P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V16QI,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI },
{ P10_BUILTIN_VEC_SLDB, P10_BUILTIN_VSLDB_V8HI,
{ P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V8HI,
RS6000_BTI_V8HI, RS6000_BTI_V8HI,
RS6000_BTI_V8HI, RS6000_BTI_UINTQI },
{ P10_BUILTIN_VEC_SLDB, P10_BUILTIN_VSLDB_V8HI,
{ P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V8HI,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI },
{ P10_BUILTIN_VEC_SLDB, P10_BUILTIN_VSLDB_V4SI,
{ P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V4SI,
RS6000_BTI_V4SI, RS6000_BTI_V4SI,
RS6000_BTI_V4SI, RS6000_BTI_UINTQI },
{ P10_BUILTIN_VEC_SLDB, P10_BUILTIN_VSLDB_V4SI,
{ P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V4SI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI },
{ P10_BUILTIN_VEC_SLDB, P10_BUILTIN_VSLDB_V2DI,
{ P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V2DI,
RS6000_BTI_V2DI, RS6000_BTI_V2DI,
RS6000_BTI_V2DI, RS6000_BTI_UINTQI },
{ P10_BUILTIN_VEC_SLDB, P10_BUILTIN_VSLDB_V2DI,
{ P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V2DI,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTQI },
{ P10_BUILTIN_VEC_XXSPLTIW, P10_BUILTIN_VXXSPLTIW_V4SI,
{ P10_BUILTIN_VEC_XXSPLTIW, P10V_BUILTIN_VXXSPLTIW_V4SI,
RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0, 0 },
{ P10_BUILTIN_VEC_XXSPLTIW, P10_BUILTIN_VXXSPLTIW_V4SF,
{ P10_BUILTIN_VEC_XXSPLTIW, P10V_BUILTIN_VXXSPLTIW_V4SF,
RS6000_BTI_V4SF, RS6000_BTI_float, 0, 0 },
{ P10_BUILTIN_VEC_XXSPLTID, P10_BUILTIN_VXXSPLTID,
{ P10_BUILTIN_VEC_XXSPLTID, P10V_BUILTIN_VXXSPLTID,
RS6000_BTI_V2DF, RS6000_BTI_float, 0, 0 },
{ P10_BUILTIN_VEC_XXSPLTI32DX, P10_BUILTIN_VXXSPLTI32DX_V4SI,
{ P10_BUILTIN_VEC_XXSPLTI32DX, P10V_BUILTIN_VXXSPLTI32DX_V4SI,
RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_UINTQI, RS6000_BTI_INTSI },
{ P10_BUILTIN_VEC_XXSPLTI32DX, P10_BUILTIN_VXXSPLTI32DX_V4SI,
{ P10_BUILTIN_VEC_XXSPLTI32DX, P10V_BUILTIN_VXXSPLTI32DX_V4SI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI,
RS6000_BTI_UINTSI },
{ P10_BUILTIN_VEC_XXSPLTI32DX, P10_BUILTIN_VXXSPLTI32DX_V4SF,
{ P10_BUILTIN_VEC_XXSPLTI32DX, P10V_BUILTIN_VXXSPLTI32DX_V4SF,
RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_UINTQI, RS6000_BTI_float },
{ P10_BUILTIN_VEC_XXBLEND, P10_BUILTIN_VXXBLEND_V16QI,
{ P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V16QI,
RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI,
RS6000_BTI_unsigned_V16QI },
{ P10_BUILTIN_VEC_XXBLEND, P10_BUILTIN_VXXBLEND_V16QI,
{ P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V16QI,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
{ P10_BUILTIN_VEC_XXBLEND, P10_BUILTIN_VXXBLEND_V8HI,
{ P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V8HI,
RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI,
RS6000_BTI_unsigned_V8HI },
{ P10_BUILTIN_VEC_XXBLEND, P10_BUILTIN_VXXBLEND_V8HI,
{ P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V8HI,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
{ P10_BUILTIN_VEC_XXBLEND, P10_BUILTIN_VXXBLEND_V4SI,
{ P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V4SI,
RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI,
RS6000_BTI_unsigned_V4SI },
{ P10_BUILTIN_VEC_XXBLEND, P10_BUILTIN_VXXBLEND_V4SI,
{ P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V4SI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
{ P10_BUILTIN_VEC_XXBLEND, P10_BUILTIN_VXXBLEND_V2DI,
{ P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V2DI,
RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI,
RS6000_BTI_unsigned_V2DI },
{ P10_BUILTIN_VEC_XXBLEND, P10_BUILTIN_VXXBLEND_V2DI,
{ P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V2DI,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
{ P10_BUILTIN_VEC_XXBLEND, P10_BUILTIN_VXXBLEND_V4SF,
{ P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V4SF,
RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF,
RS6000_BTI_unsigned_V4SI },
{ P10_BUILTIN_VEC_XXBLEND, P10_BUILTIN_VXXBLEND_V2DF,
{ P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V2DF,
RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF,
RS6000_BTI_unsigned_V2DI },
{ P10_BUILTIN_VEC_SRDB, P10_BUILTIN_VSRDB_V16QI,
{ P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V16QI,
RS6000_BTI_V16QI, RS6000_BTI_V16QI,
RS6000_BTI_V16QI, RS6000_BTI_UINTQI },
{ P10_BUILTIN_VEC_SRDB, P10_BUILTIN_VSRDB_V16QI,
{ P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V16QI,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI },
{ P10_BUILTIN_VEC_SRDB, P10_BUILTIN_VSRDB_V8HI,
{ P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V8HI,
RS6000_BTI_V8HI, RS6000_BTI_V8HI,
RS6000_BTI_V8HI, RS6000_BTI_UINTQI },
{ P10_BUILTIN_VEC_SRDB, P10_BUILTIN_VSRDB_V8HI,
{ P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V8HI,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI },
{ P10_BUILTIN_VEC_SRDB, P10_BUILTIN_VSRDB_V4SI,
{ P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V4SI,
RS6000_BTI_V4SI, RS6000_BTI_V4SI,
RS6000_BTI_V4SI, RS6000_BTI_UINTQI },
{ P10_BUILTIN_VEC_SRDB, P10_BUILTIN_VSRDB_V4SI,
{ P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V4SI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI },
{ P10_BUILTIN_VEC_SRDB, P10_BUILTIN_VSRDB_V2DI,
{ P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V2DI,
RS6000_BTI_V2DI, RS6000_BTI_V2DI,
RS6000_BTI_V2DI, RS6000_BTI_UINTQI },
{ P10_BUILTIN_VEC_SRDB, P10_BUILTIN_VSRDB_V2DI,
{ P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V2DI,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTQI },
{ P10_BUILTIN_VEC_VSTRIL, P10_BUILTIN_VSTRIBL,
{ P10_BUILTIN_VEC_VSTRIL, P10V_BUILTIN_VSTRIBL,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
{ P10_BUILTIN_VEC_VSTRIL, P10_BUILTIN_VSTRIBL,
{ P10_BUILTIN_VEC_VSTRIL, P10V_BUILTIN_VSTRIBL,
RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
{ P10_BUILTIN_VEC_VSTRIL, P10_BUILTIN_VSTRIHL,
{ P10_BUILTIN_VEC_VSTRIL, P10V_BUILTIN_VSTRIHL,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
{ P10_BUILTIN_VEC_VSTRIL, P10_BUILTIN_VSTRIHL,
{ P10_BUILTIN_VEC_VSTRIL, P10V_BUILTIN_VSTRIHL,
RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
{ P10_BUILTIN_VEC_VSTRIL_P, P10_BUILTIN_VSTRIBL_P,
{ P10_BUILTIN_VEC_VSTRIL_P, P10V_BUILTIN_VSTRIBL_P,
RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
{ P10_BUILTIN_VEC_VSTRIL_P, P10_BUILTIN_VSTRIBL_P,
{ P10_BUILTIN_VEC_VSTRIL_P, P10V_BUILTIN_VSTRIBL_P,
RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
{ P10_BUILTIN_VEC_VSTRIL_P, P10_BUILTIN_VSTRIHL_P,
{ P10_BUILTIN_VEC_VSTRIL_P, P10V_BUILTIN_VSTRIHL_P,
RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, 0, 0 },
{ P10_BUILTIN_VEC_VSTRIL_P, P10_BUILTIN_VSTRIHL_P,
{ P10_BUILTIN_VEC_VSTRIL_P, P10V_BUILTIN_VSTRIHL_P,
RS6000_BTI_INTSI, RS6000_BTI_V8HI, 0, 0 },
{ P10_BUILTIN_VEC_VSTRIR, P10_BUILTIN_VSTRIBR,
{ P10_BUILTIN_VEC_VSTRIR, P10V_BUILTIN_VSTRIBR,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
{ P10_BUILTIN_VEC_VSTRIR, P10_BUILTIN_VSTRIBR,
{ P10_BUILTIN_VEC_VSTRIR, P10V_BUILTIN_VSTRIBR,
RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
{ P10_BUILTIN_VEC_VSTRIR, P10_BUILTIN_VSTRIHR,
{ P10_BUILTIN_VEC_VSTRIR, P10V_BUILTIN_VSTRIHR,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
{ P10_BUILTIN_VEC_VSTRIR, P10_BUILTIN_VSTRIHR,
{ P10_BUILTIN_VEC_VSTRIR, P10V_BUILTIN_VSTRIHR,
RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
{ P10_BUILTIN_VEC_VSTRIR_P, P10_BUILTIN_VSTRIBR_P,
{ P10_BUILTIN_VEC_VSTRIR_P, P10V_BUILTIN_VSTRIBR_P,
RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
{ P10_BUILTIN_VEC_VSTRIR_P, P10_BUILTIN_VSTRIBR_P,
{ P10_BUILTIN_VEC_VSTRIR_P, P10V_BUILTIN_VSTRIBR_P,
RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
{ P10_BUILTIN_VEC_VSTRIR_P, P10_BUILTIN_VSTRIHR_P,
{ P10_BUILTIN_VEC_VSTRIR_P, P10V_BUILTIN_VSTRIHR_P,
RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, 0, 0 },
{ P10_BUILTIN_VEC_VSTRIR_P, P10_BUILTIN_VSTRIHR_P,
{ P10_BUILTIN_VEC_VSTRIR_P, P10V_BUILTIN_VSTRIHR_P,
RS6000_BTI_INTSI, RS6000_BTI_V8HI, 0, 0 },
{ P10_BUILTIN_VEC_MTVSRBM, P10_BUILTIN_MTVSRBM,
{ P10_BUILTIN_VEC_MTVSRBM, P10V_BUILTIN_MTVSRBM,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTDI, 0, 0 },
{ P10_BUILTIN_VEC_MTVSRHM, P10_BUILTIN_MTVSRHM,
{ P10_BUILTIN_VEC_MTVSRHM, P10V_BUILTIN_MTVSRHM,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTDI, 0, 0 },
{ P10_BUILTIN_VEC_MTVSRWM, P10_BUILTIN_MTVSRWM,
{ P10_BUILTIN_VEC_MTVSRWM, P10V_BUILTIN_MTVSRWM,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTDI, 0, 0 },
{ P10_BUILTIN_VEC_MTVSRDM, P10_BUILTIN_MTVSRDM,
{ P10_BUILTIN_VEC_MTVSRDM, P10V_BUILTIN_MTVSRDM,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTDI, 0, 0 },
{ P10_BUILTIN_VEC_MTVSRQM, P10_BUILTIN_MTVSRQM,
{ P10_BUILTIN_VEC_MTVSRQM, P10V_BUILTIN_MTVSRQM,
RS6000_BTI_unsigned_V1TI, RS6000_BTI_UINTDI, 0, 0 },
{ P10_BUILTIN_VEC_VCNTM, P10_BUILTIN_VCNTMBB,
{ P10_BUILTIN_VEC_VCNTM, P10V_BUILTIN_VCNTMBB,
RS6000_BTI_unsigned_long_long,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI, 0 },
{ P10_BUILTIN_VEC_VCNTM, P10_BUILTIN_VCNTMBH,
{ P10_BUILTIN_VEC_VCNTM, P10V_BUILTIN_VCNTMBH,
RS6000_BTI_unsigned_long_long,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI, 0 },
{ P10_BUILTIN_VEC_VCNTM, P10_BUILTIN_VCNTMBW,
{ P10_BUILTIN_VEC_VCNTM, P10V_BUILTIN_VCNTMBW,
RS6000_BTI_unsigned_long_long,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI, 0 },
{ P10_BUILTIN_VEC_VCNTM, P10_BUILTIN_VCNTMBD,
{ P10_BUILTIN_VEC_VCNTM, P10V_BUILTIN_VCNTMBD,
RS6000_BTI_unsigned_long_long,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTQI, 0 },
{ P10_BUILTIN_VEC_VEXPANDM, P10_BUILTIN_VEXPANDMB,
{ P10_BUILTIN_VEC_VEXPANDM, P10V_BUILTIN_VEXPANDMB,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
{ P10_BUILTIN_VEC_VEXPANDM, P10_BUILTIN_VEXPANDMH,
{ P10_BUILTIN_VEC_VEXPANDM, P10V_BUILTIN_VEXPANDMH,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
{ P10_BUILTIN_VEC_VEXPANDM, P10_BUILTIN_VEXPANDMW,
{ P10_BUILTIN_VEC_VEXPANDM, P10V_BUILTIN_VEXPANDMW,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
{ P10_BUILTIN_VEC_VEXPANDM, P10_BUILTIN_VEXPANDMD,
{ P10_BUILTIN_VEC_VEXPANDM, P10V_BUILTIN_VEXPANDMD,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
{ P10_BUILTIN_VEC_VEXPANDM, P10_BUILTIN_VEXPANDMQ,
{ P10_BUILTIN_VEC_VEXPANDM, P10V_BUILTIN_VEXPANDMQ,
RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
{ P10_BUILTIN_VEC_VEXTRACTM, P10_BUILTIN_VEXTRACTMB,
{ P10_BUILTIN_VEC_VEXTRACTM, P10V_BUILTIN_VEXTRACTMB,
RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
{ P10_BUILTIN_VEC_VEXTRACTM, P10_BUILTIN_VEXTRACTMH,
{ P10_BUILTIN_VEC_VEXTRACTM, P10V_BUILTIN_VEXTRACTMH,
RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, 0, 0 },
{ P10_BUILTIN_VEC_VEXTRACTM, P10_BUILTIN_VEXTRACTMW,
{ P10_BUILTIN_VEC_VEXTRACTM, P10V_BUILTIN_VEXTRACTMW,
RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, 0, 0 },
{ P10_BUILTIN_VEC_VEXTRACTM, P10_BUILTIN_VEXTRACTMD,
{ P10_BUILTIN_VEC_VEXTRACTM, P10V_BUILTIN_VEXTRACTMD,
RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, 0, 0 },
{ P10_BUILTIN_VEC_VEXTRACTM, P10_BUILTIN_VEXTRACTMQ,
{ P10_BUILTIN_VEC_VEXTRACTM, P10V_BUILTIN_VEXTRACTMQ,
RS6000_BTI_INTSI, RS6000_BTI_unsigned_V1TI, 0, 0 },
{ P10_BUILTIN_VEC_XVTLSBB_ZEROS, P10_BUILTIN_XVTLSBB_ZEROS,
{ P10_BUILTIN_VEC_XVTLSBB_ZEROS, P10V_BUILTIN_XVTLSBB_ZEROS,
RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
{ P10_BUILTIN_VEC_XVTLSBB_ONES, P10_BUILTIN_XVTLSBB_ONES,
{ P10_BUILTIN_VEC_XVTLSBB_ONES, P10V_BUILTIN_XVTLSBB_ONES,
RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
{ RS6000_BUILTIN_NONE, RS6000_BUILTIN_NONE, 0, 0, 0, 0 }
@ -13969,7 +13969,7 @@ builtin_quaternary_function_type (machine_mode mode_ret,
switch (builtin) {
case P10_BUILTIN_XXEVAL:
case P10V_BUILTIN_XXEVAL:
gcc_assert ((mode_ret == V2DImode)
&& (mode_arg0 == V2DImode)
&& (mode_arg1 == V2DImode)
@ -13978,7 +13978,7 @@ builtin_quaternary_function_type (machine_mode mode_ret,
function_type = xxeval_type;
break;
case P10_BUILTIN_VXXPERMX:
case P10V_BUILTIN_VXXPERMX:
gcc_assert ((mode_ret == V2DImode)
&& (mode_arg0 == V2DImode)
&& (mode_arg1 == V2DImode)
@ -14036,22 +14036,22 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
case P8V_BUILTIN_VGBBD:
case MISC_BUILTIN_CDTBCD:
case MISC_BUILTIN_CBCDTD:
case VSX_BUILTIN_XVCVSPBF16:
case VSX_BUILTIN_XVCVBF16SPN:
case P10_BUILTIN_MTVSRBM:
case P10_BUILTIN_MTVSRHM:
case P10_BUILTIN_MTVSRWM:
case P10_BUILTIN_MTVSRDM:
case P10_BUILTIN_MTVSRQM:
case P10_BUILTIN_VCNTMBB:
case P10_BUILTIN_VCNTMBH:
case P10_BUILTIN_VCNTMBW:
case P10_BUILTIN_VCNTMBD:
case P10_BUILTIN_VEXPANDMB:
case P10_BUILTIN_VEXPANDMH:
case P10_BUILTIN_VEXPANDMW:
case P10_BUILTIN_VEXPANDMD:
case P10_BUILTIN_VEXPANDMQ:
case P10V_BUILTIN_XVCVSPBF16:
case P10V_BUILTIN_XVCVBF16SPN:
case P10V_BUILTIN_MTVSRBM:
case P10V_BUILTIN_MTVSRHM:
case P10V_BUILTIN_MTVSRWM:
case P10V_BUILTIN_MTVSRDM:
case P10V_BUILTIN_MTVSRQM:
case P10V_BUILTIN_VCNTMBB:
case P10V_BUILTIN_VCNTMBH:
case P10V_BUILTIN_VCNTMBW:
case P10V_BUILTIN_VCNTMBD:
case P10V_BUILTIN_VEXPANDMB:
case P10V_BUILTIN_VEXPANDMH:
case P10V_BUILTIN_VEXPANDMW:
case P10V_BUILTIN_VEXPANDMD:
case P10V_BUILTIN_VEXPANDMQ:
h.uns_p[0] = 1;
h.uns_p[1] = 1;
break;
@ -14123,16 +14123,16 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
case P8V_BUILTIN_ORC_V4SI_UNS:
case P8V_BUILTIN_ORC_V2DI_UNS:
case P8V_BUILTIN_ORC_V1TI_UNS:
case P10_BUILTIN_VCFUGED:
case P10_BUILTIN_VCLZDM:
case P10_BUILTIN_VCTZDM:
case P10_BUILTIN_VGNB:
case P10_BUILTIN_VPDEPD:
case P10_BUILTIN_VPEXTD:
case P10_BUILTIN_XXGENPCVM_V16QI:
case P10_BUILTIN_XXGENPCVM_V8HI:
case P10_BUILTIN_XXGENPCVM_V4SI:
case P10_BUILTIN_XXGENPCVM_V2DI:
case P10V_BUILTIN_VCFUGED:
case P10V_BUILTIN_VCLZDM:
case P10V_BUILTIN_VCTZDM:
case P10V_BUILTIN_VGNB:
case P10V_BUILTIN_VPDEPD:
case P10V_BUILTIN_VPEXTD:
case P10V_BUILTIN_XXGENPCVM_V16QI:
case P10V_BUILTIN_XXGENPCVM_V8HI:
case P10V_BUILTIN_XXGENPCVM_V4SI:
case P10V_BUILTIN_XXGENPCVM_V2DI:
h.uns_p[0] = 1;
h.uns_p[1] = 1;
h.uns_p[2] = 1;
@ -14163,29 +14163,29 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
case CRYPTO_BUILTIN_VSHASIGMAW:
case CRYPTO_BUILTIN_VSHASIGMAD:
case CRYPTO_BUILTIN_VSHASIGMA:
case P10_BUILTIN_VEXTRACTBL:
case P10_BUILTIN_VEXTRACTHL:
case P10_BUILTIN_VEXTRACTWL:
case P10_BUILTIN_VEXTRACTDL:
case P10_BUILTIN_VEXTRACTBR:
case P10_BUILTIN_VEXTRACTHR:
case P10_BUILTIN_VEXTRACTWR:
case P10_BUILTIN_VEXTRACTDR:
case P10_BUILTIN_VINSERTGPRBL:
case P10_BUILTIN_VINSERTGPRHL:
case P10_BUILTIN_VINSERTGPRWL:
case P10_BUILTIN_VINSERTGPRDL:
case P10_BUILTIN_VINSERTVPRBL:
case P10_BUILTIN_VINSERTVPRHL:
case P10_BUILTIN_VINSERTVPRWL:
case P10_BUILTIN_VREPLACE_ELT_UV4SI:
case P10_BUILTIN_VREPLACE_ELT_UV2DI:
case P10_BUILTIN_VREPLACE_UN_UV4SI:
case P10_BUILTIN_VREPLACE_UN_UV2DI:
case P10_BUILTIN_VXXBLEND_V16QI:
case P10_BUILTIN_VXXBLEND_V8HI:
case P10_BUILTIN_VXXBLEND_V4SI:
case P10_BUILTIN_VXXBLEND_V2DI:
case P10V_BUILTIN_VEXTRACTBL:
case P10V_BUILTIN_VEXTRACTHL:
case P10V_BUILTIN_VEXTRACTWL:
case P10V_BUILTIN_VEXTRACTDL:
case P10V_BUILTIN_VEXTRACTBR:
case P10V_BUILTIN_VEXTRACTHR:
case P10V_BUILTIN_VEXTRACTWR:
case P10V_BUILTIN_VEXTRACTDR:
case P10V_BUILTIN_VINSERTGPRBL:
case P10V_BUILTIN_VINSERTGPRHL:
case P10V_BUILTIN_VINSERTGPRWL:
case P10V_BUILTIN_VINSERTGPRDL:
case P10V_BUILTIN_VINSERTVPRBL:
case P10V_BUILTIN_VINSERTVPRHL:
case P10V_BUILTIN_VINSERTVPRWL:
case P10V_BUILTIN_VREPLACE_ELT_UV4SI:
case P10V_BUILTIN_VREPLACE_ELT_UV2DI:
case P10V_BUILTIN_VREPLACE_UN_UV4SI:
case P10V_BUILTIN_VREPLACE_UN_UV2DI:
case P10V_BUILTIN_VXXBLEND_V16QI:
case P10V_BUILTIN_VXXBLEND_V8HI:
case P10V_BUILTIN_VXXBLEND_V4SI:
case P10V_BUILTIN_VXXBLEND_V2DI:
h.uns_p[0] = 1;
h.uns_p[1] = 1;
h.uns_p[2] = 1;
@ -14253,8 +14253,8 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
case ALTIVEC_BUILTIN_VSRW:
case P8V_BUILTIN_VSRD:
/* Vector splat immediate insert */
case P10_BUILTIN_VXXSPLTI32DX_V4SI:
case P10_BUILTIN_VXXSPLTI32DX_V4SF:
case P10V_BUILTIN_VXXSPLTI32DX_V4SI:
case P10V_BUILTIN_VXXSPLTI32DX_V4SF:
h.uns_p[2] = 1;
break;