Unroll my commit of 1999/08/01 16:14:58, there was a communications mixup
about its status. From-SVN: r28403
This commit is contained in:
Geoffrey Keating
parent
ccc0b2f9b5
commit
0865c6314e
@ -36,44 +36,6 @@ Sun Aug 1 20:14:00 1999 Bernd Schmidt <bernds@cygnus.co.uk>
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* tree.h (init_dummy_function_start): Declare.
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Sun Jul 25 19:32:58 1999 Geoff Keating <geoffk@cygnus.com>
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* config/rs6000/rs6000.c (num_insns_constant_wide): Correct
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for type promotion.
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(add_operand): Get test correct for 64-bit HOST_WIDE_INT.
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(non_add_cint_operand): Likewise.
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(logical_operand): Likewise.
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(non_logical_cint_operand): Likewise.
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(print_operand): Correct printf()s for 64-bit HOST_WIDE_INT.
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(print_operand_address): Correct printf() for 64-bit HOST_WIDE_INT.
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(rs6000_select_rtx_section): Suppress warning.
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(small_data_operand): Suppress warning.
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(rs6000_got_register): Suppress warning.
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* config/rs6000/rs6000.md (andsi3): HOST_WIDE_INT is a signed
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type, so `J' is generally the wrong constraint for a SImode value;
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use `L' instead.
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(andsi3_internal2): Likewise.
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(andsi3_internal3): Likewise.
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(iorsi3_internal1): Likewise.
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(xorsi3_internal1): Likewise.
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(movsi): Likewise.
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(movsf_softfloat): Likewise.
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various unnamed compare insns: Likewise.
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(movsi+2): Preserve sign bits of SImode constant.
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(floatsidf2_internal+1): Sign-extend SImode constant correctly.
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(movdf+1): Preserve high bits of DFmode constant.
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(movdi_32+1): Sign-extend properly.
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various unnamed compare insns: Sign-extend properly.
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* unroll.c (loop_iterations): Convert HOST_WIDE_INT to unsigned
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properly for mode.
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* expmed.c (expand_mult_highpart): Convert HOST_WIDE_INT from unsigned
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properly for mode.
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(expand_divmod): Likewise.
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* optabs.c (expand_fix): Keep HOST_WIDE_INT constants properly signed.
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(expand_binop): Sometimes there is work to do when changing
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the mode of a CONST_INT.
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Sun Aug 1 12:55:31 1999 Bernd Schmidt <bernds@cygnus.co.uk>
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* stmt.c (emit_filename, emit_lineno, expr_stmts_for_value,
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@ -666,11 +666,16 @@ num_insns_constant_wide (value)
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if (((unsigned HOST_WIDE_INT)value + 0x8000) < 0x10000)
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return 1;
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#if HOST_BITS_PER_WIDE_INT == 32
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/* constant loadable with {cau|addis} */
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else if (CONST_OK_FOR_LETTER_P (value, 'L'))
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else if ((value & 0xffff) == 0)
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return 1;
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#else
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/* constant loadable with {cau|addis} */
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else if ((value & 0xffff) == 0 && (value & ~0xffffffff) == 0)
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return 1;
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#if HOST_BITS_PER_WIDE_INT == 64
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else if (TARGET_64BIT)
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{
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HOST_WIDE_INT low = value & 0xffffffff;
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@ -875,7 +880,7 @@ mem_or_easy_const_operand (op, mode)
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}
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/* Return 1 if the operand is either a non-special register or an item
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that can be used as the operand of a `mode' add insn. */
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that can be used as the operand of an SI add insn. */
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int
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add_operand (op, mode)
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@ -884,7 +889,7 @@ add_operand (op, mode)
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{
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return (reg_or_short_operand (op, mode)
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|| (GET_CODE (op) == CONST_INT
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&& CONST_OK_FOR_LETTER_P (INTVAL(op), 'L')));
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&& (INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff0000)) == 0));
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}
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/* Return 1 if OP is a constant but not a valid add_operand. */
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@ -896,7 +901,7 @@ non_add_cint_operand (op, mode)
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{
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return (GET_CODE (op) == CONST_INT
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&& (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000
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&& ! CONST_OK_FOR_LETTER_P (INTVAL(op), 'L'));
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&& (INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff0000)) != 0);
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}
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/* Return 1 if the operand is a non-special register or a constant that
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@ -909,10 +914,8 @@ logical_operand (op, mode)
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{
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return (gpc_reg_operand (op, mode)
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|| (GET_CODE (op) == CONST_INT
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&& ((INTVAL (op) & GET_MODE_MASK (mode)
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& (~ (HOST_WIDE_INT) 0xffff)) == 0
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|| (INTVAL (op) & GET_MODE_MASK (mode)
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& (~ (HOST_WIDE_INT) 0xffff0000)) == 0)));
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&& ((INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff)) == 0
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|| (INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff0000)) == 0)));
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}
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/* Return 1 if C is a constant that is not a logical operand (as
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@ -921,13 +924,11 @@ logical_operand (op, mode)
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int
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non_logical_cint_operand (op, mode)
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register rtx op;
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enum machine_mode mode;
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enum machine_mode mode ATTRIBUTE_UNUSED;
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{
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return (GET_CODE (op) == CONST_INT
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&& (INTVAL (op) & GET_MODE_MASK (mode) &
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(~ (HOST_WIDE_INT) 0xffff)) != 0
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&& (INTVAL (op) & GET_MODE_MASK (mode) &
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(~ (HOST_WIDE_INT) 0xffff0000)) != 0);
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&& (INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff)) != 0
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&& (INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff0000)) != 0);
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}
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/* Return 1 if C is a constant that can be encoded in a 32-bit mask on the
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@ -1197,7 +1198,7 @@ small_data_operand (op, mode)
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enum machine_mode mode ATTRIBUTE_UNUSED;
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{
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#if TARGET_ELF
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rtx sym_ref;
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rtx sym_ref, const_part;
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if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
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return 0;
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@ -2473,7 +2474,7 @@ ccr_bit (op, scc_p)
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struct rtx_def *
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rs6000_got_register (value)
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rtx value ATTRIBUTE_UNUSED;
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rtx value;
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{
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/* The second flow pass currently (June 1999) can't update regs_ever_live
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without disturbing other parts of the compiler, so update it here to
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@ -2626,7 +2627,7 @@ print_operand (file, x, code)
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if (! INT_P (x))
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output_operand_lossage ("invalid %%b value");
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fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
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fprintf (file, "%d", INT_LOWPART (x) & 0xffff);
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return;
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case 'B':
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@ -2712,7 +2713,7 @@ print_operand (file, x, code)
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/* If constant, output low-order five bits. Otherwise,
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write normally. */
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if (INT_P (x))
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fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
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fprintf (file, "%d", INT_LOWPART (x) & 31);
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else
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print_operand (file, x, 0);
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return;
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@ -2721,7 +2722,7 @@ print_operand (file, x, code)
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/* If constant, output low-order six bits. Otherwise,
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write normally. */
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if (INT_P (x))
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fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
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fprintf (file, "%d", INT_LOWPART (x) & 63);
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else
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print_operand (file, x, 0);
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return;
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@ -2758,7 +2759,7 @@ print_operand (file, x, code)
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if (! INT_P (x))
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output_operand_lossage ("invalid %%k value");
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fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
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fprintf (file, "%d", ~ INT_LOWPART (x));
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return;
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case 'L':
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@ -2902,7 +2903,7 @@ print_operand (file, x, code)
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if (! INT_P (x))
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output_operand_lossage ("invalid %%s value");
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fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
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fprintf (file, "%d", (32 - INT_LOWPART (x)) & 31);
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return;
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case 'S':
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@ -3005,8 +3006,7 @@ print_operand (file, x, code)
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if (! INT_P (x))
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output_operand_lossage ("invalid %%u value");
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fprintf (file, HOST_WIDE_INT_PRINT_HEX,
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(INT_LOWPART (x) >> 16) & 0xffff);
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fprintf (file, "0x%x", (INT_LOWPART (x) >> 16) & 0xffff);
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return;
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case 'v':
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@ -3076,8 +3076,7 @@ print_operand (file, x, code)
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/* If constant, low-order 16 bits of constant, signed. Otherwise, write
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normally. */
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if (INT_P (x))
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fprintf (file, HOST_WIDE_INT_PRINT_DEC,
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((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
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fprintf (file, "%d", ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
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else
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print_operand (file, x, 0);
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return;
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@ -3086,7 +3085,7 @@ print_operand (file, x, code)
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/* If constant, low-order 16 bits of constant, unsigned.
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Otherwise, write normally. */
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if (INT_P (x))
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fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
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fprintf (file, "%d", INT_LOWPART (x) & 0xffff);
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else
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print_operand (file, x, 0);
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return;
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@ -3222,10 +3221,7 @@ print_operand_address (file, x)
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reg_names[ REGNO (XEXP (x, 1)) ]);
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}
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else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
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{
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fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (XEXP (x, 1)));
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fprintf (file, "(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
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}
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fprintf (file, "%d(%s)", INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
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#if TARGET_ELF
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else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
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&& CONSTANT_P (XEXP (x, 1)))
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@ -5653,7 +5649,7 @@ rs6000_longcall_ref (call_ref)
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void
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rs6000_select_rtx_section (mode, x)
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enum machine_mode mode ATTRIBUTE_UNUSED;
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enum machine_mode mode;
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rtx x;
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{
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if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x))
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@ -1938,7 +1938,7 @@
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(define_insn "andsi3"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
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(and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
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(match_operand:SI 2 "and_operand" "?r,T,K,L")))
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(match_operand:SI 2 "and_operand" "?r,T,K,J")))
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(clobber (match_scratch:CC 3 "=X,X,x,x"))]
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""
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"@
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@ -1955,7 +1955,7 @@
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(define_insn "*andsi3_internal2"
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[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
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(compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
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(match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
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(match_operand:SI 2 "and_operand" "r,K,J,T,r,K,J,T"))
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(const_int 0)))
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(clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
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(clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
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@ -1992,7 +1992,7 @@
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(define_insn "*andsi3_internal3"
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[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
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(compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
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(match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
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(match_operand:SI 2 "and_operand" "r,K,J,T,r,K,J,T"))
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
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(and:SI (match_dup 1)
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@ -2054,7 +2054,7 @@
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(define_insn "*iorsi3_internal1"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
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(ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
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(match_operand:SI 2 "logical_operand" "r,K,L")))]
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(match_operand:SI 2 "logical_operand" "r,K,J")))]
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""
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"@
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or %0,%1,%2
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@ -2161,7 +2161,7 @@
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(define_insn "*xorsi3_internal1"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
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(xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
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(match_operand:SI 2 "logical_operand" "r,K,L")))]
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(match_operand:SI 2 "logical_operand" "r,K,J")))]
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""
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"@
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xor %0,%1,%2
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@ -4226,7 +4226,7 @@
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(match_dup 3)))]
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"
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{
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operands[6] = GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff);
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operands[6] = GEN_INT (0x80000000);
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operands[7] = gen_rtx_REG (DFmode, FPMEM_REGNUM);
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}")
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@ -6127,7 +6127,7 @@
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(match_dup 3)))]
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"
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{
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operands[2] = GEN_INT (INTVAL (operands[1]) & (~ (HOST_WIDE_INT) 0xffff));
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operands[2] = GEN_INT (INTVAL (operands[1]) & 0xffff0000);
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operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff);
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}")
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@ -6383,7 +6383,7 @@
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int endian = (WORDS_BIG_ENDIAN == 0);
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operands[2] = operand_subword (operands[0], endian, 0, DFmode);
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operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
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operands[4] = GEN_INT(INTVAL (operands[1]) >> 31 >> 1);
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operands[4] = (INTVAL (operands[1]) & 0x80000000) ? constm1_rtx : const0_rtx;
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}")
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(define_split
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@ -6740,14 +6740,13 @@
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(set (match_dup 3) (match_dup 1))]
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"
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{
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HOST_WIDE_INT value = INTVAL (operands[1]);
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operands[2] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN == 0);
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operands[3] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN != 0);
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#if HOST_BITS_PER_WIDE_INT == 32
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operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
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operands[4] = (INTVAL (operands[1]) & 0x80000000) ? constm1_rtx : const0_rtx;
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#else
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operands[4] = GEN_INT (value >> 32);
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operands[1] = GEN_INT ((value & 0x7fffffff) - (value & 0x80000000));
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operands[4] = GEN_INT ((HOST_WIDE_INT) INTVAL (operands[1]) >> 32);
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operands[1] = GEN_INT (INTVAL (operands[1]) & 0xffffffff);
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#endif
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}")
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@ -8894,9 +8893,9 @@
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sign-extended to 16 bits. Then see what constant could be XOR'ed
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with C to get the sign-extended value. */
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HOST_WIDE_INT c = INTVAL (operands[2]);
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HOST_WIDE_INT sextc = (c & 0x7fff) - (c & 0x8000);
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HOST_WIDE_INT xorv = c ^ sextc;
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int c = INTVAL (operands[2]);
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int sextc = (c << 16) >> 16;
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int xorv = c ^ sextc;
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operands[4] = GEN_INT (xorv);
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operands[5] = GEN_INT (sextc);
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@ -9129,7 +9128,7 @@
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(define_insn ""
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
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(eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
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(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
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(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")))
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(clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
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""
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"@
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@ -9158,7 +9157,7 @@
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[(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x")
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(compare:CC
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(eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
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(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
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(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
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(eq:SI (match_dup 1) (match_dup 2)))
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@ -9210,7 +9209,7 @@
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(define_insn ""
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
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(plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
|
||||
(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
|
||||
(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
|
||||
(match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))
|
||||
(clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
|
||||
""
|
||||
@ -9227,7 +9226,7 @@
|
||||
(compare:CC
|
||||
(plus:SI
|
||||
(eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
|
||||
(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
|
||||
(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
|
||||
(match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
|
||||
@ -9246,7 +9245,7 @@
|
||||
(compare:CC
|
||||
(plus:SI
|
||||
(eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
|
||||
(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
|
||||
(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
|
||||
(match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))
|
||||
(const_int 0)))
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
|
||||
@ -9265,7 +9264,7 @@
|
||||
(define_insn ""
|
||||
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
|
||||
(neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
|
||||
(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))]
|
||||
(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))]
|
||||
""
|
||||
"@
|
||||
xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
|
||||
|
||||
@ -2718,13 +2718,13 @@ expand_mult_highpart (mode, op0, cnst1, target, unsignedp, max_cost)
|
||||
int size = GET_MODE_BITSIZE (mode);
|
||||
rtx op1, wide_op1;
|
||||
|
||||
/* We can't support modes wider than HOST_BITS_PER_WIDE_INT. */
|
||||
/* We can't support modes wider than HOST_BITS_PER_INT. */
|
||||
if (size > HOST_BITS_PER_WIDE_INT)
|
||||
abort ();
|
||||
|
||||
op1 = GEN_INT (cnst1 | -(cnst1 & ((HOST_WIDE_INT) 1 << (size - 1))));
|
||||
op1 = GEN_INT (cnst1);
|
||||
|
||||
if (GET_MODE_BITSIZE (wider_mode) <= HOST_BITS_PER_WIDE_INT)
|
||||
if (GET_MODE_BITSIZE (wider_mode) <= HOST_BITS_PER_INT)
|
||||
wide_op1 = op1;
|
||||
else
|
||||
wide_op1
|
||||
@ -3726,8 +3726,6 @@ expand_divmod (rem_flag, code, mode, op0, op1, target, unsignedp)
|
||||
|
||||
post_shift = floor_log2 (d & -d);
|
||||
ml = invert_mod2n (d >> post_shift, size);
|
||||
/* Sign-extend ml for compute_mode. */
|
||||
ml |= -(ml & (1 << (GET_MODE_BITSIZE (compute_mode)-1)));
|
||||
t1 = expand_mult (compute_mode, op0, GEN_INT (ml), NULL_RTX,
|
||||
unsignedp);
|
||||
quotient = expand_shift (RSHIFT_EXPR, compute_mode, t1,
|
||||
|
||||
10
gcc/md.texi
10
gcc/md.texi
@ -1384,14 +1384,13 @@ Floating point register
|
||||
Signed 16 bit constant
|
||||
|
||||
@item J
|
||||
Unsigned 16 bit constant shifted left 16 bits (use @samp{L} instead for
|
||||
@code{SImode} constants)
|
||||
Constant whose low 16 bits are 0
|
||||
|
||||
@item K
|
||||
Unsigned 16 bit constant
|
||||
Constant whose high 16 bits are 0
|
||||
|
||||
@item L
|
||||
Signed 16 bit constant shifted left 16 bits
|
||||
Constant suitable as a mask operand
|
||||
|
||||
@item M
|
||||
Constant larger than 31
|
||||
@ -1419,9 +1418,6 @@ AIX TOC entry
|
||||
@item S
|
||||
Constant suitable as a 64-bit mask operand
|
||||
|
||||
@item T
|
||||
Constant suitable as a 32-bit mask operand
|
||||
|
||||
@item U
|
||||
System V Release 4 small data area reference
|
||||
@end table
|
||||
|
||||
@ -857,12 +857,12 @@ expand_binop (mode, binoptab, op0, op1, target, unsignedp, methods)
|
||||
/* In case the insn wants input operands in modes different from
|
||||
the result, convert the operands. */
|
||||
|
||||
if ((GET_MODE (op0) != VOIDmode || GET_CODE (op0) == CONST_INT)
|
||||
if (GET_MODE (op0) != VOIDmode
|
||||
&& GET_MODE (op0) != mode0
|
||||
&& mode0 != VOIDmode)
|
||||
xop0 = convert_to_mode (mode0, xop0, unsignedp);
|
||||
|
||||
if ((GET_MODE (xop1) != VOIDmode || GET_CODE (xop1) == CONST_INT)
|
||||
if (GET_MODE (xop1) != VOIDmode
|
||||
&& GET_MODE (xop1) != mode1
|
||||
&& mode1 != VOIDmode)
|
||||
xop1 = convert_to_mode (mode1, xop1, unsignedp);
|
||||
@ -4231,7 +4231,7 @@ expand_fix (to, from, unsignedp)
|
||||
NULL_RTX, 0, OPTAB_LIB_WIDEN);
|
||||
expand_fix (to, target, 0);
|
||||
target = expand_binop (GET_MODE (to), xor_optab, to,
|
||||
GEN_INT ((HOST_WIDE_INT) -1 << (bitsize - 1)),
|
||||
GEN_INT ((HOST_WIDE_INT) 1 << (bitsize - 1)),
|
||||
to, 1, OPTAB_LIB_WIDEN);
|
||||
|
||||
if (target != to)
|
||||
|
||||
@ -3588,7 +3588,6 @@ loop_iterations (loop_start, loop_end, loop_info)
|
||||
rtx comparison, comparison_value;
|
||||
rtx iteration_var, initial_value, increment, final_value;
|
||||
enum rtx_code comparison_code;
|
||||
enum machine_mode comparison_mode;
|
||||
HOST_WIDE_INT abs_inc;
|
||||
unsigned HOST_WIDE_INT abs_diff;
|
||||
int off_by_one;
|
||||
@ -3653,7 +3652,6 @@ loop_iterations (loop_start, loop_end, loop_info)
|
||||
invariant register when it canonicalizes the comparison. */
|
||||
|
||||
comparison_code = GET_CODE (comparison);
|
||||
comparison_mode = GET_MODE (comparison);
|
||||
iteration_var = XEXP (comparison, 0);
|
||||
comparison_value = XEXP (comparison, 1);
|
||||
|
||||
@ -3993,10 +3991,6 @@ loop_iterations (loop_start, loop_end, loop_info)
|
||||
else
|
||||
abort ();
|
||||
|
||||
/* It may be that comparison_mode is smaller than a HOST_WIDE_INT,
|
||||
for instance on a 64-bit host when comparison_mode is SImode. */
|
||||
abs_diff &= GET_MODE_MASK (comparison_mode);
|
||||
|
||||
/* For NE tests, make sure that the iteration variable won't miss
|
||||
the final value. If abs_diff mod abs_incr is not zero, then the
|
||||
iteration variable will overflow before the loop exits, and we
|
||||
|
||||
Loading…
Reference in New Issue
Block a user