re PR target/52144 (ARM should support arm/thumb function attribute to permit different instruction sets in the same source)
2015-05-13 Christian Bruel <christian.bruel@st.com> PR target/52144 * config/arm/arm.c (arm_option_check_internal) (arm_option_params_internal): Check opts->target_flags to set macros. (TREE_TARGET_ARM, TREE_TARGET_THUMB) (TREE_TARGET_THUMB1, TREE_TARGET_THUMB2) Replace with... (TARGET_ARM_P, TARGET_THUMB_P, TARGET_THUMB1_P, TARGET_THUMB2_P) (builtin_define): Replaced with def_or_undef_macro. * config/arm/arm.h (TREE_TARGET_ARM, TREE_TARGET_THUMB) TREE_TARGET_THUMB1, TREE_TARGET_THUMB2) Redefine with... (TARGET_ARM_P, TARGET_THUMB_P, TARGET_THUMB1_P, TARGET_THUMB2_P) (TARGET_32BIT_P, TARGET_ARM_QBIT_P, TARGET_ARM_SAT_P, TARGET_IDIV_P) (TARGET_HAVE_LDREX_P, TARGET_HAVE_LDREXBH_P, TARGET_HAVE_LDREXD_P) (TARGET_ARM_FEATURE_LDREX_P) (TARGET_DSP_MULTIPLY_P, TARGET_INT_SIMD_P): New macros. (def_or_undef_macro): New function. From-SVN: r223699
This commit is contained in:
Christian Bruel
parent
7049e4eb33
commit
08793a386a
@ -1,3 +1,21 @@
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2015-05-13 Christian Bruel <christian.bruel@st.com>
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PR target/52144
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* config/arm/arm.c (arm_option_check_internal)
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(arm_option_params_internal): Check opts->target_flags to set macros.
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(TREE_TARGET_ARM, TREE_TARGET_THUMB)
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(TREE_TARGET_THUMB1, TREE_TARGET_THUMB2) Replace with...
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(TARGET_ARM_P, TARGET_THUMB_P, TARGET_THUMB1_P, TARGET_THUMB2_P)
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(builtin_define): Replaced with def_or_undef_macro.
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* config/arm/arm.h (TREE_TARGET_ARM, TREE_TARGET_THUMB)
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TREE_TARGET_THUMB1, TREE_TARGET_THUMB2) Redefine with...
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(TARGET_ARM_P, TARGET_THUMB_P, TARGET_THUMB1_P, TARGET_THUMB2_P)
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(TARGET_32BIT_P, TARGET_ARM_QBIT_P, TARGET_ARM_SAT_P, TARGET_IDIV_P)
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(TARGET_HAVE_LDREX_P, TARGET_HAVE_LDREXBH_P, TARGET_HAVE_LDREXD_P)
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(TARGET_ARM_FEATURE_LDREX_P)
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(TARGET_DSP_MULTIPLY_P, TARGET_INT_SIMD_P): New macros.
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(def_or_undef_macro): New function.
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2015-05-26 Christian Bruel <christian.bruel@st.com>
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* c-common.h (builtin_define_with_int_value)
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@ -55,31 +55,49 @@ arm_lang_object_attributes_init (void)
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#define builtin_define(TXT) cpp_define (pfile, TXT)
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#define builtin_assert(TXT) cpp_assert (pfile, TXT)
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/* Define or undefine macros based on the current target. If the user does
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#pragma GCC target, we need to adjust the macros dynamically. */
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static void
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def_or_undef_macro(struct cpp_reader* pfile, const char *name, bool def_p)
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{
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if (def_p)
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cpp_define (pfile, name);
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else
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cpp_undef (pfile, name);
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}
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void
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arm_cpu_cpp_builtins (struct cpp_reader * pfile)
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{
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if (TARGET_DSP_MULTIPLY)
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builtin_define ("__ARM_FEATURE_DSP");
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if (TARGET_ARM_QBIT)
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builtin_define ("__ARM_FEATURE_QBIT");
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if (TARGET_ARM_SAT)
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builtin_define ("__ARM_FEATURE_SAT");
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int flags = target_flags;
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def_or_undef_macro (pfile, "__ARM_FEATURE_DSP",
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TARGET_DSP_MULTIPLY_P (flags));
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def_or_undef_macro (pfile, "__ARM_FEATURE_QBIT",
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TARGET_ARM_QBIT_P (flags));
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def_or_undef_macro (pfile, "__ARM_FEATURE_SAT",
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TARGET_ARM_SAT_P (flags));
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if (TARGET_CRYPTO)
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builtin_define ("__ARM_FEATURE_CRYPTO");
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if (unaligned_access)
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builtin_define ("__ARM_FEATURE_UNALIGNED");
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if (TARGET_CRC32)
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builtin_define ("__ARM_FEATURE_CRC32");
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if (TARGET_32BIT)
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builtin_define ("__ARM_32BIT_STATE");
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if (TARGET_ARM_FEATURE_LDREX)
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def_or_undef_macro (pfile, "__ARM_32BIT_STATE", TARGET_32BIT_P (flags));
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if (TARGET_ARM_FEATURE_LDREX_P (flags))
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builtin_define_with_int_value ("__ARM_FEATURE_LDREX",
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TARGET_ARM_FEATURE_LDREX);
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if ((TARGET_ARM_ARCH >= 5 && !TARGET_THUMB)
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|| TARGET_ARM_ARCH_ISA_THUMB >=2)
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builtin_define ("__ARM_FEATURE_CLZ");
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if (TARGET_INT_SIMD)
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builtin_define ("__ARM_FEATURE_SIMD32");
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TARGET_ARM_FEATURE_LDREX_P (flags));
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else
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cpp_undef (pfile, "__ARM_FEATURE_LDREX");
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def_or_undef_macro (pfile, "__ARM_FEATURE_CLZ",
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((TARGET_ARM_ARCH >= 5 && !TARGET_THUMB_P (flags))
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|| TARGET_ARM_ARCH_ISA_THUMB >=2));
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def_or_undef_macro (pfile, "__ARM_FEATURE_SIMD32", TARGET_INT_SIMD_P (flags));
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builtin_define_with_int_value ("__ARM_SIZEOF_MINIMAL_ENUM",
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flag_short_enums ? 1 : 4);
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@ -96,10 +114,14 @@ arm_cpu_cpp_builtins (struct cpp_reader * pfile)
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if (arm_arch_notm)
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builtin_define ("__ARM_ARCH_ISA_ARM");
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builtin_define ("__APCS_32__");
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if (TARGET_THUMB)
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builtin_define ("__thumb__");
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if (TARGET_THUMB2)
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builtin_define ("__thumb2__");
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def_or_undef_macro (pfile, "__thumb__", TARGET_THUMB_P (flags));
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def_or_undef_macro (pfile, "__thumb2__", TARGET_THUMB2_P (flags));
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if (TARGET_BIG_END)
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def_or_undef_macro (pfile, "__THUMBEB__", TARGET_THUMB_P (flags));
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else
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def_or_undef_macro (pfile, "__THUMBEL__", TARGET_THUMB_P (flags));
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if (TARGET_ARM_ARCH_ISA_THUMB)
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builtin_define_with_int_value ("__ARM_ARCH_ISA_THUMB",
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TARGET_ARM_ARCH_ISA_THUMB);
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@ -108,14 +130,10 @@ arm_cpu_cpp_builtins (struct cpp_reader * pfile)
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{
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builtin_define ("__ARMEB__");
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builtin_define ("__ARM_BIG_ENDIAN");
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if (TARGET_THUMB)
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builtin_define ("__THUMBEB__");
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}
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else
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{
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builtin_define ("__ARMEL__");
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if (TARGET_THUMB)
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builtin_define ("__THUMBEL__");
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}
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if (TARGET_SOFT_FLOAT)
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@ -166,11 +184,11 @@ arm_cpu_cpp_builtins (struct cpp_reader * pfile)
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builtin_define ("__ARM_PCS");
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builtin_define ("__ARM_EABI__");
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}
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if (TARGET_IDIV)
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{
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builtin_define ("__ARM_ARCH_EXT_IDIV__");
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builtin_define ("__ARM_FEATURE_IDIV");
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}
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if (inline_asm_unified)
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builtin_define ("__ARM_ASM_SYNTAX_UNIFIED__");
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def_or_undef_macro (pfile, "__ARM_ARCH_EXT_IDIV__", TARGET_IDIV_P (flags));
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def_or_undef_macro (pfile, "__ARM_FEATURE_IDIV", TARGET_IDIV_P (flags));
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def_or_undef_macro (pfile, "__ARM_ASM_SYNTAX_UNIFIED__", inline_asm_unified);
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}
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@ -2702,35 +2702,37 @@ arm_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
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static void
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arm_option_check_internal (struct gcc_options *opts)
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{
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int flags = opts->x_target_flags;
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/* Make sure that the processor choice does not conflict with any of the
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other command line choices. */
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if (TREE_TARGET_ARM (opts) && !(insn_flags & FL_NOTM))
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if (TARGET_ARM_P (flags) && !(insn_flags & FL_NOTM))
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error ("target CPU does not support ARM mode");
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/* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
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from here where no function is being compiled currently. */
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if ((TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) && TREE_TARGET_ARM (opts))
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if ((TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) && TARGET_ARM_P (flags))
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warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb");
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if (TREE_TARGET_ARM (opts) && TARGET_CALLEE_INTERWORKING)
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if (TARGET_ARM_P (flags) && TARGET_CALLEE_INTERWORKING)
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warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb");
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/* If this target is normally configured to use APCS frames, warn if they
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are turned off and debugging is turned on. */
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if (TREE_TARGET_ARM (opts)
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if (TARGET_ARM_P (flags)
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&& write_symbols != NO_DEBUG
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&& !TARGET_APCS_FRAME
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&& (TARGET_DEFAULT & MASK_APCS_FRAME))
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warning (0, "-g with -mno-apcs-frame may not give sensible debugging");
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/* iWMMXt unsupported under Thumb mode. */
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if (TREE_TARGET_THUMB (opts) && TARGET_IWMMXT)
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if (TARGET_THUMB_P (flags) && TARGET_IWMMXT)
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error ("iWMMXt unsupported under Thumb mode");
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if (TARGET_HARD_TP && TREE_TARGET_THUMB1 (opts))
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if (TARGET_HARD_TP && TARGET_THUMB1_P (flags))
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error ("can not use -mtp=cp15 with 16-bit Thumb");
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if (TREE_TARGET_THUMB (opts) && TARGET_VXWORKS_RTP && flag_pic)
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if (TARGET_THUMB_P (flags) && TARGET_VXWORKS_RTP && flag_pic)
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{
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error ("RTP PIC is incompatible with Thumb");
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flag_pic = 0;
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@ -2739,7 +2741,7 @@ arm_option_check_internal (struct gcc_options *opts)
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/* We only support -mslow-flash-data on armv7-m targets. */
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if (target_slow_flash_data
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&& ((!(arm_arch7 && !arm_arch_notm) && !arm_arch7em)
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|| (TREE_TARGET_THUMB1 (opts) || flag_pic || TARGET_NEON)))
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|| (TARGET_THUMB1_P (flags) || flag_pic || TARGET_NEON)))
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error ("-mslow-flash-data only supports non-pic code on armv7-m targets");
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}
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@ -2747,9 +2749,11 @@ arm_option_check_internal (struct gcc_options *opts)
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static void
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arm_option_params_internal (struct gcc_options *opts)
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{
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int flags = opts->x_target_flags;
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/* If we are not using the default (ARM mode) section anchor offset
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ranges, then set the correct ranges now. */
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if (TREE_TARGET_THUMB1 (opts))
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if (TARGET_THUMB1_P (flags))
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{
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/* Thumb-1 LDR instructions cannot have negative offsets.
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Permissible positive offset ranges are 5-bit (for byte loads),
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@ -2759,7 +2763,7 @@ arm_option_params_internal (struct gcc_options *opts)
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targetm.min_anchor_offset = 0;
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targetm.max_anchor_offset = 127;
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}
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else if (TREE_TARGET_THUMB2 (opts))
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else if (TARGET_THUMB2_P (flags))
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{
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/* The minimum is set such that the total size of the block
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for a particular anchor is 248 + 1 + 4095 bytes, which is
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@ -2780,7 +2784,7 @@ arm_option_params_internal (struct gcc_options *opts)
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max_insns_skipped = 6;
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/* For THUMB2, we limit the conditional sequence to one IT block. */
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if (TREE_TARGET_THUMB2 (opts))
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if (TARGET_THUMB2_P (flags))
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max_insns_skipped = opts->x_arm_restrict_it ? 1 : 4;
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}
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else
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@ -2792,13 +2796,13 @@ static void
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arm_option_override_internal (struct gcc_options *opts,
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struct gcc_options *opts_set)
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{
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if (TREE_TARGET_THUMB (opts) && !(insn_flags & FL_THUMB))
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if (TARGET_THUMB_P (opts->x_target_flags) && !(insn_flags & FL_THUMB))
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{
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warning (0, "target CPU does not support THUMB instructions");
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opts->x_target_flags &= ~MASK_THUMB;
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}
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if (TARGET_APCS_FRAME && TREE_TARGET_THUMB (opts))
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if (TARGET_APCS_FRAME && TARGET_THUMB_P (opts->x_target_flags))
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{
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/* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */
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opts->x_target_flags &= ~MASK_APCS_FRAME;
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@ -2806,16 +2810,16 @@ arm_option_override_internal (struct gcc_options *opts,
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/* Callee super interworking implies thumb interworking. Adding
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this to the flags here simplifies the logic elsewhere. */
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if (TREE_TARGET_THUMB (opts) && TARGET_CALLEE_INTERWORKING)
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if (TARGET_THUMB_P (opts->x_target_flags) && TARGET_CALLEE_INTERWORKING)
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opts->x_target_flags |= MASK_INTERWORK;
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if (! opts_set->x_arm_restrict_it)
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opts->x_arm_restrict_it = arm_arch8;
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if (!TREE_TARGET_THUMB2 (opts))
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if (!TARGET_THUMB2_P (opts->x_target_flags))
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opts->x_arm_restrict_it = 0;
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if (TREE_TARGET_THUMB1 (opts))
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if (TARGET_THUMB1_P (opts->x_target_flags))
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{
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/* Don't warn since it's on by default in -O2. */
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opts->x_flag_schedule_insns = 0;
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@ -2823,7 +2827,8 @@ arm_option_override_internal (struct gcc_options *opts,
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/* Disable shrink-wrap when optimizing function for size, since it tends to
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generate additional returns. */
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if (optimize_function_for_size_p (cfun) && TREE_TARGET_THUMB2 (opts))
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if (optimize_function_for_size_p (cfun)
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&& TARGET_THUMB2_P (opts->x_target_flags))
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opts->x_flag_shrink_wrap = false;
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/* In Thumb1 mode, we emit the epilogue in RTL, but the last insn
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@ -2834,12 +2839,12 @@ arm_option_override_internal (struct gcc_options *opts,
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finding out about it. Therefore, disable fipa-ra in Thumb1 mode.
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TODO: Accurately model clobbers for epilogue_insns and reenable
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fipa-ra. */
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if (TREE_TARGET_THUMB1 (opts))
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if (TARGET_THUMB1_P (opts->x_target_flags))
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opts->x_flag_ipa_ra = 0;
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/* Thumb2 inline assembly code should always use unified syntax.
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This will apply to ARM and Thumb1 eventually. */
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opts->x_inline_asm_unified = TREE_TARGET_THUMB2 (opts);
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opts->x_inline_asm_unified = TARGET_THUMB2_P (opts->x_target_flags);
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}
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/* Fix up any incompatible options that the user has specified. */
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@ -128,12 +128,10 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
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#endif
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/* Tree Target Specification. */
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#define TREE_TARGET_THUMB(opts) (TARGET_THUMB_P (opts->x_target_flags))
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#define TREE_TARGET_ARM(opts) (!TARGET_THUMB_P (opts->x_target_flags))
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#define TREE_TARGET_THUMB1(opts) (TARGET_THUMB_P (opts->x_target_flags) \
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&& !arm_arch_thumb2)
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#define TREE_TARGET_THUMB2(opts) (TARGET_THUMB_P (opts->x_target_flags) \
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&& arm_arch_thumb2)
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#define TARGET_ARM_P(flags) (!TARGET_THUMB_P (flags))
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#define TARGET_THUMB1_P(flags) (TARGET_THUMB_P (flags) && !arm_arch_thumb2)
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#define TARGET_THUMB2_P(flags) (TARGET_THUMB_P (flags) && arm_arch_thumb2)
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/* Run-time Target Specification. */
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#define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
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/* Use hardware floating point instructions. */
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@ -162,6 +160,8 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
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#define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2)
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/* Arm or Thumb-2 32-bit code. */
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#define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2)
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#define TARGET_32BIT_P(flags) (TARGET_ARM_P (flags) \
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|| arm_arch_thumb2)
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/* 32-bit Thumb-2 code. */
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#define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
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/* Thumb-1 only. */
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@ -216,17 +216,21 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
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&& TARGET_VFP && arm_fpu_desc->neon)
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/* Q-bit is present. */
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#define TARGET_ARM_QBIT \
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(TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7))
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#define TARGET_ARM_QBIT_P(flags) \
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(TARGET_32BIT_P (flags) && arm_arch5e && (arm_arch_notm || arm_arch7))
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#define TARGET_ARM_QBIT TARGET_ARM_QBIT_P(target_flags)
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/* Saturation operation, e.g. SSAT. */
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#define TARGET_ARM_SAT \
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(TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7))
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#define TARGET_ARM_SAT_P(flags) \
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(TARGET_32BIT_P (flags) && arm_arch6 && (arm_arch_notm || arm_arch7))
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#define TARGET_ARM_SAT TARGET_ARM_SAT_P(target_flags)
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/* "DSP" multiply instructions, eg. SMULxy. */
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#define TARGET_DSP_MULTIPLY \
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(TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em))
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#define TARGET_DSP_MULTIPLY_P(flags) \
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(TARGET_32BIT_P (flags) && arm_arch5e && (arm_arch_notm || arm_arch7em))
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#define TARGET_DSP_MULTIPLY TARGET_DSP_MULTIPLY_P(target_flags)
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/* Integer SIMD instructions, and extend-accumulate instructions. */
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#define TARGET_INT_SIMD \
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(TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em))
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#define TARGET_INT_SIMD_P(flags) \
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(TARGET_32BIT_P (flags) && arm_arch6 && (arm_arch_notm || arm_arch7em))
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#define TARGET_INT_SIMD TARGET_INT_SIMD_P(target_flags)
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/* Should MOVW/MOVT be used in preference to a constant pool. */
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#define TARGET_USE_MOVT \
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||||
@ -249,21 +253,30 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
|
||||
#define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)
|
||||
|
||||
/* Nonzero if this chip supports ldrex and strex */
|
||||
#define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7)
|
||||
#define TARGET_HAVE_LDREX_P(flags) ((arm_arch6 && TARGET_ARM_P (flags)) \
|
||||
|| arm_arch7)
|
||||
#define TARGET_HAVE_LDREX TARGET_HAVE_LDREX_P (target_flags)
|
||||
|
||||
/* Nonzero if this chip supports ldrex{bh} and strex{bh}. */
|
||||
#define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) || arm_arch7)
|
||||
#define TARGET_HAVE_LDREXBH_P(flags) ((arm_arch6k && TARGET_ARM_P (flags)) \
|
||||
|| arm_arch7)
|
||||
#define TARGET_HAVE_LDREXBH TARGET_HAVE_LDREXBH_P (target_flags)
|
||||
|
||||
/* Nonzero if this chip supports ldrexd and strexd. */
|
||||
#define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) || arm_arch7) \
|
||||
&& arm_arch_notm)
|
||||
#define TARGET_HAVE_LDREXD_P(flags) (((arm_arch6k && TARGET_ARM_P (flags)) \
|
||||
|| arm_arch7) && arm_arch_notm)
|
||||
#define TARGET_HAVE_LDREXD TARGET_HAVE_LDREXD_P (target_flags)
|
||||
|
||||
|
||||
/* Nonzero if this chip supports load-acquire and store-release. */
|
||||
#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8)
|
||||
|
||||
/* Nonzero if integer division instructions supported. */
|
||||
#define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \
|
||||
|| (TARGET_THUMB2 && arm_arch_thumb_hwdiv))
|
||||
#define TARGET_IDIV_P(flags) ((TARGET_ARM_P (flags) && arm_arch_arm_hwdiv) \
|
||||
|| (TARGET_THUMB2_P (flags) \
|
||||
&& arm_arch_thumb_hwdiv))
|
||||
#define TARGET_IDIV TARGET_IDIV_P (target_flags)
|
||||
|
||||
|
||||
/* Nonzero if disallow volatile memory access in IT block. */
|
||||
#define TARGET_NO_VOLATILE_CE (arm_arch_no_volatile_ce)
|
||||
@ -2189,6 +2202,11 @@ extern int making_const_table;
|
||||
| (TARGET_HAVE_LDREXBH ? 3 : 0) \
|
||||
| (TARGET_HAVE_LDREXD ? 8 : 0))
|
||||
|
||||
#define TARGET_ARM_FEATURE_LDREX_P(flags) \
|
||||
((TARGET_HAVE_LDREX_P (flags) ? 4 : 0) \
|
||||
| (TARGET_HAVE_LDREXBH_P (flags) ? 3 : 0) \
|
||||
| (TARGET_HAVE_LDREXD_P (flags) ? 8 : 0))
|
||||
|
||||
/* Set as a bit mask indicating the available widths of hardware floating
|
||||
point types. Where bit 1 indicates 16-bit support, bit 2 indicates
|
||||
32-bit support, bit 3 indicates 64-bit support. */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user