[AArch64] Make call insns record the callee's arm_pcs
At the moment we rely on SYMBOL_REF_DECL to get the ABI of the callee of a call insn, falling back to the default ABI if the decl isn't available. I think it'd be cleaner to attach the ABI directly to the call instruction instead, which would also have the very minor benefit of handling indirect calls more efficiently. 2019-10-01 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/aarch64-protos.h (aarch64_expand_call): Take an extra callee_abi argument. * config/aarch64/aarch64.c (aarch64_expand_call): Likewise. Insert a CALLEE_ABI unspec into the call pattern as the second element in the PARALLEL. (aarch64_simd_call_p): Delete. (aarch64_insn_callee_abi): Get the arm_pcs of the callee from the new CALLEE_ABI element of the PARALLEL. (aarch64_init_cumulative_args): Get the arm_pcs of the callee from the function type, if given. (aarch64_function_arg_advance): Handle ARM_PCS_SIMD. (aarch64_function_arg): Likewise. Return the arm_pcs of the callee when passed the function_arg_info end marker. (aarch64_output_mi_thunk): Pass the arm_pcs of the callee as the final argument of gen_sibcall. * config/aarch64/aarch64.md (UNSPEC_CALLEE_ABI): New unspec. (call): Make operand 2 a const_int_operand and pass it to expand_call. Wrap it in an UNSPEC_CALLEE_ABI unspec for the dummy define_expand pattern. (call_value): Likewise operand 3. (sibcall): Likewise operand 2. Place the unspec before rather than after the return. (sibcall_value): Likewise operand 3. (*call_insn, *call_value_insn): Include an UNSPEC_CALLEE_ABI. (tlsgd_small_<mode>, *tlsgd_small_<mode>): Likewise. (*sibcall_insn, *sibcall_value_insn): Likewise. Remove empty constraint strings. (untyped_call): Pass const0_rtx as the callee ABI to gen_call. gcc/testsuite/ * gcc.target/aarch64/torture/simd-abi-10.c: New test. * gcc.target/aarch64/torture/simd-abi-11.c: Likewise. From-SVN: r276391
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
810f316dd6
commit
08cc4d925f
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@ -1,3 +1,34 @@
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2019-10-01 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/aarch64-protos.h (aarch64_expand_call): Take an
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extra callee_abi argument.
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* config/aarch64/aarch64.c (aarch64_expand_call): Likewise.
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Insert a CALLEE_ABI unspec into the call pattern as the second
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element in the PARALLEL.
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(aarch64_simd_call_p): Delete.
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(aarch64_insn_callee_abi): Get the arm_pcs of the callee from
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the new CALLEE_ABI element of the PARALLEL.
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(aarch64_init_cumulative_args): Get the arm_pcs of the callee
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from the function type, if given.
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(aarch64_function_arg_advance): Handle ARM_PCS_SIMD.
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(aarch64_function_arg): Likewise. Return the arm_pcs of the callee
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when passed the function_arg_info end marker.
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(aarch64_output_mi_thunk): Pass the arm_pcs of the callee as the
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final argument of gen_sibcall.
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* config/aarch64/aarch64.md (UNSPEC_CALLEE_ABI): New unspec.
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(call): Make operand 2 a const_int_operand and pass it to expand_call.
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Wrap it in an UNSPEC_CALLEE_ABI unspec for the dummy define_expand
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pattern.
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(call_value): Likewise operand 3.
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(sibcall): Likewise operand 2. Place the unspec before rather than
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after the return.
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(sibcall_value): Likewise operand 3.
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(*call_insn, *call_value_insn): Include an UNSPEC_CALLEE_ABI.
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(tlsgd_small_<mode>, *tlsgd_small_<mode>): Likewise.
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(*sibcall_insn, *sibcall_value_insn): Likewise. Remove empty
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constraint strings.
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(untyped_call): Pass const0_rtx as the callee ABI to gen_call.
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2019-10-01 Richard Sandiford <richard.sandiford@arm.com>
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* regs.h (HARD_REGNO_CALLER_SAVE_MODE): Update call to
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@ -468,7 +468,7 @@ bool aarch64_const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT,
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bool aarch64_constant_address_p (rtx);
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bool aarch64_emit_approx_div (rtx, rtx, rtx);
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bool aarch64_emit_approx_sqrt (rtx, rtx, bool);
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void aarch64_expand_call (rtx, rtx, bool);
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void aarch64_expand_call (rtx, rtx, rtx, bool);
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bool aarch64_expand_cpymem (rtx *);
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bool aarch64_float_const_zero_rtx_p (rtx);
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bool aarch64_float_const_rtx_p (rtx);
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@ -1872,37 +1872,17 @@ aarch64_reg_save_mode (tree fndecl, unsigned regno)
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: (aarch64_simd_decl_p (fndecl) ? E_TFmode : E_DFmode);
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}
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/* Return true if the instruction is a call to a SIMD function, false
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if it is not a SIMD function or if we do not know anything about
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the function. */
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static bool
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aarch64_simd_call_p (const rtx_insn *insn)
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{
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rtx symbol;
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rtx call;
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tree fndecl;
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gcc_assert (CALL_P (insn));
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call = get_call_rtx_from (insn);
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symbol = XEXP (XEXP (call, 0), 0);
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if (GET_CODE (symbol) != SYMBOL_REF)
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return false;
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fndecl = SYMBOL_REF_DECL (symbol);
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if (!fndecl)
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return false;
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return aarch64_simd_decl_p (fndecl);
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}
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/* Implement TARGET_INSN_CALLEE_ABI. */
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const predefined_function_abi &
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aarch64_insn_callee_abi (const rtx_insn *insn)
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{
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if (aarch64_simd_call_p (insn))
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return aarch64_simd_abi ();
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return default_function_abi;
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rtx pat = PATTERN (insn);
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gcc_assert (GET_CODE (pat) == PARALLEL);
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rtx unspec = XVECEXP (pat, 0, 1);
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gcc_assert (GET_CODE (unspec) == UNSPEC
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&& XINT (unspec, 1) == UNSPEC_CALLEE_ABI);
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return function_abis[INTVAL (XVECEXP (unspec, 0, 0))];
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}
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/* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. The callee only saves
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@ -4847,10 +4827,11 @@ static rtx
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aarch64_function_arg (cumulative_args_t pcum_v, const function_arg_info &arg)
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{
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CUMULATIVE_ARGS *pcum = get_cumulative_args (pcum_v);
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gcc_assert (pcum->pcs_variant == ARM_PCS_AAPCS64);
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gcc_assert (pcum->pcs_variant == ARM_PCS_AAPCS64
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|| pcum->pcs_variant == ARM_PCS_SIMD);
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if (arg.end_marker_p ())
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return NULL_RTX;
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return gen_int_mode (pcum->pcs_variant, DImode);
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aarch64_layout_arg (pcum_v, arg.mode, arg.type, arg.named);
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return pcum->aapcs_reg;
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@ -4858,16 +4839,19 @@ aarch64_function_arg (cumulative_args_t pcum_v, const function_arg_info &arg)
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void
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aarch64_init_cumulative_args (CUMULATIVE_ARGS *pcum,
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const_tree fntype ATTRIBUTE_UNUSED,
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rtx libname ATTRIBUTE_UNUSED,
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const_tree fndecl ATTRIBUTE_UNUSED,
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unsigned n_named ATTRIBUTE_UNUSED)
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const_tree fntype,
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rtx libname ATTRIBUTE_UNUSED,
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const_tree fndecl ATTRIBUTE_UNUSED,
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unsigned n_named ATTRIBUTE_UNUSED)
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{
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pcum->aapcs_ncrn = 0;
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pcum->aapcs_nvrn = 0;
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pcum->aapcs_nextncrn = 0;
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pcum->aapcs_nextnvrn = 0;
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pcum->pcs_variant = ARM_PCS_AAPCS64;
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if (fntype)
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pcum->pcs_variant = (arm_pcs) fntype_abi (fntype).id ();
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else
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pcum->pcs_variant = ARM_PCS_AAPCS64;
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pcum->aapcs_reg = NULL_RTX;
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pcum->aapcs_arg_processed = false;
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pcum->aapcs_stack_words = 0;
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@ -4892,7 +4876,8 @@ aarch64_function_arg_advance (cumulative_args_t pcum_v,
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const function_arg_info &arg)
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{
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CUMULATIVE_ARGS *pcum = get_cumulative_args (pcum_v);
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if (pcum->pcs_variant == ARM_PCS_AAPCS64)
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if (pcum->pcs_variant == ARM_PCS_AAPCS64
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|| pcum->pcs_variant == ARM_PCS_SIMD)
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{
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aarch64_layout_arg (pcum_v, arg.mode, arg.type, arg.named);
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gcc_assert ((pcum->aapcs_reg != NULL_RTX)
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@ -6921,7 +6906,8 @@ aarch64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
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}
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funexp = XEXP (DECL_RTL (function), 0);
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funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
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insn = emit_call_insn (gen_sibcall (funexp, const0_rtx, NULL_RTX));
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rtx callee_abi = gen_int_mode (fndecl_abi (function).id (), DImode);
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insn = emit_call_insn (gen_sibcall (funexp, const0_rtx, callee_abi));
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SIBLING_CALL_P (insn) = 1;
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insn = get_insns ();
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@ -7999,11 +7985,12 @@ aarch64_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
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RESULT is the register in which the result is returned. It's NULL for
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"call" and "sibcall".
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MEM is the location of the function call.
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CALLEE_ABI is a const_int that gives the arm_pcs of the callee.
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SIBCALL indicates whether this function call is normal call or sibling call.
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It will generate different pattern accordingly. */
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void
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aarch64_expand_call (rtx result, rtx mem, bool sibcall)
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aarch64_expand_call (rtx result, rtx mem, rtx callee_abi, bool sibcall)
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{
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rtx call, callee, tmp;
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rtvec vec;
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@ -8033,7 +8020,11 @@ aarch64_expand_call (rtx result, rtx mem, bool sibcall)
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else
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tmp = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNUM));
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vec = gen_rtvec (2, call, tmp);
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gcc_assert (CONST_INT_P (callee_abi));
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callee_abi = gen_rtx_UNSPEC (DImode, gen_rtvec (1, callee_abi),
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UNSPEC_CALLEE_ABI);
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vec = gen_rtvec (3, call, callee_abi, tmp);
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call = gen_rtx_PARALLEL (VOIDmode, vec);
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aarch64_emit_call_insn (call);
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@ -130,6 +130,7 @@
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UNSPEC_AUTIB1716
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UNSPEC_AUTIASP
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UNSPEC_AUTIBSP
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UNSPEC_CALLEE_ABI
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UNSPEC_CASESI
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UNSPEC_CRC32B
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UNSPEC_CRC32CB
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@ -913,14 +914,15 @@
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;; -------------------------------------------------------------------
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(define_expand "call"
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[(parallel [(call (match_operand 0 "memory_operand")
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(match_operand 1 "general_operand"))
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(use (match_operand 2 "" ""))
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(clobber (reg:DI LR_REGNUM))])]
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[(parallel
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[(call (match_operand 0 "memory_operand")
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(match_operand 1 "general_operand"))
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(unspec:DI [(match_operand 2 "const_int_operand")] UNSPEC_CALLEE_ABI)
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(clobber (reg:DI LR_REGNUM))])]
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""
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"
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{
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aarch64_expand_call (NULL_RTX, operands[0], false);
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aarch64_expand_call (NULL_RTX, operands[0], operands[2], false);
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DONE;
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}"
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)
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@ -928,6 +930,7 @@
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(define_insn "*call_insn"
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[(call (mem:DI (match_operand:DI 0 "aarch64_call_insn_operand" "r, Usf"))
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(match_operand 1 "" ""))
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(unspec:DI [(match_operand:DI 2 "const_int_operand")] UNSPEC_CALLEE_ABI)
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(clobber (reg:DI LR_REGNUM))]
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""
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"@
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@ -937,15 +940,16 @@
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)
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(define_expand "call_value"
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[(parallel [(set (match_operand 0 "" "")
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(call (match_operand 1 "memory_operand")
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(match_operand 2 "general_operand")))
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(use (match_operand 3 "" ""))
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(clobber (reg:DI LR_REGNUM))])]
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[(parallel
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[(set (match_operand 0 "")
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(call (match_operand 1 "memory_operand")
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(match_operand 2 "general_operand")))
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(unspec:DI [(match_operand 3 "const_int_operand")] UNSPEC_CALLEE_ABI)
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(clobber (reg:DI LR_REGNUM))])]
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""
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"
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{
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aarch64_expand_call (operands[0], operands[1], false);
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aarch64_expand_call (operands[0], operands[1], operands[3], false);
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DONE;
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}"
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)
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@ -954,6 +958,7 @@
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[(set (match_operand 0 "" "")
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(call (mem:DI (match_operand:DI 1 "aarch64_call_insn_operand" "r, Usf"))
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(match_operand 2 "" "")))
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(unspec:DI [(match_operand:DI 3 "const_int_operand")] UNSPEC_CALLEE_ABI)
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(clobber (reg:DI LR_REGNUM))]
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""
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"@
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@ -963,33 +968,36 @@
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)
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(define_expand "sibcall"
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[(parallel [(call (match_operand 0 "memory_operand")
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(match_operand 1 "general_operand"))
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(return)
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(use (match_operand 2 "" ""))])]
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[(parallel
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[(call (match_operand 0 "memory_operand")
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(match_operand 1 "general_operand"))
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(unspec:DI [(match_operand 2 "const_int_operand")] UNSPEC_CALLEE_ABI)
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(return)])]
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""
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{
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aarch64_expand_call (NULL_RTX, operands[0], true);
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aarch64_expand_call (NULL_RTX, operands[0], operands[2], true);
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DONE;
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}
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)
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(define_expand "sibcall_value"
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[(parallel [(set (match_operand 0 "" "")
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(call (match_operand 1 "memory_operand")
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(match_operand 2 "general_operand")))
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(return)
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(use (match_operand 3 "" ""))])]
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[(parallel
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[(set (match_operand 0 "")
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(call (match_operand 1 "memory_operand")
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(match_operand 2 "general_operand")))
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(unspec:DI [(match_operand 3 "const_int_operand")] UNSPEC_CALLEE_ABI)
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(return)])]
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""
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{
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aarch64_expand_call (operands[0], operands[1], true);
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aarch64_expand_call (operands[0], operands[1], operands[3], true);
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DONE;
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}
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)
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(define_insn "*sibcall_insn"
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[(call (mem:DI (match_operand:DI 0 "aarch64_call_insn_operand" "Ucs, Usf"))
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(match_operand 1 "" ""))
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(match_operand 1 ""))
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(unspec:DI [(match_operand:DI 2 "const_int_operand")] UNSPEC_CALLEE_ABI)
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(return)]
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"SIBLING_CALL_P (insn)"
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"@
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@ -999,10 +1007,11 @@
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)
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(define_insn "*sibcall_value_insn"
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[(set (match_operand 0 "" "")
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[(set (match_operand 0 "")
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(call (mem:DI
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(match_operand:DI 1 "aarch64_call_insn_operand" "Ucs, Usf"))
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(match_operand 2 "" "")))
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(match_operand 2 "")))
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(unspec:DI [(match_operand:DI 3 "const_int_operand")] UNSPEC_CALLEE_ABI)
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(return)]
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"SIBLING_CALL_P (insn)"
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"@
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@ -1022,7 +1031,9 @@
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{
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int i;
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emit_call_insn (gen_call (operands[0], const0_rtx, NULL));
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/* Untyped calls always use the default ABI. It's only possible to use
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ABI variants if we know the type of the target function. */
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emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
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for (i = 0; i < XVECLEN (operands[2], 0); i++)
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{
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@ -6682,6 +6693,7 @@
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(define_expand "tlsgd_small_<mode>"
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[(parallel [(set (match_operand 0 "register_operand")
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(call (mem:DI (match_dup 2)) (const_int 1)))
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(unspec:DI [(const_int 0)] UNSPEC_CALLEE_ABI)
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(unspec:DI [(match_operand:PTR 1 "aarch64_valid_symref")] UNSPEC_GOTSMALLTLS)
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(clobber (reg:DI LR_REGNUM))])]
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""
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@ -6692,6 +6704,7 @@
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(define_insn "*tlsgd_small_<mode>"
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[(set (match_operand 0 "register_operand" "")
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(call (mem:DI (match_operand:DI 2 "" "")) (const_int 1)))
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(unspec:DI [(const_int 0)] UNSPEC_CALLEE_ABI)
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(unspec:DI [(match_operand:PTR 1 "aarch64_valid_symref" "S")] UNSPEC_GOTSMALLTLS)
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(clobber (reg:DI LR_REGNUM))
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]
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@ -1,3 +1,8 @@
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2019-10-01 Richard Sandiford <richard.sandiford@arm.com>
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* gcc.target/aarch64/torture/simd-abi-10.c: New test.
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* gcc.target/aarch64/torture/simd-abi-11.c: Likewise.
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2019-09-30 Yuliang Wang <yuliang.wang@arm.com>
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* gcc.dg/vect/vect-sdiv-pow2-1.c: New test.
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@ -0,0 +1,14 @@
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/* { dg-do compile } */
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int __attribute__((aarch64_vector_pcs)) (*callee) (void);
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|
||||
int __attribute__ ((aarch64_vector_pcs))
|
||||
caller (int *x)
|
||||
{
|
||||
return callee () + 1;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-not {\tstp\tq} } } */
|
||||
/* { dg-final { scan-assembler-not {\tldp\tq} } } */
|
||||
/* { dg-final { scan-assembler-not {\tstr\tq} } } */
|
||||
/* { dg-final { scan-assembler-not {\tldr\tq} } } */
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
/* { dg-do compile } */
|
||||
|
||||
int (*callee) (void);
|
||||
|
||||
int __attribute__ ((aarch64_vector_pcs))
|
||||
caller (int *x)
|
||||
{
|
||||
return callee () + 1;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler {\sstp\tq8, q9} } } */
|
||||
/* { dg-final { scan-assembler {\sstp\tq10, q11} } } */
|
||||
/* { dg-final { scan-assembler {\sstp\tq12, q13} } } */
|
||||
/* { dg-final { scan-assembler {\sstp\tq14, q15} } } */
|
||||
/* { dg-final { scan-assembler {\sstp\tq16, q17} } } */
|
||||
/* { dg-final { scan-assembler {\sstp\tq18, q19} } } */
|
||||
/* { dg-final { scan-assembler {\sstp\tq20, q21} } } */
|
||||
/* { dg-final { scan-assembler {\sstp\tq22, q23} } } */
|
||||
/* { dg-final { scan-assembler {\sldp\tq8, q9} } } */
|
||||
/* { dg-final { scan-assembler {\sldp\tq10, q11} } } */
|
||||
/* { dg-final { scan-assembler {\sldp\tq12, q13} } } */
|
||||
/* { dg-final { scan-assembler {\sldp\tq14, q15} } } */
|
||||
/* { dg-final { scan-assembler {\sldp\tq16, q17} } } */
|
||||
/* { dg-final { scan-assembler {\sldp\tq18, q19} } } */
|
||||
/* { dg-final { scan-assembler {\sldp\tq20, q21} } } */
|
||||
/* { dg-final { scan-assembler {\sldp\tq22, q23} } } */
|
||||
Loading…
Reference in New Issue