alpha.c: Fix comment typos.
* config/alpha/alpha.c: Fix comment typos. * config/alpha/elf.h: Likewise. * config/arm/arm.c: Likewise. * config/arm/arm.h: Likewise. * config/arm/arm.md: Likewise. * config/arm/t-arm-coff: Likewise. * config/arm/t-strongarm-pe: Likewise. * config/arm/xscale-elf.h: Likewise. * config/avr/avr.h: Likewise. From-SVN: r68800
This commit is contained in:
Kazu Hirata
Kazu Hirata
parent
2a2ecc33a8
commit
093354e08f
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@ -1,3 +1,15 @@
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2003-07-01 Kazu Hirata <kazu@cs.umass.edu>
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* config/alpha/alpha.c: Fix comment typos.
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* config/alpha/elf.h: Likewise.
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* config/arm/arm.c: Likewise.
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* config/arm/arm.h: Likewise.
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* config/arm/arm.md: Likewise.
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* config/arm/t-arm-coff: Likewise.
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* config/arm/t-strongarm-pe: Likewise.
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* config/arm/xscale-elf.h: Likewise.
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* config/avr/avr.h: Likewise.
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2003-07-01 Jeff Law <law@redhat.com>
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* stmt.c (any_pending_cleanups): Remove another redundant test.
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@ -974,7 +974,7 @@ call_operand (rtx op, enum machine_mode mode)
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{
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if (TARGET_ABI_OSF)
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{
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/* Disallow virtual registers to cope with pathalogical test cases
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/* Disallow virtual registers to cope with pathological test cases
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such as compile/930117-1.c in which the virtual reg decomposes
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to the frame pointer. Which is a hard reg that is not $27. */
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return (REGNO (op) == 27 || REGNO (op) > LAST_VIRTUAL_REGISTER);
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@ -2006,7 +2006,7 @@ split_small_symbolic_operand (rtx x)
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that we've marked with gpdisp relocs, since those have to stay in
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1-1 correspondence with one another.
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Techinically we could copy them if we could set up a mapping from one
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Technically we could copy them if we could set up a mapping from one
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sequence number to another, across the set of insns to be duplicated.
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This seems overly complicated and error-prone since interblock motion
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from sched-ebb could move one of the pair of insns to a different block. */
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@ -7253,7 +7253,7 @@ alpha_expand_prologue (void)
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=> alpha_procedure_type != PT_NULL,
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so when we are not setting the bit here, we are guaranteed to
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have emited an FRP frame pointer update just before. */
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have emitted an FRP frame pointer update just before. */
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RTX_FRAME_RELATED_P (seq) = ! frame_pointer_needed;
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}
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}
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@ -8267,7 +8267,7 @@ alpha_handle_trap_shadows (void)
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}
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/* Alpha can only issue instruction groups simultaneously if they are
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suitibly aligned. This is very processor-specific. */
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suitably aligned. This is very processor-specific. */
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enum alphaev4_pipe {
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EV4_STOP = 0,
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@ -8857,7 +8857,7 @@ alpha_elf_select_rtx_section (enum machine_mode mode, rtx x,
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unsigned HOST_WIDE_INT align)
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{
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if (TARGET_SMALL_DATA && GET_MODE_SIZE (mode) <= g_switch_value)
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/* ??? Consider using mergable sdata sections. */
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/* ??? Consider using mergeable sdata sections. */
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sdata_section ();
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else
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default_elf_select_rtx_section (mode, x, align);
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@ -149,7 +149,7 @@ do { \
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not defined, the default value is `BIGGEST_ALIGNMENT'.
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This value is really 2^63. Since gcc figures the alignment in bits,
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we could only potentially get to 2^60 on suitible hosts. Due to other
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we could only potentially get to 2^60 on suitable hosts. Due to other
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considerations in varasm, we must restrict this to what fits in an int. */
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#undef MAX_OFILE_ALIGNMENT
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@ -2085,7 +2085,7 @@ arm_va_arg (tree valist, tree type)
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tree t;
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/* Maintain 64-bit alignment of the valist pointer by
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contructing: valist = ((valist + (8 - 1)) & -8). */
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constructing: valist = ((valist + (8 - 1)) & -8). */
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minus_eight = build_int_2 (- (IWMMXT_ALIGNMENT / BITS_PER_UNIT), -1);
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t = build_int_2 ((IWMMXT_ALIGNMENT / BITS_PER_UNIT) - 1, 0);
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t = build (PLUS_EXPR, TREE_TYPE (valist), valist, t);
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@ -6124,7 +6124,7 @@ get_jump_table_size (rtx insn)
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/* Move a minipool fix MP from its current location to before MAX_MP.
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If MAX_MP is NULL, then MP doesn't need moving, but the addressing
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contrains may need updating. */
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constraints may need updating. */
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static Mnode *
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move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp,
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HOST_WIDE_INT max_address)
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@ -6747,7 +6747,7 @@ push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc,
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Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
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#ifdef AOF_ASSEMBLER
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/* PIC symbol refereneces need to be converted into offsets into the
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/* PIC symbol references need to be converted into offsets into the
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based area. */
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/* XXX This shouldn't be done here. */
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if (flag_pic && GET_CODE (value) == SYMBOL_REF)
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@ -9490,13 +9490,13 @@ arm_print_operand (FILE *stream, rtx x, int code)
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In a pair of registers containing a DI or DF value the 'Q'
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operand returns the register number of the register containing
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the least signficant part of the value. The 'R' operand returns
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the least significant part of the value. The 'R' operand returns
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the register number of the register containing the most
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significant part of the value.
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The 'H' operand returns the higher of the two register numbers.
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On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
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same as the 'Q' operand, since the most signficant part of the
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same as the 'Q' operand, since the most significant part of the
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value is held in the lower number register. The reverse is true
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on systems where WORDS_BIG_ENDIAN is false.
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@ -11702,7 +11702,7 @@ thumb_unexpanded_epilogue (void)
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high_regs_pushed++;
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/* The prolog may have pushed some high registers to use as
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work registers. eg the testuite file:
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work registers. eg the testsuite file:
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gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
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compiles to produce:
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push {r4, r5, r6, r7, lr}
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@ -1024,7 +1024,7 @@ extern const char * structure_size_string;
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/* The number of (integer) argument register available. */
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#define NUM_ARG_REGS 4
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/* Return the regiser number of the N'th (integer) argument. */
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/* Return the register number of the N'th (integer) argument. */
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#define ARG_REGISTER(N) (N - 1)
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#if 0 /* FIXME: The ARM backend has special code to handle structure
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@ -1726,7 +1726,7 @@
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/* A Trick, since we are setting the bottom bits in the word,
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we can shift operand[3] up, operand[0] down, OR them together
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and rotate the result back again. This takes 3 insns, and
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the third might be mergable into another op. */
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the third might be mergeable into another op. */
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/* The shift up copes with the possibility that operand[3] is
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wider than the bitfield. */
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rtx op0 = gen_reg_rtx (SImode);
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@ -28,7 +28,7 @@ EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o
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LIBGCC = stmp-multilib
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INSTALL_LIBGCC = install-multilib
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# Currently there is a bug somwehere in GCC's alias analysis
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# Currently there is a bug somewhere in GCC's alias analysis
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# or scheduling code that is breaking _fpmul_parts in fp-bit.c.
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# Disabling function inlining is a workaround for this problem.
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TARGET_LIBGCC2_CFLAGS = -Dinhibit_libc -fno-inline
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@ -32,7 +32,7 @@ EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o
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LIBGCC = stmp-multilib
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INSTALL_LIBGCC = install-multilib
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# Currently there is a bug somwehere in GCC's alias analysis
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# Currently there is a bug somewhere in GCC's alias analysis
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# or scheduling code that is breaking _fpmul_parts in fp-bit.c.
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# Disabling function inlining is a workaround for this problem.
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TARGET_LIBGCC2_CFLAGS = -Dinhibit_libc -fno-inline
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@ -32,7 +32,7 @@
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the assembler:
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-mfpu=softvfp This is the default. It indicates thats doubles are
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stored in a format compatable with the VFP
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stored in a format compatible with the VFP
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specification. This is the newer double format, whereby
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the endian-ness of the doubles matches the endian-ness
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of the memory architecture.
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@ -43,8 +43,8 @@
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is what happens].
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-mfpu=softfpa This is when -msoft-float is specified.
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This is the normal beahviour of other arm configurations,
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which for backwards compatability purposes default to
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This is the normal behavior of other arm configurations,
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which for backwards compatibility purposes default to
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supporting the old FPA format which was always big
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endian, regardless of the endian-ness of the memory
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system. */
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@ -364,7 +364,7 @@ extern int avr_asm_only_p;
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One use of this macro is on machines where the highest numbered
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registers must always be saved and the save-multiple-registers
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instruction supports only sequences of consetionve registers. On
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instruction supports only sequences of consecutive registers. On
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such machines, define `REG_ALLOC_ORDER' to be an initializer that
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lists the highest numbered allocatable register first. */
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