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alpha.c: Fix comment typos. 

* config/alpha/alpha.c: Fix comment typos.
	* config/alpha/elf.h: Likewise.
	* config/arm/arm.c: Likewise.
	* config/arm/arm.h: Likewise.
	* config/arm/arm.md: Likewise.
	* config/arm/t-arm-coff: Likewise.
	* config/arm/t-strongarm-pe: Likewise.
	* config/arm/xscale-elf.h: Likewise.
	* config/avr/avr.h: Likewise.

From-SVN: r68800
This commit is contained in:
Kazu Hirata 2003-07-01 23:26:43 +00:00 committed by Kazu Hirata
parent 2a2ecc33a8
commit 093354e08f
10 changed files with 32 additions and 20 deletions
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12
gcc/ChangeLog
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@ -1,3 +1,15 @@
2003-07-01 Kazu Hirata <kazu@cs.umass.edu>
* config/alpha/alpha.c: Fix comment typos.
* config/alpha/elf.h: Likewise.
* config/arm/arm.c: Likewise.
* config/arm/arm.h: Likewise.
* config/arm/arm.md: Likewise.
* config/arm/t-arm-coff: Likewise.
* config/arm/t-strongarm-pe: Likewise.
* config/arm/xscale-elf.h: Likewise.
* config/avr/avr.h: Likewise.
2003-07-01 Jeff Law <law@redhat.com> 2003-07-01 Jeff Law <law@redhat.com>
* stmt.c (any_pending_cleanups): Remove another redundant test. * stmt.c (any_pending_cleanups): Remove another redundant test.

10
gcc/config/alpha/alpha.c
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@ -974,7 +974,7 @@ call_operand (rtx op, enum machine_mode mode)
{ {
if (TARGET_ABI_OSF) if (TARGET_ABI_OSF)
{ {
/* Disallow virtual registers to cope with pathalogical test cases /* Disallow virtual registers to cope with pathological test cases
such as compile/930117-1.c in which the virtual reg decomposes such as compile/930117-1.c in which the virtual reg decomposes
to the frame pointer. Which is a hard reg that is not $27. */ to the frame pointer. Which is a hard reg that is not $27. */
return (REGNO (op) == 27 || REGNO (op) > LAST_VIRTUAL_REGISTER); return (REGNO (op) == 27 || REGNO (op) > LAST_VIRTUAL_REGISTER);
@ -2006,7 +2006,7 @@ split_small_symbolic_operand (rtx x)
that we've marked with gpdisp relocs, since those have to stay in that we've marked with gpdisp relocs, since those have to stay in
1-1 correspondence with one another. 1-1 correspondence with one another.
Techinically we could copy them if we could set up a mapping from one Technically we could copy them if we could set up a mapping from one
sequence number to another, across the set of insns to be duplicated. sequence number to another, across the set of insns to be duplicated.
This seems overly complicated and error-prone since interblock motion This seems overly complicated and error-prone since interblock motion
from sched-ebb could move one of the pair of insns to a different block. */ from sched-ebb could move one of the pair of insns to a different block. */
@ -7253,7 +7253,7 @@ alpha_expand_prologue (void)
=> alpha_procedure_type != PT_NULL, => alpha_procedure_type != PT_NULL,
so when we are not setting the bit here, we are guaranteed to so when we are not setting the bit here, we are guaranteed to
have emited an FRP frame pointer update just before. */ have emitted an FRP frame pointer update just before. */
RTX_FRAME_RELATED_P (seq) = ! frame_pointer_needed; RTX_FRAME_RELATED_P (seq) = ! frame_pointer_needed;
} }
} }
@ -8267,7 +8267,7 @@ alpha_handle_trap_shadows (void)
} }
/* Alpha can only issue instruction groups simultaneously if they are /* Alpha can only issue instruction groups simultaneously if they are
suitibly aligned. This is very processor-specific. */ suitably aligned. This is very processor-specific. */
enum alphaev4_pipe { enum alphaev4_pipe {
EV4_STOP = 0, EV4_STOP = 0,
@ -8857,7 +8857,7 @@ alpha_elf_select_rtx_section (enum machine_mode mode, rtx x,
unsigned HOST_WIDE_INT align) unsigned HOST_WIDE_INT align)
{ {
if (TARGET_SMALL_DATA && GET_MODE_SIZE (mode) <= g_switch_value) if (TARGET_SMALL_DATA && GET_MODE_SIZE (mode) <= g_switch_value)
/* ??? Consider using mergable sdata sections. */ /* ??? Consider using mergeable sdata sections. */
sdata_section (); sdata_section ();
else else
default_elf_select_rtx_section (mode, x, align); default_elf_select_rtx_section (mode, x, align);

2
gcc/config/alpha/elf.h
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@ -149,7 +149,7 @@ do { \
not defined, the default value is `BIGGEST_ALIGNMENT'. not defined, the default value is `BIGGEST_ALIGNMENT'.
This value is really 2^63. Since gcc figures the alignment in bits, This value is really 2^63. Since gcc figures the alignment in bits,
we could only potentially get to 2^60 on suitible hosts. Due to other we could only potentially get to 2^60 on suitable hosts. Due to other
considerations in varasm, we must restrict this to what fits in an int. */ considerations in varasm, we must restrict this to what fits in an int. */
#undef MAX_OFILE_ALIGNMENT #undef MAX_OFILE_ALIGNMENT

12
gcc/config/arm/arm.c
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@ -2085,7 +2085,7 @@ arm_va_arg (tree valist, tree type)
tree t; tree t;
/* Maintain 64-bit alignment of the valist pointer by /* Maintain 64-bit alignment of the valist pointer by
contructing: valist = ((valist + (8 - 1)) & -8). */ constructing: valist = ((valist + (8 - 1)) & -8). */
minus_eight = build_int_2 (- (IWMMXT_ALIGNMENT / BITS_PER_UNIT), -1); minus_eight = build_int_2 (- (IWMMXT_ALIGNMENT / BITS_PER_UNIT), -1);
t = build_int_2 ((IWMMXT_ALIGNMENT / BITS_PER_UNIT) - 1, 0); t = build_int_2 ((IWMMXT_ALIGNMENT / BITS_PER_UNIT) - 1, 0);
t = build (PLUS_EXPR, TREE_TYPE (valist), valist, t); t = build (PLUS_EXPR, TREE_TYPE (valist), valist, t);
@ -6124,7 +6124,7 @@ get_jump_table_size (rtx insn)
/* Move a minipool fix MP from its current location to before MAX_MP. /* Move a minipool fix MP from its current location to before MAX_MP.
If MAX_MP is NULL, then MP doesn't need moving, but the addressing If MAX_MP is NULL, then MP doesn't need moving, but the addressing
contrains may need updating. */ constraints may need updating. */
static Mnode * static Mnode *
move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp, move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp,
HOST_WIDE_INT max_address) HOST_WIDE_INT max_address)
@ -6747,7 +6747,7 @@ push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc,
Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix)); Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
#ifdef AOF_ASSEMBLER #ifdef AOF_ASSEMBLER
/* PIC symbol refereneces need to be converted into offsets into the /* PIC symbol references need to be converted into offsets into the
based area. */ based area. */
/* XXX This shouldn't be done here. */ /* XXX This shouldn't be done here. */
if (flag_pic && GET_CODE (value) == SYMBOL_REF) if (flag_pic && GET_CODE (value) == SYMBOL_REF)
@ -9490,13 +9490,13 @@ arm_print_operand (FILE *stream, rtx x, int code)
In a pair of registers containing a DI or DF value the 'Q' In a pair of registers containing a DI or DF value the 'Q'
operand returns the register number of the register containing operand returns the register number of the register containing
the least signficant part of the value. The 'R' operand returns the least significant part of the value. The 'R' operand returns
the register number of the register containing the most the register number of the register containing the most
significant part of the value. significant part of the value.
The 'H' operand returns the higher of the two register numbers. The 'H' operand returns the higher of the two register numbers.
On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
same as the 'Q' operand, since the most signficant part of the same as the 'Q' operand, since the most significant part of the
value is held in the lower number register. The reverse is true value is held in the lower number register. The reverse is true
on systems where WORDS_BIG_ENDIAN is false. on systems where WORDS_BIG_ENDIAN is false.
@ -11702,7 +11702,7 @@ thumb_unexpanded_epilogue (void)
high_regs_pushed++; high_regs_pushed++;
/* The prolog may have pushed some high registers to use as /* The prolog may have pushed some high registers to use as
work registers. eg the testuite file: work registers. eg the testsuite file:
gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
compiles to produce: compiles to produce:
push {r4, r5, r6, r7, lr} push {r4, r5, r6, r7, lr}

2
gcc/config/arm/arm.h
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@ -1024,7 +1024,7 @@ extern const char * structure_size_string;
/* The number of (integer) argument register available. */ /* The number of (integer) argument register available. */
#define NUM_ARG_REGS 4 #define NUM_ARG_REGS 4
/* Return the regiser number of the N'th (integer) argument. */ /* Return the register number of the N'th (integer) argument. */
#define ARG_REGISTER(N) (N - 1) #define ARG_REGISTER(N) (N - 1)
#if 0 /* FIXME: The ARM backend has special code to handle structure #if 0 /* FIXME: The ARM backend has special code to handle structure

2
gcc/config/arm/arm.md
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@ -1726,7 +1726,7 @@
/* A Trick, since we are setting the bottom bits in the word, /* A Trick, since we are setting the bottom bits in the word,
we can shift operand[3] up, operand[0] down, OR them together we can shift operand[3] up, operand[0] down, OR them together
and rotate the result back again. This takes 3 insns, and and rotate the result back again. This takes 3 insns, and
the third might be mergable into another op. */ the third might be mergeable into another op. */
/* The shift up copes with the possibility that operand[3] is /* The shift up copes with the possibility that operand[3] is
wider than the bitfield. */ wider than the bitfield. */
rtx op0 = gen_reg_rtx (SImode); rtx op0 = gen_reg_rtx (SImode);

2
gcc/config/arm/t-arm-coff
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@ -28,7 +28,7 @@ EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o
LIBGCC = stmp-multilib LIBGCC = stmp-multilib
INSTALL_LIBGCC = install-multilib INSTALL_LIBGCC = install-multilib
# Currently there is a bug somwehere in GCC's alias analysis # Currently there is a bug somewhere in GCC's alias analysis
# or scheduling code that is breaking _fpmul_parts in fp-bit.c. # or scheduling code that is breaking _fpmul_parts in fp-bit.c.
# Disabling function inlining is a workaround for this problem. # Disabling function inlining is a workaround for this problem.
TARGET_LIBGCC2_CFLAGS = -Dinhibit_libc -fno-inline TARGET_LIBGCC2_CFLAGS = -Dinhibit_libc -fno-inline

2
gcc/config/arm/t-strongarm-pe
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@ -32,7 +32,7 @@ EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o
LIBGCC = stmp-multilib LIBGCC = stmp-multilib
INSTALL_LIBGCC = install-multilib INSTALL_LIBGCC = install-multilib
# Currently there is a bug somwehere in GCC's alias analysis # Currently there is a bug somewhere in GCC's alias analysis
# or scheduling code that is breaking _fpmul_parts in fp-bit.c. # or scheduling code that is breaking _fpmul_parts in fp-bit.c.
# Disabling function inlining is a workaround for this problem. # Disabling function inlining is a workaround for this problem.
TARGET_LIBGCC2_CFLAGS = -Dinhibit_libc -fno-inline TARGET_LIBGCC2_CFLAGS = -Dinhibit_libc -fno-inline

6
gcc/config/arm/xscale-elf.h
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@ -32,7 +32,7 @@
the assembler: the assembler:
-mfpu=softvfp This is the default. It indicates thats doubles are -mfpu=softvfp This is the default. It indicates thats doubles are
stored in a format compatable with the VFP stored in a format compatible with the VFP
specification. This is the newer double format, whereby specification. This is the newer double format, whereby
the endian-ness of the doubles matches the endian-ness the endian-ness of the doubles matches the endian-ness
of the memory architecture. of the memory architecture.
@ -43,8 +43,8 @@
is what happens]. is what happens].
-mfpu=softfpa This is when -msoft-float is specified. -mfpu=softfpa This is when -msoft-float is specified.
This is the normal beahviour of other arm configurations, This is the normal behavior of other arm configurations,
which for backwards compatability purposes default to which for backwards compatibility purposes default to
supporting the old FPA format which was always big supporting the old FPA format which was always big
endian, regardless of the endian-ness of the memory endian, regardless of the endian-ness of the memory
system. */ system. */

2
gcc/config/avr/avr.h
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@ -364,7 +364,7 @@ extern int avr_asm_only_p;
One use of this macro is on machines where the highest numbered One use of this macro is on machines where the highest numbered
registers must always be saved and the save-multiple-registers registers must always be saved and the save-multiple-registers
instruction supports only sequences of consetionve registers. On instruction supports only sequences of consecutive registers. On
such machines, define `REG_ALLOC_ORDER' to be an initializer that such machines, define `REG_ALLOC_ORDER' to be an initializer that
lists the highest numbered allocatable register first. */ lists the highest numbered allocatable register first. */