parent
0854b1c4ba
commit
09a625f76b
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@ -1,3 +1,14 @@
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2001-12-08 Tom Rix <trix@redhat.com>
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* config/rs6000/aix43.h (NON_POWERPC_MASKS): Delete MASK_STRING.
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* config/rs6000/aix51.h (NON_POWERPC_MASKS): Same.
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* config/rs6000/rs6000.md (load_multiple, store_multiple): Do not use
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for powerpc64.
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* config/rs6000/rs6000.md (movstrsi_8reg, movstrsi_6reg,
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movstrsi_4reg, movstrsi_1_reg): Add powerpc64.
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* config/rs6000/rs6000.c (expand_block_move): Do not use
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gen_movstrsi_2reg and powerpc64.
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2001-10-08 Aldy Hernandez <aldyh@redhat.com>
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* c-common.h (rid): Add RID_CHOOSE_EXPR and
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@ -40,7 +40,7 @@ Boston, MA 02111-1307, USA. */
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The macro SUBTARGET_OVERRIDE_OPTIONS is provided for subtargets, to
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get control. */
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#define NON_POWERPC_MASKS (MASK_POWER | MASK_POWER2 | MASK_STRING)
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#define NON_POWERPC_MASKS (MASK_POWER | MASK_POWER2)
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#define SUBTARGET_OVERRIDE_OPTIONS \
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do { \
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if (TARGET_64BIT && (target_flags & NON_POWERPC_MASKS)) \
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@ -40,7 +40,7 @@ Boston, MA 02111-1307, USA. */
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The macro SUBTARGET_OVERRIDE_OPTIONS is provided for subtargets, to
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get control. */
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#define NON_POWERPC_MASKS (MASK_POWER | MASK_POWER2 | MASK_STRING)
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#define NON_POWERPC_MASKS (MASK_POWER | MASK_POWER2)
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#define SUBTARGET_OVERRIDE_OPTIONS \
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do { \
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if (TARGET_64BIT && (target_flags & NON_POWERPC_MASKS)) \
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@ -4074,7 +4074,7 @@ expand_block_move (operands)
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dest_reg, orig_dest),
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tmp_reg);
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}
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else if (bytes > 4)
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else if (bytes > 4 && !TARGET_POWERPC64)
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{ /* move up to 8 bytes at a time */
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move_bytes = (bytes > 8) ? 8 : bytes;
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emit_insn (gen_movstrsi_2reg (expand_block_move_mem (BLKmode,
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@ -8568,7 +8568,7 @@
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[(match_par_dup 3 [(set (match_operand:SI 0 "" "")
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(match_operand:SI 1 "" ""))
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(use (match_operand:SI 2 "" ""))])]
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"TARGET_STRING"
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"TARGET_STRING && !TARGET_POWERPC64"
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"
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{
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int regno;
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@ -8664,7 +8664,7 @@
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(match_operand:SI 1 "" ""))
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(clobber (scratch:SI))
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(use (match_operand:SI 2 "" ""))])]
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"TARGET_STRING"
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"TARGET_STRING && !TARGET_POWERPC64"
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"
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{
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int regno;
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@ -8810,6 +8810,30 @@
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[(set_attr "type" "load")
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(set_attr "length" "8")])
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(define_insn ""
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[(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
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(mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
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(use (match_operand:SI 2 "immediate_operand" "i"))
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(use (match_operand:SI 3 "immediate_operand" "i"))
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(clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
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(clobber (reg:SI 6))
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(clobber (reg:SI 7))
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(clobber (reg:SI 8))
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(clobber (reg:SI 9))
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(clobber (reg:SI 10))
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(clobber (reg:SI 11))
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(clobber (reg:SI 12))
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(clobber (match_scratch:SI 5 "X"))]
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"TARGET_STRING && TARGET_POWERPC64
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&& ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
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|| INTVAL (operands[2]) == 0)
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&& (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
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&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
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&& REGNO (operands[4]) == 5"
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"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
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[(set_attr "type" "load")
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(set_attr "length" "8")])
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;; Move up to 24 bytes at a time. The fixed registers are needed because the
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;; register allocator doesn't have a clue about allocating 6 word registers.
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;; rD/rS = r5 is preferred, efficient form.
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@ -8870,6 +8894,27 @@
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[(set_attr "type" "load")
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(set_attr "length" "8")])
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(define_insn ""
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[(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
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(mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
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(use (match_operand:SI 2 "immediate_operand" "i"))
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(use (match_operand:SI 3 "immediate_operand" "i"))
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(clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
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(clobber (reg:SI 6))
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(clobber (reg:SI 7))
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(clobber (reg:SI 8))
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(clobber (reg:SI 9))
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(clobber (reg:SI 10))
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(clobber (match_scratch:SI 5 "X"))]
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"TARGET_STRING && TARGET_POWERPC64
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&& INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
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&& (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
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&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
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&& REGNO (operands[4]) == 5"
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"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
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[(set_attr "type" "load")
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(set_attr "length" "8")])
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;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
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;; problems with TImode.
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;; rD/rS = r5 is preferred, efficient form.
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@ -8924,6 +8969,25 @@
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[(set_attr "type" "load")
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(set_attr "length" "8")])
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(define_insn ""
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[(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
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(mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
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(use (match_operand:SI 2 "immediate_operand" "i"))
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(use (match_operand:SI 3 "immediate_operand" "i"))
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(clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
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(clobber (reg:SI 6))
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(clobber (reg:SI 7))
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(clobber (reg:SI 8))
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(clobber (match_scratch:SI 5 "X"))]
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"TARGET_STRING && TARGET_POWERPC64
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&& INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
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&& (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
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&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
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&& REGNO (operands[4]) == 5"
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"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
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[(set_attr "type" "load")
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(set_attr "length" "8")])
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;; Move up to 8 bytes at a time.
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(define_expand "movstrsi_2reg"
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[(parallel [(set (match_operand 0 "" "")
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@ -8998,6 +9062,19 @@
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[(set_attr "type" "load")
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(set_attr "length" "8")])
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(define_insn ""
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[(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
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(mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
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(use (match_operand:SI 2 "immediate_operand" "i"))
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(use (match_operand:SI 3 "immediate_operand" "i"))
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(clobber (match_scratch:SI 4 "=&r"))
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(clobber (match_scratch:SI 5 "X"))]
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"TARGET_STRING && TARGET_POWERPC64
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&& INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
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"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
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[(set_attr "type" "load")
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(set_attr "length" "8")])
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;; Define insns that do load or store with update. Some of these we can
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;; get by using pre-decrement or pre-increment, but the hardware can also
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