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pdp11.c: Include "recog.h". 

* pdp11.c: Include "recog.h".
        (output_functip', `notice_update_cc_on_set', `output_ascii',
        `output_function_epilogue', `output_function_prologue',
        `print_operand_address', `register_move_cost',
        `simple_memory_operand'.
        (HARD_REGNO_MODE_OK): Parenthesise `REGNO' arg.
        (REGNO_REG_CLASS): Likewise.
        * pdp11.md: Add explicit `int' to `static count' (in two places).
        (addhi3): Add explicit braces to avoid ambiguous else.
        (addqi3): Likewise.
        (ashlhi3): Likewise.

From-SVN: r26125
This commit is contained in:
Joseph Myers 1999-04-02 06:46:46 -07:00 committed by Jeff Law
parent 8b9243df27
commit 09b893bba7
4 changed files with 64 additions and 24 deletions
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24
gcc/ChangeLog
View File

@ -1,3 +1,27 @@
1999-04-02 Joseph S. Myers <jsm28@cam.ac.uk>
* pdp11.c: Include "recog.h".
(output_function_prologue): Remove unused variables `nregs', `i',
`offset'.
(output_function_epilogue): Remove unused variables
`may_call_alloca', `nregs', `regno', `adjust_fp'.
(output_ascii): Mark as returning void.
(print_operand_address: Likewise.
(simple_memory_operand): Remove unused variables `plus0', `plus1',
`offset'.
* pdp11.h: Declare functions `arith_operand',
`const_immediate_operand', `expand_shift_operand',
`legitimate_address_p', `notice_update_cc_on_set', `output_ascii',
`output_function_epilogue', `output_function_prologue',
`print_operand_address', `register_move_cost',
`simple_memory_operand'.
(HARD_REGNO_MODE_OK): Parenthesise `REGNO' arg.
(REGNO_REG_CLASS): Likewise.
* pdp11.md: Add explicit `int' to `static count' (in two places).
(addhi3): Add explicit braces to avoid ambiguous else.
(addqi3): Likewise.
(ashlhi3): Likewise.
Fri Apr 2 14:17:10 1999 Jerry James <jerry@cs.ucsb.edu>
* gcc/invoke.texi: Add documentation for additional supported

13
gcc/config/pdp11/pdp11.c
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@ -31,6 +31,7 @@ Boston, MA 02111-1307, USA. */
#include "output.h"
#include "insn-attr.h"
#include "flags.h"
#include "recog.h"
/*
#define FPU_REG_P(X) ((X)>=8 && (X)<14)
@ -97,8 +98,7 @@ output_function_prologue(stream, size)
int size;
{
int fsize = ((size) + 1) & ~1;
int regno, nregs, i;
int offset = 0;
int regno;
int via_ac = -1;
@ -192,10 +192,8 @@ output_function_epilogue(stream, size)
FILE *stream;
int size;
{
extern int may_call_alloca;
int fsize = ((size) + 1) & ~1;
int nregs, regno, i, j, k, adjust_fp;
int i, j, k;
int via_ac;
@ -735,6 +733,7 @@ find_addr_reg (addr)
}
/* Output an ascii string. */
void
output_ascii (file, p, size)
FILE *file;
char *p;
@ -769,6 +768,7 @@ output_ascii (file, p, size)
/* --- stole from out-vax, needs changes */
void
print_operand_address (file, addr)
FILE *file;
register rtx addr;
@ -1039,8 +1039,7 @@ int simple_memory_operand(op, mode)
rtx op;
enum machine_mode mode;
{
rtx addr, plus0, plus1;
int offset = 0;
rtx addr;
/* Eliminate non-memory operations */
if (GET_CODE (op) != MEM)

17
gcc/config/pdp11/pdp11.h
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@ -21,10 +21,21 @@ Boston, MA 02111-1307, USA. */
/* declarations */
int arith_operand ();
int const_immediate_operand ();
int expand_shift_operand ();
int legitimate_address_p ();
void notice_update_cc_on_set ();
void output_ascii ();
void output_function_epilogue ();
void output_function_prologue ();
char *output_jump();
char *output_move_double();
char *output_move_quad();
char *output_block_move();
void print_operand_address ();
int register_move_cost ();
int simple_memory_operand ();
/* check whether load_fpu_reg or not */
#define LOAD_FPU_REG_P(x) ((x)>=8 && (x)<=11)
@ -289,9 +300,9 @@ extern int target_flags;
FPU can only hold DF - simplifies life!
*/
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
((REGNO < 8)? \
(((REGNO) < 8)? \
((GET_MODE_BITSIZE(MODE) <= 16) \
|| (GET_MODE_BITSIZE(MODE) == 32 && !(REGNO & 1))) \
|| (GET_MODE_BITSIZE(MODE) == 32 && !((REGNO) & 1))) \
:(MODE) == DFmode)
@ -395,7 +406,7 @@ enum reg_class { NO_REGS, MUL_REGS, GENERAL_REGS, LOAD_FPU_REGS, NO_LOAD_FPU_REG
or could index an array. */
#define REGNO_REG_CLASS(REGNO) \
((REGNO)>=8?((REGNO)<=11?LOAD_FPU_REGS:NO_LOAD_FPU_REGS):((REGNO&1)?MUL_REGS:GENERAL_REGS))
((REGNO)>=8?((REGNO)<=11?LOAD_FPU_REGS:NO_LOAD_FPU_REGS):(((REGNO)&1)?MUL_REGS:GENERAL_REGS))
/* The class value for index registers, and the one for base regs. */

34
gcc/config/pdp11/pdp11.md
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@ -878,7 +878,7 @@
"(! TARGET_40_PLUS)"
"*
{
static count = 0;
static int count = 0;
char buf[100];
rtx lateoperands[2];
@ -1041,10 +1041,12 @@
"*
{
if (GET_CODE (operands[2]) == CONST_INT)
if (INTVAL(operands[2]) == 1)
return \"inc %0\";
else if (INTVAL(operands[2]) == -1)
return \"dec %0\";
{
if (INTVAL(operands[2]) == 1)
return \"inc %0\";
else if (INTVAL(operands[2]) == -1)
return \"dec %0\";
}
return \"add %2, %0\";
}"
@ -1058,10 +1060,12 @@
"*
{
if (GET_CODE (operands[2]) == CONST_INT)
if (INTVAL(operands[2]) == 1)
return \"incb %0\";
else if (INTVAL(operands[2]) == -1)
return \"decb %0\";
{
if (INTVAL(operands[2]) == 1)
return \"incb %0\";
else if (INTVAL(operands[2]) == -1)
return \"decb %0\";
}
return \"addb %2, %0\";
}"
@ -1520,10 +1524,12 @@
"*
{
if (GET_CODE(operands[2]) == CONST_INT)
if (INTVAL(operands[2]) == 1)
return \"asl %0\";
else if (INTVAL(operands[2]) == -1)
return \"asr %0\";
{
if (INTVAL(operands[2]) == 1)
return \"asl %0\";
else if (INTVAL(operands[2]) == -1)
return \"asr %0\";
}
return \"ash %2,%0\";
}"
@ -1563,7 +1569,7 @@
"TARGET_ABSHI_BUILTIN"
"*
{
static count = 0;
static int count = 0;
char buf[200];
output_asm_insn(\"tst %0\", operands);