RISC-V: Add RV32E support.
Kito Cheng <kito.cheng@gmail.com> Monk Chiang <sh.chiang04@gmail.com> gcc/ * common/config/riscv/riscv-common.c (riscv_parse_arch_string): Add support to parse rv32e*. Clear MASK_RVE for rv32i and rv64i. * config.gcc (riscv*-*-*): Add support for rv32e* and ilp32e. * config/riscv/riscv-c.c (riscv_cpu_cpp_builtins): Define __riscv_32e when TARGET_RVE. Handle ABI_ILP32E as soft-float ABI. * config/riscv/riscv-opts.h (riscv_abi_type): Add ABI_ILP32E. * config/riscv/riscv.c (riscv_compute_frame_info): When TARGET_RVE, compute save_libcall_adjustment properly. (riscv_option_override): Call error if TARGET_RVE and not ABI_ILP32E. (riscv_conditional_register_usage): Handle TARGET_RVE and ABI_ILP32E. * config/riscv/riscv.h (UNITS_PER_FP_ARG): Handle ABI_ILP32E. (STACK_BOUNDARY, ABI_STACK_BOUNDARY): Handle TARGET_RVE. (GP_REG_LAST, MAX_ARGS_IN_REGISTERS): Likewise. (ABI_SPEC): Handle mabi=ilp32e. * config/riscv/riscv.opt (abi_type): Add ABI_ILP32E. (RVE): Add RVE mask. * doc/invoke.texi (RISC-V options) <-mabi>: Add ilp32e info. <-march>: Add rv32e as an example. gcc/testsuite/ * gcc.dg/stack-usage-1.c: Add support for rv32e. libgcc/ * config/riscv/save-restore.S: Add support for rv32e. Co-Authored-By: Jim Wilson <jimw@sifive.com> Co-Authored-By: Monk Chiang <sh.chiang04@gmail.com> From-SVN: r260384
This commit is contained in:
Kito Cheng
Jim Wilson
parent
dc2ebc998a
commit
09baee1ab1
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@ -1,3 +1,26 @@
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2018-05-18 Kito Cheng <kito.cheng@gmail.com>
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Monk Chiang <sh.chiang04@gmail.com>
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Jim Wilson <jimw@sifive.com>
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* common/config/riscv/riscv-common.c (riscv_parse_arch_string):
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Add support to parse rv32e*. Clear MASK_RVE for rv32i and rv64i.
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* config.gcc (riscv*-*-*): Add support for rv32e* and ilp32e.
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* config/riscv/riscv-c.c (riscv_cpu_cpp_builtins): Define
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__riscv_32e when TARGET_RVE. Handle ABI_ILP32E as soft-float ABI.
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* config/riscv/riscv-opts.h (riscv_abi_type): Add ABI_ILP32E.
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* config/riscv/riscv.c (riscv_compute_frame_info): When TARGET_RVE,
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compute save_libcall_adjustment properly.
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(riscv_option_override): Call error if TARGET_RVE and not ABI_ILP32E.
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(riscv_conditional_register_usage): Handle TARGET_RVE and ABI_ILP32E.
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* config/riscv/riscv.h (UNITS_PER_FP_ARG): Handle ABI_ILP32E.
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(STACK_BOUNDARY, ABI_STACK_BOUNDARY): Handle TARGET_RVE.
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(GP_REG_LAST, MAX_ARGS_IN_REGISTERS): Likewise.
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(ABI_SPEC): Handle mabi=ilp32e.
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* config/riscv/riscv.opt (abi_type): Add ABI_ILP32E.
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(RVE): Add RVE mask.
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* doc/invoke.texi (RISC-V options) <-mabi>: Add ilp32e info.
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<-march>: Add rv32e as an example.
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2018-05-18 Marc Glisse <marc.glisse@inria.fr>
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PR c++/82899
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@ -27,7 +27,8 @@ along with GCC; see the file COPYING3. If not see
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#include "flags.h"
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#include "diagnostic-core.h"
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/* Parse a RISC-V ISA string into an option mask. */
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/* Parse a RISC-V ISA string into an option mask. Must clear or set all arch
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dependent mask bits, in case more than one -march string is passed. */
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static void
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riscv_parse_arch_string (const char *isa, int *flags, location_t loc)
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@ -48,6 +49,8 @@ riscv_parse_arch_string (const char *isa, int *flags, location_t loc)
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{
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p++;
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*flags &= ~MASK_RVE;
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*flags |= MASK_MUL;
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*flags |= MASK_ATOMIC;
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*flags |= MASK_HARD_FLOAT;
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@ -57,6 +60,8 @@ riscv_parse_arch_string (const char *isa, int *flags, location_t loc)
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{
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p++;
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*flags &= ~MASK_RVE;
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*flags &= ~MASK_MUL;
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if (*p == 'm')
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*flags |= MASK_MUL, p++;
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@ -77,6 +82,28 @@ riscv_parse_arch_string (const char *isa, int *flags, location_t loc)
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}
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}
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}
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else if (*p == 'e')
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{
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p++;
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*flags |= MASK_RVE;
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if (*flags & MASK_64BIT)
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{
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error ("RV64E is not a valid base ISA");
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return;
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}
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*flags &= ~MASK_MUL;
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if (*p == 'm')
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*flags |= MASK_MUL, p++;
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*flags &= ~MASK_ATOMIC;
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if (*p == 'a')
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*flags |= MASK_ATOMIC, p++;
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*flags &= ~(MASK_HARD_FLOAT | MASK_DOUBLE_FLOAT);
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}
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else
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{
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error_at (loc, "-march=%s: invalid ISA string", isa);
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@ -4077,19 +4077,20 @@ case "${target}" in
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# Infer arch from --with-arch, --target, and --with-abi.
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case "${with_arch}" in
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rv32i* | rv32g* | rv64i* | rv64g*)
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rv32e* | rv32i* | rv32g* | rv64i* | rv64g*)
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# OK.
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;;
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"")
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# Infer XLEN, but otherwise assume GC.
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case "${with_abi}" in
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ilp32e) with_arch="rv32e" ;;
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ilp32 | ilp32f | ilp32d) with_arch="rv32gc" ;;
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lp64 | lp64f | lp64d) with_arch="rv64gc" ;;
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*) with_arch="rv${xlen}gc" ;;
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esac
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;;
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*)
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echo "--with-arch=${with_arch} is not supported. The argument must begin with rv32i, rv32g, rv64i, or rv64g." 1>&2
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echo "--with-arch=${with_arch} is not supported. The argument must begin with rv32e, rv32i, rv32g, rv64i, or rv64g." 1>&2
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exit 1
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;;
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esac
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@ -4098,11 +4099,12 @@ case "${target}" in
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# pick a default based on the ISA, preferring soft-float
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# unless the D extension is present.
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case "${with_abi}" in
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ilp32 | ilp32f | ilp32d | lp64 | lp64f | lp64d)
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ilp32 | ilp32e | ilp32f | ilp32d | lp64 | lp64f | lp64d)
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;;
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"")
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case "${with_arch}" in
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rv32*d* | rv32g*) with_abi=ilp32d ;;
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rv32e*) with_abi=ilp32e ;;
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rv32*) with_abi=ilp32 ;;
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rv64*d* | rv64g*) with_abi=lp64d ;;
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rv64*) with_abi=lp64 ;;
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@ -4116,7 +4118,7 @@ case "${target}" in
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# Make sure ABI and ISA are compatible.
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case "${with_abi},${with_arch}" in
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ilp32,rv32* \
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ilp32,rv32* | ilp32e,rv32e* \
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| ilp32f,rv32*f* | ilp32f,rv32g* \
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| ilp32d,rv32*d* | ilp32d,rv32g* \
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| lp64,rv64* \
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@ -39,6 +39,9 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
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if (TARGET_RVC)
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builtin_define ("__riscv_compressed");
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if (TARGET_RVE)
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builtin_define ("__riscv_32e");
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if (TARGET_ATOMIC)
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builtin_define ("__riscv_atomic");
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@ -62,6 +65,7 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
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switch (riscv_abi)
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{
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case ABI_ILP32:
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case ABI_ILP32E:
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case ABI_LP64:
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builtin_define ("__riscv_float_abi_soft");
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break;
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@ -23,6 +23,7 @@ along with GCC; see the file COPYING3. If not see
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enum riscv_abi_type {
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ABI_ILP32,
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ABI_ILP32E,
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ABI_ILP32F,
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ABI_ILP32D,
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ABI_LP64,
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@ -3334,7 +3334,14 @@ riscv_compute_frame_info (void)
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/* Only use save/restore routines if they don't alter the stack size. */
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if (RISCV_STACK_ALIGN (num_save_restore * UNITS_PER_WORD) == x_save_size)
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frame->save_libcall_adjustment = x_save_size;
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{
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/* Libcall saves/restores 3 registers at once, so we need to
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allocate 12 bytes for callee-saved register. */
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if (TARGET_RVE)
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x_save_size = 3 * UNITS_PER_WORD;
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frame->save_libcall_adjustment = x_save_size;
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}
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offset += x_save_size;
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}
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@ -4147,6 +4154,9 @@ riscv_option_override (void)
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error ("requested ABI requires -march to subsume the %qc extension",
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UNITS_PER_FP_ARG > 8 ? 'Q' : (UNITS_PER_FP_ARG > 4 ? 'D' : 'F'));
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if (TARGET_RVE && riscv_abi != ABI_ILP32E)
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error ("rv32e requires ilp32e ABI");
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/* We do not yet support ILP32 on RV64. */
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if (BITS_PER_WORD != POINTER_SIZE)
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error ("ABI requires -march=rv%d", POINTER_SIZE);
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@ -4171,6 +4181,19 @@ riscv_option_override (void)
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static void
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riscv_conditional_register_usage (void)
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{
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/* We have only x0~x15 on RV32E. */
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if (TARGET_RVE)
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{
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for (int r = 16; r <= 31; r++)
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fixed_regs[r] = 1;
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}
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if (riscv_abi == ABI_ILP32E)
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{
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for (int r = 16; r <= 31; r++)
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call_used_regs[r] = 1;
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}
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if (!TARGET_HARD_FLOAT)
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{
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for (int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
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@ -102,9 +102,11 @@ along with GCC; see the file COPYING3. If not see
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#define UNITS_PER_FP_REG (TARGET_DOUBLE_FLOAT ? 8 : 4)
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/* The largest type that can be passed in floating-point registers. */
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#define UNITS_PER_FP_ARG \
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(riscv_abi == ABI_ILP32 || riscv_abi == ABI_LP64 ? 0 : \
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riscv_abi == ABI_ILP32F || riscv_abi == ABI_LP64F ? 4 : 8) \
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#define UNITS_PER_FP_ARG \
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((riscv_abi == ABI_ILP32 || riscv_abi == ABI_ILP32E \
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|| riscv_abi == ABI_LP64) \
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? 0 \
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: ((riscv_abi == ABI_ILP32F || riscv_abi == ABI_LP64F) ? 4 : 8))
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/* Set the sizes of the core types. */
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#define SHORT_TYPE_SIZE 16
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@ -124,10 +126,10 @@ along with GCC; see the file COPYING3. If not see
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#define FUNCTION_BOUNDARY (TARGET_RVC ? 16 : 32)
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/* The smallest supported stack boundary the calling convention supports. */
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#define STACK_BOUNDARY (2 * BITS_PER_WORD)
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#define STACK_BOUNDARY (TARGET_RVE ? BITS_PER_WORD : 2 * BITS_PER_WORD)
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/* The ABI stack alignment. */
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#define ABI_STACK_BOUNDARY 128
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#define ABI_STACK_BOUNDARY (TARGET_RVE ? BITS_PER_WORD : 128)
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/* There is no point aligning anything to a rounder boundary than this. */
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#define BIGGEST_ALIGNMENT 128
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@ -260,7 +262,7 @@ along with GCC; see the file COPYING3. If not see
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/* Internal macros to classify an ISA register's type. */
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#define GP_REG_FIRST 0
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#define GP_REG_LAST 31
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#define GP_REG_LAST (TARGET_RVE ? 15 : 31)
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#define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
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#define FP_REG_FIRST 32
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@ -490,7 +492,7 @@ enum reg_class
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#define GP_RETURN GP_ARG_FIRST
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#define FP_RETURN (UNITS_PER_FP_ARG == 0 ? GP_RETURN : FP_ARG_FIRST)
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#define MAX_ARGS_IN_REGISTERS 8
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#define MAX_ARGS_IN_REGISTERS (TARGET_RVE ? 6 : 8)
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/* Symbolic macros for the first/last argument registers. */
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@ -870,6 +872,7 @@ extern unsigned riscv_stack_boundary;
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#define ABI_SPEC \
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"%{mabi=ilp32:ilp32}" \
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"%{mabi=ilp32e:ilp32e}" \
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"%{mabi=ilp32f:ilp32f}" \
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"%{mabi=ilp32d:ilp32d}" \
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"%{mabi=lp64:lp64}" \
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@ -44,6 +44,9 @@ Supported ABIs (for use with the -mabi= option):
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EnumValue
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Enum(abi_type) String(ilp32) Value(ABI_ILP32)
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EnumValue
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Enum(abi_type) String(ilp32e) Value(ABI_ILP32E)
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EnumValue
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Enum(abi_type) String(ilp32f) Value(ABI_ILP32F)
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@ -122,3 +125,5 @@ Mask(HARD_FLOAT)
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Mask(DOUBLE_FLOAT)
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Mask(RVC)
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Mask(RVE)
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@ -23025,7 +23025,9 @@ conventions are: @samp{ilp32}, @samp{ilp32f}, @samp{ilp32d}, @samp{lp64},
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@samp{lp64f}, and @samp{lp64d}. Some calling conventions are impossible to
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implement on some ISAs: for example, @samp{-march=rv32if -mabi=ilp32d} is
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invalid because the ABI requires 64-bit values be passed in F registers, but F
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registers are only 32 bits wide.
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registers are only 32 bits wide. There is also the @samp{ilp32e} ABI that can
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only be used with the @samp{rv32e} architecture. This ABI is not well
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specified at present, and is subject to change.
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@item -mfdiv
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@itemx -mno-fdiv
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@ -23044,7 +23046,8 @@ these instructions.
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@item -march=@var{ISA-string}
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@opindex march
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Generate code for given RISC-V ISA (e.g.@ @samp{rv64im}). ISA strings must be
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lower-case. Examples include @samp{rv64i}, @samp{rv32g}, and @samp{rv32imaf}.
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lower-case. Examples include @samp{rv64i}, @samp{rv32g}, @samp{rv32e}, and
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@samp{rv32imaf}.
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@item -mtune=@var{processor-string}
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@opindex mtune
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@ -1,3 +1,7 @@
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2018-05-18 Kito Cheng <kito.cheng@gmail.com>
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* gcc.dg/stack-usage-1.c: Add support for rv32e.
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2018-05-18 Marc Glisse <marc.glisse@inria.fr>
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PR c++/82899
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@ -64,7 +64,11 @@
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# define SIZE 240
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# endif
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#elif defined (__riscv)
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# define SIZE 240
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# if defined (__riscv_32e)
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# define SIZE 252
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# else
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# define SIZE 240
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# endif
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#elif defined (__AVR__)
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#if defined (__AVR_3_BYTE_PC__ )
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# define SIZE 251 /* 256 - 2 bytes for Y - 3 bytes for return address */
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@ -1,3 +1,9 @@
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2018-05-18 Kito Cheng <kito.cheng@gmail.com>
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Monk Chiang <sh.chiang04@gmail.com>
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Jim Wilson <jimw@sifive.com>
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* config/riscv/save-restore.S: Add support for rv32e.
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2018-05-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* config/arm/libunwind.S: Update comment relating to armv5.
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@ -294,6 +294,48 @@ FUNC_END (__riscv_restore_0)
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#else
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#ifdef __riscv_32e
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FUNC_BEGIN(__riscv_save_2)
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FUNC_BEGIN(__riscv_save_1)
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FUNC_BEGIN(__riscv_save_0)
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.cfi_startproc
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# __riscv_save_* routine use t0/x5 as return address
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.cfi_return_column 5
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addi sp, sp, -12
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.cfi_def_cfa_offset 12
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sw s1, 0(sp)
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.cfi_offset 9, -12
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sw s0, 4(sp)
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.cfi_offset 8, -8
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sw ra, 8(sp)
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.cfi_offset 1, 0
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jr t0
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.cfi_endproc
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FUNC_END(__riscv_save_2)
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FUNC_END(__riscv_save_1)
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FUNC_END(__riscv_save_0)
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FUNC_BEGIN(__riscv_restore_2)
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FUNC_BEGIN(__riscv_restore_1)
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FUNC_BEGIN(__riscv_restore_0)
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.cfi_startproc
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.cfi_def_cfa_offset 14
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lw s1, 0(sp)
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.cfi_restore 9
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lw s0, 4(sp)
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.cfi_restore 8
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lw ra, 8(sp)
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.cfi_restore 1
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addi sp, sp, 12
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.cfi_def_cfa_offset 0
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ret
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.cfi_endproc
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FUNC_END(__riscv_restore_2)
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FUNC_END(__riscv_restore_1)
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FUNC_END(__riscv_restore_0)
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#else
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||||
|
||||
FUNC_BEGIN (__riscv_save_12)
|
||||
.cfi_startproc
|
||||
# __riscv_save_* routine use t0/x5 as return address
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|
|
@ -486,4 +528,6 @@ FUNC_END (__riscv_restore_2)
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FUNC_END (__riscv_restore_1)
|
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FUNC_END (__riscv_restore_0)
|
||||
|
||||
#endif
|
||||
#endif /* __riscv_32e */
|
||||
|
||||
#endif /* __riscv_xlen == 64 */
|
||||
|
|
|
|||
Loading…
Reference in New Issue