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i386.h (TARGET_ABM): New define. 

* config/i386/i386.h (TARGET_ABM): New define.
	(TARGET_POPCNT): Ditto.
	(TARGET_64BIT, TARGET_MMX, TARGET_3DNOW, TARGET_3DNOW_A, TARGET_SSE*):
	New temporary defines to redefine from OPTION_ISA_* defines.
	(MASK_64BIT, MASK_MMX, MASK_3DNOW, MASK_3DNOW_A, MASK_SSE*):
	New temporary defines to redefine from OPTION_MASK_ISA_* defines.
	(ix86_isa_flags): New extern int declaration.
	(TARGET_SUBTARGET_DEFAULT): New define.
	(TARGET_SUBTARGET_ISA_DEFAULT): Ditto.
	(TARGET_SUBTARGET32_DEFAULT): Ditto.
	(TARGET_SUBTARGET32_ISA_DEFAULT): Ditto.
	(TARGET_SUBTARGET64_ISA_DEFAULT): Ditto.
	* config/i386/unix.h: Undef TARGET_SUBTARGET_DEFAULT before define.
	* config/i386/darwin.h: Change TARGET_64BIT define to
	OPTION_ISA_64BIT.

	* config/i386/i386.opt (m3dnowa): Define as undocumented option
	using existing "ix86_isa_flags" varible.
	(m32, m64): Use existing "ix86_isa_flags" variable.
	(mmmx, m3dnow): Ditto.
	(msse, msse2, msse3, mssse3, msse4.1, msse4a): Ditto.
	(mabm): Define as non-negative option using "x86_abm" variable.
	(mpopcnt): Define as non-negative option using "x86_popcnt" variable.

	* config/i386/i386.c (ix86_arch_features) [X86_ARCH_CMOVE]:
	Rewrite feature test bitmap.
	(ix86_isa_flags): New initialized global int varible.
	(ix86_isa_flags_explicit): New static int variable.
	(ix86_handle_option): Set "ix86_isa_flags_explicit" when mmmx, m3dnow,
	msse, msse2, msse3, msse4.1 and msse4a option is processed.  Change
	i86_isa_flags and ix86_isa_flags_explicit, not target_flags and
	target_flags_explicit.
	(override_options): Remove "target_enable" and "target_disable" fields
	from "struct ptt". Update processor_target_table accordingly. Remove
	PTA_PREFETCH_SSE from processor_alias_table entry if PTE_SSE is
	defined and rearrange PTA_* bits.  Use "ix86_isa_flags" instead of
	"target_flags" and "ix86_isa_flags_explicit" instead of
	"target_flags_explicit" when masked with MASK_64BIT, MASK_MMX,
	MASK_3DNOW, MASK_3DNOW_A or MASK_SSE*.  Set "x86_abm" to true when
	PTA_ABM is set in processor_alias_table flags entry.  Set "x86_popcnt"
	to true when either of PTA_POPCNT or PTA_ABM is set in
	processor_alias_table flags entry.  Set "x86_prefetch_sse" to true
	when either of PTA_PREFETCH_SSE or PTA_SSE is set in
	processor_alias_table flags entry.  Remove handling of
	"target_enable" and "target_disable" fields of processor_target_table.
	Mask "target_flags" with TARGET_SUBTARGET32_DEFAULT for 32-bit
	targets or with TARGET_SUBTARGET64_DEFAULT for 64-bit targets.
	Mask "ix86_isa_flags" with TARGET_SUBTARGET32_ISA_DEFAULT for 32-bit
	targets or with TARGET_SUBTARGET64_ISA_DEFAULT for 64-bit targets.
	(def_builtin): Mask "mask" variable with "ix86_isa_flags", not
	"target_flags".
	(TARGET_DEFAULT_TARGET_FLAGS): Do not include TARGET_64BIT_DEFAULT.

From-SVN: r125180
This commit is contained in:
Uros Bizjak 2007-05-30 13:24:32 +02:00
parent a7c835467a
commit 0a1c5e5520
6 changed files with 354 additions and 227 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

59
gcc/ChangeLog
View File

@ -1,3 +1,58 @@
2007-05-30 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.h (TARGET_ABM): New define.
(TARGET_POPCNT): Ditto.
(TARGET_64BIT, TARGET_MMX, TARGET_3DNOW, TARGET_3DNOW_A, TARGET_SSE*):
New temporary defines to redefine from OPTION_ISA_* defines.
(MASK_64BIT, MASK_MMX, MASK_3DNOW, MASK_3DNOW_A, MASK_SSE*):
New temporary defines to redefine from OPTION_MASK_ISA_* defines.
(ix86_isa_flags): New extern int declaration.
(TARGET_SUBTARGET_DEFAULT): New define.
(TARGET_SUBTARGET_ISA_DEFAULT): Ditto.
(TARGET_SUBTARGET32_DEFAULT): Ditto.
(TARGET_SUBTARGET32_ISA_DEFAULT): Ditto.
(TARGET_SUBTARGET64_ISA_DEFAULT): Ditto.
* config/i386/unix.h: Undef TARGET_SUBTARGET_DEFAULT before define.
* config/i386/darwin.h: Change TARGET_64BIT define to
OPTION_ISA_64BIT.
* config/i386/i386.opt (m3dnowa): Define as undocumented option
using existing "ix86_isa_flags" varible.
(m32, m64): Use existing "ix86_isa_flags" variable.
(mmmx, m3dnow): Ditto.
(msse, msse2, msse3, mssse3, msse4.1, msse4a): Ditto.
(mabm): Define as non-negative option using "x86_abm" variable.
(mpopcnt): Define as non-negative option using "x86_popcnt" variable.
* config/i386/i386.c (ix86_arch_features) [X86_ARCH_CMOVE]:
Rewrite feature test bitmap.
(ix86_isa_flags): New initialized global int varible.
(ix86_isa_flags_explicit): New static int variable.
(ix86_handle_option): Set "ix86_isa_flags_explicit" when mmmx, m3dnow,
msse, msse2, msse3, msse4.1 and msse4a option is processed. Change
i86_isa_flags and ix86_isa_flags_explicit, not target_flags and
target_flags_explicit.
(override_options): Remove "target_enable" and "target_disable" fields
from "struct ptt". Update processor_target_table accordingly. Remove
PTA_PREFETCH_SSE from processor_alias_table entry if PTE_SSE is
defined and rearrange PTA_* bits. Use "ix86_isa_flags" instead of
"target_flags" and "ix86_isa_flags_explicit" instead of
"target_flags_explicit" when masked with MASK_64BIT, MASK_MMX,
MASK_3DNOW, MASK_3DNOW_A or MASK_SSE*. Set "x86_abm" to true when
PTA_ABM is set in processor_alias_table flags entry. Set "x86_popcnt"
to true when either of PTA_POPCNT or PTA_ABM is set in
processor_alias_table flags entry. Set "x86_prefetch_sse" to true
when either of PTA_PREFETCH_SSE or PTA_SSE is set in
processor_alias_table flags entry. Remove handling of
"target_enable" and "target_disable" fields of processor_target_table.
Mask "target_flags" with TARGET_SUBTARGET32_DEFAULT for 32-bit
targets or with TARGET_SUBTARGET64_DEFAULT for 64-bit targets.
Mask "ix86_isa_flags" with TARGET_SUBTARGET32_ISA_DEFAULT for 32-bit
targets or with TARGET_SUBTARGET64_ISA_DEFAULT for 64-bit targets.
(def_builtin): Mask "mask" variable with "ix86_isa_flags", not
"target_flags".
(TARGET_DEFAULT_TARGET_FLAGS): Do not include TARGET_64BIT_DEFAULT.
2007-05-29 David Daney <ddaney@avtrex.com
PR gcc/31975
@ -119,7 +174,6 @@
* varpool.c (add_new_static_var): New function.
* cgraph.h (add_new_static_var): Declare.
2007-05-27 Eric Christopher <echristo@apple.com>
* config/rs6000/rs6000.c (rs6000_emit_prologue): Update
@ -136,7 +190,8 @@
* tree-ssa-threadupdate.c (thread_block): Ditto.
(thread_through_all_blocks): Ditto. Assert that loops were analysed.
* tree-ssa-loop-manip.c (rewrite_into_loop_closed_ssa,
verify_loop_closed_ssa): Check number_of_loops instead of current_loops.
verify_loop_closed_ssa): Check number_of_loops instead of
current_loops.
* predict.c (tree_estimate_probability): Ditto.
* tree-if-conv.c (main_tree_if_conversion): Ditto.
* tree-ssa-loop-ch.c (copy_loop_headers): Ditto.

2
gcc/config/i386/darwin.h
View File

@ -26,7 +26,7 @@ Boston, MA 02110-1301, USA. */
#define TARGET_VERSION fprintf (stderr, " (i686 Darwin)");
#undef TARGET_64BIT
#define TARGET_64BIT (target_flags & MASK_64BIT)
#define TARGET_64BIT OPTION_ISA_64BIT
#ifdef IN_LIBGCC2
#undef TARGET_64BIT

349
gcc/config/i386/i386.c
View File

@ -1227,8 +1227,8 @@ unsigned int ix86_tune_features[X86_TUNE_LAST] = {
/* Feature tests against the various architecture variations. */
unsigned int ix86_arch_features[X86_ARCH_LAST] = {
/* X86_ARCH_CMOVE */
m_PPRO | m_GEODE | m_ATHLON_K8_AMDFAM10 | m_PENT4 | m_NOCONA,
/* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
~(m_386 | m_486 | m_PENT | m_K6),
/* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
~m_386,
@ -1544,6 +1544,13 @@ static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
#define DEFAULT_PCC_STRUCT_RETURN 1
#endif
/* Bit flags that specify the ISA we are compiling for. */
int ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT;
/* A mask of ix86_isa_flags that includes bit X if X
was set or cleared on the command line. */
static int ix86_isa_flags_explicit;
/* Implement TARGET_HANDLE_OPTION. */
static bool
@ -1551,72 +1558,83 @@ ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
{
switch (code)
{
case OPT_m3dnow:
case OPT_mmmx:
ix86_isa_flags_explicit |= MASK_MMX;
if (!value)
{
target_flags &= ~MASK_3DNOW_A;
target_flags_explicit |= MASK_3DNOW_A;
ix86_isa_flags &= ~(MASK_3DNOW | MASK_3DNOW_A);
ix86_isa_flags_explicit |= MASK_3DNOW | MASK_3DNOW_A;
}
return true;
case OPT_mmmx:
case OPT_m3dnow:
ix86_isa_flags_explicit |= MASK_3DNOW;
if (!value)
{
target_flags &= ~(MASK_3DNOW | MASK_3DNOW_A);
target_flags_explicit |= MASK_3DNOW | MASK_3DNOW_A;
ix86_isa_flags &= ~MASK_3DNOW_A;
ix86_isa_flags_explicit |= MASK_3DNOW_A;
}
return true;
case OPT_m3dnowa:
return false;
case OPT_msse:
ix86_isa_flags_explicit |= MASK_SSE;
if (!value)
{
target_flags &= ~(MASK_SSE2 | MASK_SSE3 | MASK_SSSE3
| MASK_SSE4_1 | MASK_SSE4A);
target_flags_explicit |= (MASK_SSE2 | MASK_SSE3 | MASK_SSSE3
| MASK_SSE4_1 | MASK_SSE4A);
ix86_isa_flags &= ~(MASK_SSE2 | MASK_SSE3 | MASK_SSSE3
| MASK_SSE4_1 | MASK_SSE4A);
ix86_isa_flags_explicit |= (MASK_SSE2 | MASK_SSE3 | MASK_SSSE3
| MASK_SSE4_1 | MASK_SSE4A);
}
return true;
case OPT_msse2:
ix86_isa_flags_explicit |= MASK_SSE2;
if (!value)
{
target_flags &= ~(MASK_SSE3 | MASK_SSSE3 | MASK_SSE4_1
| MASK_SSE4A);
target_flags_explicit |= (MASK_SSE3 | MASK_SSSE3
| MASK_SSE4_1 | MASK_SSE4A);
ix86_isa_flags &= ~(MASK_SSE3 | MASK_SSSE3 | MASK_SSE4_1
| MASK_SSE4A);
ix86_isa_flags_explicit |= (MASK_SSE3 | MASK_SSSE3
| MASK_SSE4_1 | MASK_SSE4A);
}
return true;
case OPT_msse3:
ix86_isa_flags_explicit |= MASK_SSE3;
if (!value)
{
target_flags &= ~(MASK_SSSE3 | MASK_SSE4_1 | MASK_SSE4A);
target_flags_explicit |= (MASK_SSSE3 | MASK_SSE4_1
| MASK_SSE4A);
ix86_isa_flags &= ~(MASK_SSSE3 | MASK_SSE4_1 | MASK_SSE4A);
ix86_isa_flags_explicit |= (MASK_SSSE3 | MASK_SSE4_1
| MASK_SSE4A);
}
return true;
case OPT_mssse3:
ix86_isa_flags_explicit |= MASK_SSSE3;
if (!value)
{
target_flags &= ~(MASK_SSE4_1 | MASK_SSE4A);
target_flags_explicit |= MASK_SSE4_1 | MASK_SSE4A;
ix86_isa_flags &= ~(MASK_SSE4_1 | MASK_SSE4A);
ix86_isa_flags_explicit |= MASK_SSE4_1 | MASK_SSE4A;
}
return true;
case OPT_msse4_1:
ix86_isa_flags_explicit |= MASK_SSE4_1;
if (!value)
{
target_flags &= ~MASK_SSE4A;
target_flags_explicit |= MASK_SSE4A;
ix86_isa_flags &= ~MASK_SSE4A;
ix86_isa_flags_explicit |= MASK_SSE4A;
}
return true;
case OPT_msse4a:
ix86_isa_flags_explicit |= MASK_SSE4A;
if (!value)
{
target_flags &= ~MASK_SSE4_1;
target_flags_explicit |= MASK_SSE4_1;
ix86_isa_flags &= ~MASK_SSE4_1;
ix86_isa_flags_explicit |= MASK_SSE4_1;
}
return true;
@ -1647,8 +1665,6 @@ override_options (void)
static struct ptt
{
const struct processor_costs *cost; /* Processor costs */
const int target_enable; /* Target flags to enable. */
const int target_disable; /* Target flags to disable. */
const int align_loop; /* Default alignments. */
const int align_loop_max_skip;
const int align_jump;
@ -1657,20 +1673,20 @@ override_options (void)
}
const processor_target_table[PROCESSOR_max] =
{
{&i386_cost, 0, 0, 4, 3, 4, 3, 4},
{&i486_cost, 0, 0, 16, 15, 16, 15, 16},
{&pentium_cost, 0, 0, 16, 7, 16, 7, 16},
{&pentiumpro_cost, 0, 0, 16, 15, 16, 7, 16},
{&geode_cost, 0, 0, 0, 0, 0, 0, 0},
{&k6_cost, 0, 0, 32, 7, 32, 7, 32},
{&athlon_cost, 0, 0, 16, 7, 16, 7, 16},
{&pentium4_cost, 0, 0, 0, 0, 0, 0, 0},
{&k8_cost, 0, 0, 16, 7, 16, 7, 16},
{&nocona_cost, 0, 0, 0, 0, 0, 0, 0},
{&core2_cost, 0, 0, 16, 7, 16, 7, 16},
{&generic32_cost, 0, 0, 16, 7, 16, 7, 16},
{&generic64_cost, 0, 0, 16, 7, 16, 7, 16},
{&amdfam10_cost, 0, 0, 32, 24, 32, 7, 32}
{&i386_cost, 4, 3, 4, 3, 4},
{&i486_cost, 16, 15, 16, 15, 16},
{&pentium_cost, 16, 7, 16, 7, 16},
{&pentiumpro_cost, 16, 15, 16, 7, 16},
{&geode_cost, 0, 0, 0, 0, 0},
{&k6_cost, 32, 7, 32, 7, 32},
{&athlon_cost, 16, 7, 16, 7, 16},
{&pentium4_cost, 0, 0, 0, 0, 0},
{&k8_cost, 16, 7, 16, 7, 16},
{&nocona_cost, 0, 0, 0, 0, 0},
{&core2_cost, 16, 7, 16, 7, 16},
{&generic32_cost, 16, 7, 16, 7, 16},
{&generic64_cost, 16, 7, 16, 7, 16},
{&amdfam10_cost, 32, 24, 32, 7, 32}
};
static const char * const cpu_names[] = TARGET_CPU_DEFAULT_NAMES;
@ -1707,71 +1723,79 @@ override_options (void)
{"winchip-c6", PROCESSOR_I486, PTA_MMX},
{"winchip2", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
{"c3", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
{"c3-2", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_PREFETCH_SSE | PTA_SSE},
{"c3-2", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE},
{"i686", PROCESSOR_PENTIUMPRO, 0},
{"pentiumpro", PROCESSOR_PENTIUMPRO, 0},
{"pentium2", PROCESSOR_PENTIUMPRO, PTA_MMX},
{"pentium3", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE},
{"pentium3m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE},
{"pentium-m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE | PTA_SSE2},
{"pentium4", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2
| PTA_MMX | PTA_PREFETCH_SSE},
{"pentium4m", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2
| PTA_MMX | PTA_PREFETCH_SSE},
{"prescott", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_MMX | PTA_PREFETCH_SSE},
{"nocona", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_64BIT
| PTA_MMX | PTA_PREFETCH_SSE
| PTA_CX16 | PTA_NO_SAHF},
{"core2", PROCESSOR_CORE2, PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
| PTA_64BIT | PTA_MMX
| PTA_PREFETCH_SSE | PTA_CX16},
{"geode", PROCESSOR_GEODE, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
| PTA_3DNOW_A},
{"pentium3", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE},
{"pentium3m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE},
{"pentium-m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_SSE2},
{"pentium4", PROCESSOR_PENTIUM4, PTA_MMX |PTA_SSE | PTA_SSE2},
{"pentium4m", PROCESSOR_PENTIUM4, PTA_MMX | PTA_SSE | PTA_SSE2},
{"prescott", PROCESSOR_NOCONA, PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3},
{"nocona", PROCESSOR_NOCONA, (PTA_64BIT
| PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_CX16 | PTA_NO_SAHF)},
{"core2", PROCESSOR_CORE2, (PTA_64BIT
| PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSSE3
| PTA_CX16)},
{"geode", PROCESSOR_GEODE, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
|PTA_PREFETCH_SSE)},
{"k6", PROCESSOR_K6, PTA_MMX},
{"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
{"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
{"athlon", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
| PTA_3DNOW_A},
{"athlon-tbird", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE
| PTA_3DNOW | PTA_3DNOW_A},
{"athlon-4", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
| PTA_3DNOW_A | PTA_SSE},
{"athlon-xp", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
| PTA_3DNOW_A | PTA_SSE},
{"athlon-mp", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
| PTA_3DNOW_A | PTA_SSE},
{"x86-64", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_64BIT
| PTA_SSE | PTA_SSE2 | PTA_NO_SAHF},
{"k8", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
| PTA_3DNOW_A | PTA_SSE | PTA_SSE2
| PTA_NO_SAHF},
{"k8-sse3", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
| PTA_3DNOW_A | PTA_SSE | PTA_SSE2
| PTA_SSE3 | PTA_NO_SAHF},
{"opteron", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
| PTA_64BIT | PTA_3DNOW_A | PTA_SSE
| PTA_SSE2 | PTA_NO_SAHF},
{"opteron-sse3", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
| PTA_64BIT | PTA_3DNOW_A | PTA_SSE
| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
{"athlon64", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
| PTA_64BIT | PTA_3DNOW_A | PTA_SSE
| PTA_SSE2 | PTA_NO_SAHF},
{"athlon64-sse3", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
| PTA_64BIT | PTA_3DNOW_A | PTA_SSE
| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
{"athlon-fx", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
| PTA_64BIT | PTA_3DNOW_A | PTA_SSE
| PTA_SSE2 | PTA_NO_SAHF},
{"amdfam10", PROCESSOR_AMDFAM10, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
| PTA_64BIT | PTA_3DNOW_A | PTA_SSE
| PTA_SSE2 | PTA_SSE3 | PTA_POPCNT
| PTA_ABM | PTA_SSE4A | PTA_CX16},
{"barcelona", PROCESSOR_AMDFAM10, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
| PTA_64BIT | PTA_3DNOW_A | PTA_SSE
| PTA_SSE2 | PTA_SSE3 | PTA_POPCNT
| PTA_ABM | PTA_SSE4A | PTA_CX16},
{"athlon", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
| PTA_PREFETCH_SSE)},
{"athlon-tbird", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
| PTA_PREFETCH_SSE)},
{"athlon-4", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
| PTA_SSE)},
{"athlon-xp", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
| PTA_SSE)},
{"athlon-mp", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
| PTA_SSE)},
{"x86-64", PROCESSOR_K8, (PTA_64BIT
| PTA_MMX | PTA_SSE | PTA_SSE2
| PTA_NO_SAHF)},
{"k8", PROCESSOR_K8, (PTA_64BIT
| PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
| PTA_SSE | PTA_SSE2
| PTA_NO_SAHF)},
{"k8-sse3", PROCESSOR_K8, (PTA_64BIT
| PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
| PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_NO_SAHF)},
{"opteron", PROCESSOR_K8, (PTA_64BIT
| PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
| PTA_SSE | PTA_SSE2
| PTA_NO_SAHF)},
{"opteron-sse3", PROCESSOR_K8, (PTA_64BIT
| PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
| PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_NO_SAHF)},
{"athlon64", PROCESSOR_K8, (PTA_64BIT
| PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
| PTA_SSE | PTA_SSE2
| PTA_NO_SAHF)},
{"athlon64-sse3", PROCESSOR_K8, (PTA_64BIT
| PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
| PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_NO_SAHF)},
{"athlon-fx", PROCESSOR_K8, (PTA_64BIT
| PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
| PTA_SSE | PTA_SSE2
| PTA_NO_SAHF)},
{"amdfam10", PROCESSOR_AMDFAM10, (PTA_64BIT
| PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
| PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSE4A
| PTA_CX16 | PTA_ABM)},
{"barcelona", PROCESSOR_AMDFAM10, (PTA_64BIT
| PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
| PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSE4A
| PTA_CX16 | PTA_ABM)},
{"generic32", PROCESSOR_GENERIC32, 0 /* flags are only used for -march switch. */ },
{"generic64", PROCESSOR_GENERIC64, PTA_64BIT /* flags are only used for -march switch. */ },
};
@ -1925,9 +1949,9 @@ override_options (void)
if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
error ("code model %qs not supported in the %s bit mode",
ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
if ((TARGET_64BIT != 0) != ((target_flags & MASK_64BIT) != 0))
if ((TARGET_64BIT != 0) != ((ix86_isa_flags & MASK_64BIT) != 0))
sorry ("%i-bit mode not compiled in",
(target_flags & MASK_64BIT) ? 64 : 32);
(ix86_isa_flags & MASK_64BIT) ? 64 : 32);
for (i = 0; i < pta_size; i++)
if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
@ -1935,48 +1959,50 @@ override_options (void)
ix86_arch = processor_alias_table[i].processor;
/* Default cpu tuning to the architecture. */
ix86_tune = ix86_arch;
if (processor_alias_table[i].flags & PTA_MMX
&& !(target_flags_explicit & MASK_MMX))
target_flags |= MASK_MMX;
if (processor_alias_table[i].flags & PTA_3DNOW
&& !(target_flags_explicit & MASK_3DNOW))
target_flags |= MASK_3DNOW;
if (processor_alias_table[i].flags & PTA_3DNOW_A
&& !(target_flags_explicit & MASK_3DNOW_A))
target_flags |= MASK_3DNOW_A;
if (processor_alias_table[i].flags & PTA_SSE
&& !(target_flags_explicit & MASK_SSE))
target_flags |= MASK_SSE;
if (processor_alias_table[i].flags & PTA_SSE2
&& !(target_flags_explicit & MASK_SSE2))
target_flags |= MASK_SSE2;
if (processor_alias_table[i].flags & PTA_SSE3
&& !(target_flags_explicit & MASK_SSE3))
target_flags |= MASK_SSE3;
if (processor_alias_table[i].flags & PTA_SSSE3
&& !(target_flags_explicit & MASK_SSSE3))
target_flags |= MASK_SSSE3;
if (processor_alias_table[i].flags & PTA_SSE4_1
&& !(target_flags_explicit & MASK_SSE4_1))
target_flags |= MASK_SSE4_1;
if (processor_alias_table[i].flags & PTA_PREFETCH_SSE)
x86_prefetch_sse = true;
if (processor_alias_table[i].flags & PTA_CX16)
x86_cmpxchg16b = true;
if (processor_alias_table[i].flags & PTA_POPCNT
&& !(target_flags_explicit & MASK_POPCNT))
target_flags |= MASK_POPCNT;
if (processor_alias_table[i].flags & PTA_ABM
&& !(target_flags_explicit & MASK_ABM))
target_flags |= MASK_ABM;
if (processor_alias_table[i].flags & PTA_SSE4A
&& !(target_flags_explicit & MASK_SSE4A))
target_flags |= MASK_SSE4A;
if (!(TARGET_64BIT && (processor_alias_table[i].flags & PTA_NO_SAHF)))
x86_sahf = true;
if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
error ("CPU you selected does not support x86-64 "
"instruction set");
if (processor_alias_table[i].flags & PTA_MMX
&& !(ix86_isa_flags_explicit & MASK_MMX))
ix86_isa_flags |= MASK_MMX;
if (processor_alias_table[i].flags & PTA_3DNOW
&& !(ix86_isa_flags_explicit & MASK_3DNOW))
ix86_isa_flags |= MASK_3DNOW;
if (processor_alias_table[i].flags & PTA_3DNOW_A
&& !(ix86_isa_flags_explicit & MASK_3DNOW_A))
ix86_isa_flags |= MASK_3DNOW_A;
if (processor_alias_table[i].flags & PTA_SSE
&& !(ix86_isa_flags_explicit & MASK_SSE))
ix86_isa_flags |= MASK_SSE;
if (processor_alias_table[i].flags & PTA_SSE2
&& !(ix86_isa_flags_explicit & MASK_SSE2))
ix86_isa_flags |= MASK_SSE2;
if (processor_alias_table[i].flags & PTA_SSE3
&& !(ix86_isa_flags_explicit & MASK_SSE3))
ix86_isa_flags |= MASK_SSE3;
if (processor_alias_table[i].flags & PTA_SSSE3
&& !(ix86_isa_flags_explicit & MASK_SSSE3))
ix86_isa_flags |= MASK_SSSE3;
if (processor_alias_table[i].flags & PTA_SSE4_1
&& !(ix86_isa_flags_explicit & MASK_SSE4_1))
ix86_isa_flags |= MASK_SSE4_1;
if (processor_alias_table[i].flags & PTA_SSE4A
&& !(ix86_isa_flags_explicit & MASK_SSE4A))
ix86_isa_flags |= MASK_SSE4A;
if (processor_alias_table[i].flags & PTA_ABM)
x86_abm = true;
if (processor_alias_table[i].flags & PTA_CX16)
x86_cmpxchg16b = true;
if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM))
x86_popcnt = true;
if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
x86_prefetch_sse = true;
if ((processor_alias_table[i].flags & PTA_NO_SAHF) && !TARGET_64BIT)
x86_sahf = true;
break;
}
@ -2011,7 +2037,8 @@ override_options (void)
-mtune (rather than -march) points us to a processor that has them.
However, the VIA C3 gives a SIGILL, so we only do that for i686 and
higher processors. */
if (TARGET_CMOVE && (processor_alias_table[i].flags & PTA_PREFETCH_SSE))
if (TARGET_CMOVE
&& (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
x86_prefetch_sse = true;
break;
}
@ -2026,8 +2053,6 @@ override_options (void)
ix86_cost = &size_cost;
else
ix86_cost = processor_target_table[ix86_tune].cost;
target_flags |= processor_target_table[ix86_tune].target_enable;
target_flags &= ~processor_target_table[ix86_tune].target_disable;
/* Arrange to set up i386_stack_locals for all functions. */
init_machine_status = ix86_init_machine_status;
@ -2166,53 +2191,60 @@ override_options (void)
/* Turn on SSSE3 builtins for -msse4.1. */
if (TARGET_SSE4_1)
target_flags |= MASK_SSSE3;
ix86_isa_flags |= MASK_SSSE3;
/* Turn on SSE3 builtins for -mssse3. */
if (TARGET_SSSE3)
target_flags |= MASK_SSE3;
ix86_isa_flags |= MASK_SSE3;
/* Turn on SSE3 builtins for -msse4a. */
if (TARGET_SSE4A)
target_flags |= MASK_SSE3;
ix86_isa_flags |= MASK_SSE3;
/* Turn on SSE2 builtins for -msse3. */
if (TARGET_SSE3)
target_flags |= MASK_SSE2;
ix86_isa_flags |= MASK_SSE2;
/* Turn on SSE builtins for -msse2. */
if (TARGET_SSE2)
target_flags |= MASK_SSE;
ix86_isa_flags |= MASK_SSE;
/* Turn on MMX builtins for -msse. */
if (TARGET_SSE)
{
target_flags |= MASK_MMX & ~target_flags_explicit;
ix86_isa_flags |= MASK_MMX & ~ix86_isa_flags_explicit;
x86_prefetch_sse = true;
}
/* Turn on MMX builtins for 3Dnow. */
if (TARGET_3DNOW)
target_flags |= MASK_MMX;
ix86_isa_flags |= MASK_MMX;
/* Turn on POPCNT builtins for -mabm. */
if (TARGET_ABM)
target_flags |= MASK_POPCNT;
x86_popcnt = true;
if (TARGET_64BIT)
{
if (TARGET_RTD)
warning (0, "-mrtd is ignored in 64bit mode");
target_flags |= TARGET_SUBTARGET64_DEFAULT & ~target_flags_explicit;
/* Enable by default the SSE and MMX builtins. Do allow the user to
explicitly disable any of these. In particular, disabling SSE and
MMX for kernel code is extremely useful. */
target_flags
|= ((MASK_SSE2 | MASK_SSE | MASK_MMX | TARGET_SUBTARGET64_DEFAULT)
& ~target_flags_explicit);
ix86_isa_flags
|= ((MASK_SSE2 | MASK_SSE | MASK_MMX | TARGET_SUBTARGET64_ISA_DEFAULT)
& ~ix86_isa_flags_explicit);
if (TARGET_RTD)
warning (0, "-mrtd is ignored in 64bit mode");
}
else
{
target_flags |= TARGET_SUBTARGET32_DEFAULT & ~target_flags_explicit;
ix86_isa_flags
|= TARGET_SUBTARGET32_DEFAULT & ~ix86_isa_flags_explicit;
/* i386 ABI does not specify red zone. It still makes sense to use it
when programmer takes care to stack from being destroyed. */
if (!(target_flags_explicit & MASK_NO_RED_ZONE))
@ -16608,7 +16640,7 @@ def_builtin (int mask, const char *name, tree type, enum ix86_builtins code)
{
tree decl = NULL_TREE;
if (mask & target_flags
if (mask & ix86_isa_flags
&& (!(mask & MASK_64BIT) || TARGET_64BIT))
{
decl = add_builtin_function (name, type, code, BUILT_IN_MD,
@ -22702,7 +22734,6 @@ static const struct attribute_spec ix86_attribute_table[] =
#undef TARGET_DEFAULT_TARGET_FLAGS
#define TARGET_DEFAULT_TARGET_FLAGS \
(TARGET_DEFAULT \
| TARGET_64BIT_DEFAULT \
| TARGET_SUBTARGET_DEFAULT \
| TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)

45
gcc/config/i386/i386.h
View File

@ -35,6 +35,32 @@ Boston, MA 02110-1301, USA. */
ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
that start with ASM_ or end in ASM_OP. */
/* Redefines for option macros. */
#define TARGET_64BIT OPTION_ISA_64BIT
#define TARGET_MMX OPTION_ISA_MMX
#define TARGET_3DNOW OPTION_ISA_3DNOW
#define TARGET_3DNOW_A OPTION_ISA_3DNOW_A
#define TARGET_SSE OPTION_ISA_SSE
#define TARGET_SSE2 OPTION_ISA_SSE2
#define TARGET_SSE3 OPTION_ISA_SSE3
#define TARGET_SSSE3 OPTION_ISA_SSSE3
#define TARGET_SSE4_1 OPTION_ISA_SSE4_1
#define TARGET_SSE4A OPTION_ISA_SSE4A
/* ??? Remove following defines. */
#define MASK_64BIT OPTION_MASK_ISA_64BIT
#define MASK_MMX OPTION_MASK_ISA_MMX
#define MASK_3DNOW OPTION_MASK_ISA_3DNOW
#define MASK_3DNOW_A OPTION_MASK_ISA_3DNOW_A
#define MASK_SSE OPTION_MASK_ISA_SSE
#define MASK_SSE2 OPTION_MASK_ISA_SSE2
#define MASK_SSE3 OPTION_MASK_ISA_SSE3
#define MASK_SSSE3 OPTION_MASK_ISA_SSSE3
#define MASK_SSE4_1 OPTION_MASK_ISA_SSE4_1
#define MASK_SSE4A OPTION_MASK_ISA_SSE4A
#include "config/vxworks-dummy.h"
/* Algorithm to expand string function with. */
@ -342,13 +368,15 @@ extern unsigned int ix86_arch_features[X86_ARCH_LAST];
#define TARGET_XADD ix86_arch_features[X86_ARCH_XADD]
#define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP]
#define TARGET_CMPXCHG16B x86_cmpxchg16b
#define TARGET_SAHF x86_sahf
#define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
extern int x86_prefetch_sse;
#define TARGET_ABM x86_abm
#define TARGET_CMPXCHG16B x86_cmpxchg16b
#define TARGET_POPCNT x86_popcnt
#define TARGET_PREFETCH_SSE x86_prefetch_sse
#define TARGET_SAHF x86_sahf
#define ASSEMBLER_DIALECT (ix86_asm_dialect)
@ -361,6 +389,8 @@ extern int x86_prefetch_sse;
#define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS)
#define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN)
extern int ix86_isa_flags;
#ifndef TARGET_64BIT_DEFAULT
#define TARGET_64BIT_DEFAULT 0
#endif
@ -373,8 +403,17 @@ extern int x86_prefetch_sse;
the frame pointer in leaf functions. */
#define TARGET_DEFAULT 0
/* Extra bits to force. */
#define TARGET_SUBTARGET_DEFAULT 0
#define TARGET_SUBTARGET_ISA_DEFAULT 0
/* Extra bits to force on w/ 32-bit mode. */
#define TARGET_SUBTARGET32_DEFAULT 0
#define TARGET_SUBTARGET32_ISA_DEFAULT 0
/* Extra bits to force on w/ 64-bit mode. */
#define TARGET_SUBTARGET64_DEFAULT 0
#define TARGET_SUBTARGET64_ISA_DEFAULT 0
/* This is not really a target flag, but is done this way so that
it's analogous to similar code for Mach-O on PowerPC. darwin.h

125
gcc/config/i386/i386.opt
View File

@ -23,18 +23,6 @@ m128bit-long-double
Target RejectNegative Report Mask(128BIT_LONG_DOUBLE)
sizeof(long double) is 16
m32
Target RejectNegative Negative(m64) Report InverseMask(64BIT)
Generate 32bit i386 code
m3dnow
Target Report Mask(3DNOW)
Support 3DNow! built-in functions
m64
Target RejectNegative Negative(m32) Report Mask(64BIT)
Generate 64bit x86-64 code
m80387
Target Report Mask(80387)
Use hardware fp
@ -119,10 +107,6 @@ mintel-syntax
Target Undocumented
;; Deprecated
mmmx
Target Report Mask(MMX)
Support MMX built-in functions
mms-bitfields
Target Report Mask(MS_BITFIELD_LAYOUT)
Use native (MS) bitfield layout
@ -171,50 +155,6 @@ msoft-float
Target InverseMask(80387)
Do not use hardware fp
msse
Target Report Mask(SSE)
Support MMX and SSE built-in functions and code generation
msse2
Target Report Mask(SSE2)
Support MMX, SSE and SSE2 built-in functions and code generation
msse3
Target Report Mask(SSE3)
Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation
mssse3
Target Report Mask(SSSE3)
Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation
msse4.1
Target Report Mask(SSE4_1)
Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation
msse4a
Target Report Mask(SSE4A)
Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation
mpopcnt
Target Report Mask(POPCNT)
Support code generation of popcnt instruction for popcount built-ins
namely __builtin_popcount, __builtin_popcountl and __builtin_popcountll
mabm
Target Report Mask(ABM)
Support code generation of Advanced Bit Manipulation (ABM) instructions,
which include popcnt and lzcnt instructions, for popcount and clz built-ins
namely __builtin_popcount, __builtin_popcountl, __builtin_popcountll and
__builtin_clz, __builtin_clzl, __builtin_clzll
mcx16
Target Report RejectNegative Var(x86_cmpxchg16b)
Support code generation of cmpxchg16b instruction.
msahf
Target Report RejectNegative Var(x86_sahf)
Support code generation of sahf instruction in 64bit x86-64 code
msseregparm
Target RejectNegative Mask(SSEREGPARM)
Use SSE register passing conventions for SF and DF mode
@ -243,5 +183,66 @@ mtune=
Target RejectNegative Joined Var(ix86_tune_string)
Schedule code for given CPU
;; Support Athlon 3Dnow builtins
Mask(3DNOW_A)
;; ISA support
m32
Target RejectNegative Negative(m64) Report InverseMask(ISA_64BIT) Var(ix86_isa_flags) VarExists
Generate 32bit i386 code
m64
Target RejectNegative Negative(m32) Report Mask(ISA_64BIT) Var(ix86_isa_flags) VarExists
Generate 64bit x86-64 code
mmmx
Target Report Mask(ISA_MMX) Var(ix86_isa_flags) VarExists
Support MMX built-in functions
m3dnow
Target Report Mask(ISA_3DNOW) Var(ix86_isa_flags) VarExists
Support 3DNow! built-in functions
m3dnowa
Target Undocumented Mask(ISA_3DNOW_A) Var(ix86_isa_flags) VarExists
Support Athlon 3Dnow! built-in functions
msse
Target Report Mask(ISA_SSE) Var(ix86_isa_flags) VarExists
Support MMX and SSE built-in functions and code generation
msse2
Target Report Mask(ISA_SSE2) Var(ix86_isa_flags) VarExists
Support MMX, SSE and SSE2 built-in functions and code generation
msse3
Target Report Mask(ISA_SSE3) Var(ix86_isa_flags) VarExists
Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation
mssse3
Target Report Mask(ISA_SSSE3) Var(ix86_isa_flags) VarExists
Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation
msse4.1
Target Report Mask(ISA_SSE4_1) Var(ix86_isa_flags) VarExists
Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation
msse4a
Target Report Mask(ISA_SSE4A) Var(ix86_isa_flags) VarExists
Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation
;; Instruction support
mabm
Target Report RejectNegative Var(x86_abm)
Support code generation of Advanced Bit Manipulation (ABM) instructions.
mcx16
Target Report RejectNegative Var(x86_cmpxchg16b)
Support code generation of cmpxchg16b instruction.
mpopcnt
Target Report RejectNegative Var(x86_popcnt)
Support code generation of popcnt instruction.
msahf
Target Report RejectNegative Var(x86_sahf)
Support code generation of sahf instruction in 64bit x86-64 code.

1
gcc/config/i386/unix.h
View File

@ -61,6 +61,7 @@ Boston, MA 02110-1301, USA. */
/* By default, target has a 80387, uses IEEE compatible arithmetic,
and returns float values in the 387. */
#undef TARGET_SUBTARGET_DEFAULT
#define TARGET_SUBTARGET_DEFAULT \
(MASK_80387 | MASK_IEEE_FP | MASK_FLOAT_RETURNS)