i386.c (x86_double_with_add): Turn off for Pentium and PPro.
* i386.c (x86_double_with_add): Turn off for Pentium and PPro. (small_shift_operand, output_ashlsi3): New functions. * i386.h (small_shift_operand, output_ashlsi3): Declare. * i386.md (ashlsi3): Simplify ahlsi3 patterns. Remove splitters that are no longer needed. From-SVN: r26189
This commit is contained in:
Jeffrey A Law
Jeff Law
parent
b5d9b9ab00
commit
0a726ef13b
@ -1,12 +1,16 @@
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Mon Apr 5 04:47:14 1999 Jeffrey A Law (law@cygnus.com)
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* i386.c (x86_double_with_add): Turn off for Pentium and PPro.
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(small_shift_operand, output_ashlsi3): New functions.
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* i386.h (small_shift_operand, output_ashlsi3): Declare.
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* i386.md (ashlsi3): Simplify ahlsi3 patterns. Remove splitters
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that are no longer needed.
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Sun Apr 4 04:05:04 1999 Jeffrey A Law (law@cygnus.com)
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* stmt.c (expand_loop_end): When copying the loop exit test,
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do not walk into a nested loop.
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Sun Apr 4 01:15:04 PST 1999 Jeff Law (law@cygnus.com)
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* version.c: Bump for snapshot.
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Sun Apr 4 00:14:54 1999 Jeffrey A Law (law@cygnus.com)
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* fixinc/hackshell.tpl: Skip links to directories, to avoid
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@ -123,7 +123,7 @@ const int x86_use_leave = m_386 | m_K6;
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const int x86_push_memory = m_386 | m_K6;
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const int x86_zero_extend_with_and = m_486 | m_PENT;
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const int x86_movx = m_386 | m_PPRO | m_K6;
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const int x86_double_with_add = ~m_386;
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const int x86_double_with_add = ~(m_386 | m_PENT | m_PPRO);
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const int x86_use_bit_test = m_386;
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const int x86_unroll_strlen = m_486 | m_PENT | m_PPRO;
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const int x86_use_q_reg = m_PENT | m_PPRO | m_K6;
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@ -1687,6 +1687,17 @@ symbolic_operand (op, mode)
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}
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}
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/* Return nonzero if OP is a constant shift count small enough to
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encode into an lea instruction. */
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int
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small_shift_operand (op, mode)
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rtx op;
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enum machine_mode mode ATTRIBUTE_UNUSED;
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{
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return (GET_CODE (op) == CONST_INT && INTVAL (op) > 0 && INTVAL (op) < 4);
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}
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/* Test for a valid operand for a call instruction.
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Don't allow the arg pointer register or virtual regs
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since they may change into reg + const, which the patterns
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@ -5595,3 +5606,89 @@ x86_adjust_cost (insn, link, dep_insn, cost)
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return cost;
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}
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/* Output assembly code for a left shift.
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Always use "sal" when shifting a memory operand or for a non constant
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shift count.
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When optimizing for size, we know that src == dest, and we should always
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use "sal". If src != dest, then copy src to dest and use "sal".
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Pentium and PPro (speed):
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When src == dest, use "add" for a shift counts of one, else use
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"sal". If we modeled Pentium AGI stalls and U/V pipelining better we
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would want to generate lea for some shifts on the Pentium.
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When src != dest, use "lea" for small shift counts. Otherwise,
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copy src to dest and use the normal shifting code. Exception for
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TARGET_DOUBLE_WITH_ADD. */
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char *
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output_ashlsi3 (operands)
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rtx *operands;
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{
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/* Handle case where srcreg != dstreg. */
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if (REG_P (operands[0]) && REGNO (operands[0]) != REGNO (operands[1]))
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{
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if (TARGET_DOUBLE_WITH_ADD && INTVAL (operands[2]) == 1)
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{
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output_asm_insn (AS2 (mov%L0,%1,%0), operands);
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return AS2 (add%L0,%1,%0);
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}
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else
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{
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CC_STATUS_INIT;
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/* This should be extremely rare (impossible?). We can not encode a
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shift of the stack pointer using an lea instruction. So copy the
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stack pointer into the destination register and use an lea. */
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if (operands[1] == stack_pointer_rtx)
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{
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output_asm_insn (AS2 (mov%L0,%1,%0), operands);
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operands[1] = operands[0];
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}
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/* For shifts up to and including 3 bits, use lea. */
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operands[1] = gen_rtx_MULT (SImode, operands[1],
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GEN_INT (1 << INTVAL (operands[2])));
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return AS2 (lea%L0,%a1,%0);
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}
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}
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/* Source and destination match. */
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/* Handle variable shift. */
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if (REG_P (operands[2]))
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return AS2 (sal%L0,%b2,%0);
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/* Always perform shift by 1 using an add instruction. */
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if (REG_P (operands[0]) && operands[2] == const1_rtx)
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return AS2 (add%L0,%0,%0);
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#if 0
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/* ??? Currently disabled. reg-stack currently stomps on the mode of
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each insn. Thus, we can not easily detect when we should use lea to
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improve issue characteristics. Until reg-stack is fixed, fall back to
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sal instruction for Pentiums to avoid AGI stall. */
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/* Shift reg by 2 or 3 use an lea instruction for Pentium if this is
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insn is expected to issue into the V pipe (the insn's mode will be
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TImode for a U pipe, and !TImode for a V pipe instruction). */
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if (! optimize_size
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&& REG_P (operands[0])
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&& GET_CODE (operands[2]) == CONST_INT
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&& INTVAL (operands[2]) <= 3
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&& (int)ix86_cpu == (int)PROCESSOR_PENTIUM
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&& GET_MODE (insn) != TImode)
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{
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CC_STATUS_INIT;
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operands[1] = gen_rtx_MULT (SImode, operands[1],
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GEN_INT (1 << INTVAL (operands[2])));
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return AS2 (lea%L0,%a1,%0);
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}
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#endif
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/* Otherwise use a shift instruction. */
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return AS2 (sal%L0,%2,%0);
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}
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@ -2765,6 +2765,8 @@ extern int reg_mentioned_in_mem ();
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extern char *output_int_conditional_move ();
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extern char *output_fp_conditional_move ();
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extern int ix86_can_use_return_insn_p ();
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extern int small_shift_operand ();
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extern char *output_ashlsi3 ();
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#ifdef NOTYET
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extern struct rtx_def *copy_all_rtx ();
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@ -4753,205 +4753,27 @@ byte_xor_operation:
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""
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"")
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;; Optimizing for code size:
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;; For regsiter destinations:
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;; add == 2 bytes, move == 2 bytes, shift == 3 bytes, lea == 7 bytes
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;; Pattern for shifts which can be encoded into an lea instruction.
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;; This is kept as a separate pattern so that regmove can optimize cases
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;; where we know the source and destination must match.
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;;
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;; lea loses when optimizing for size
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;;
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;; Do the math. If the count is 1, using add, else using sal will
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;; produce the smallest possible code, even when the source and
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;; dest do not match. For a memory destination, sal is the only
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;; choice.
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;;
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;; Do not try to handle case where src and dest do not match. Let regmove
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;; and reload handle them. A mov followed by this insn will generate the
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;; desired size optimized results.
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;; Do not expose this pattern when optimizing for size since we never want
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;; to use lea when optimizing for size since mov+sal is smaller than lea.
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(define_insn ""
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[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r")
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(ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,r")
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(match_operand:SI 2 "small_shift_operand" "M,M")))]
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"! optimize_size"
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"* return output_ashlsi3 (operands);")
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;; Generic left shift pattern to catch all cases not handled by the
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;; shift pattern above.
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(define_insn ""
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[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
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(ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
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(match_operand:SI 2 "nonmemory_operand" "cI")))]
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"optimize_size"
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"*
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{
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if (REG_P (operands[0]) && operands[2] == const1_rtx)
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return AS2 (add%L0,%0,%0);
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if (REG_P (operands[2]))
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return AS2 (sal%L0,%b2,%0);
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return AS2 (sal%L0,%2,%0);
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}")
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;; For Pentium/Pentium MMX:
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;;
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;; We want to optimize for pairability, but avoid generating AGI stalls.
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;;
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;; If this insn is expected to issue in the U pipe, then prefer sal,
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;; else prefer lea for small shifts when srcreg == dstreg.
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;;
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;; For PPro/PII
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;;
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;; There's more than one approach to optimizing for this family; it is
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;; unclear which approach is best. For now, we will try to minimize
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;; uops. Note that sal and lea have the same characteristics, so we
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;; prefer sal as it takes less space.
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;;
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;; We can actually share code for these two cases since the basic techniques
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;; for generating good code on these chips is the same, even if the final
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;; code sequences are different.
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;;
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;; I do not know what is most appropriate for the AMD or Cyrix chips.
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;;
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;; srcreg == dstreg, constant shift count:
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;;
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;; For a shift count of one, use "add".
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;; For a shift count of two or three, use "sal"/"lea" for Pentium and
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;; Pentium MMX depending on which pipe the insn will execute.
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;; All others use "sar".
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;;
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;; srcreg != dstreg, constant shift count:
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;;
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;; For shift counts of one to three, use "lea".
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;; All others use "lea" for the first shift into the destination reg,
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;; then fall back on the srcreg == dstreg for the residual shifts.
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;;
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;; memory destinations or nonconstant shift count:
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;;
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;; Use "sal".
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;;
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(define_insn ""
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[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
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(ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,r")
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(match_operand:SI 2 "nonmemory_operand" "cI,I")))]
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"! optimize_size
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&& ((int)ix86_cpu == (int)PROCESSOR_PENTIUM
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|| (int)ix86_cpu == (int)PROCESSOR_PENTIUMPRO)"
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"*
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{
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/* This should be extremely rare (impossible?). We can not encode a shift
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of the stack pointer using an lea instruction. So copy the stack pointer
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into the destination register and fall into the srcreg == dstreg shifting
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support. */
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if (operands[1] == stack_pointer_rtx)
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{
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output_asm_insn (AS2 (mov%L0,%1,%0), operands);
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operands[1] = operands[0];
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}
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/* Handle case where srcreg != dstreg. */
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if (REG_P (operands[0]) && REGNO (operands[0]) != REGNO (operands[1]))
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{
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/* For counts > 3, it is easiest to split into component insns. */
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if (INTVAL (operands[2]) > 3)
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return \"#\";
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/* For shifts up to and including 3 bits, use lea. */
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operands[1] = gen_rtx_MULT (SImode, operands[1],
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GEN_INT (1 << INTVAL (operands[2])));
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return AS2 (lea%L0,%a1,%0);
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}
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/* Source and destination match. */
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/* Handle variable shift. */
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if (REG_P (operands[2]))
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return AS2 (sal%L0,%b2,%0);
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/* Always perform shift by 1 using an add instruction. */
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if (REG_P (operands[0]) && operands[2] == const1_rtx)
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return AS2 (add%L0,%0,%0);
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#if 0
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/* ??? Currently disabled. reg-stack currently stomps on the mode of
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each insn. Thus, we can not easily detect when we should use lea to
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improve issue characteristics. Until reg-stack is fixed, fall back to
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sal instruction for Pentiums to avoid AGI stall. */
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/* Shift reg by 2 or 3 use an lea instruction for Pentium if this is
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insn is expected to issue into the V pipe (the insn's mode will be
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TImode for a U pipe, and !TImode for a V pipe instruction). */
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if (REG_P (operands[0])
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&& GET_CODE (operands[2]) == CONST_INT
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&& INTVAL (operands[2]) <= 3
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&& (int)ix86_cpu == (int)PROCESSOR_PENTIUM
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&& GET_MODE (insn) != TImode)
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{
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operands[1] = gen_rtx_MULT (SImode, operands[1],
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GEN_INT (1 << INTVAL (operands[2])));
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return AS2 (lea%L0,%a1,%0);
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}
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#endif
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/* Otherwise use a shift instruction. */
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return AS2 (sal%L0,%2,%0);
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}")
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;; Pentium/PPro/PII Splitter used when srcreg != destreg and shift
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;; count is > 3. In each case we use lea to perform the first three
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;; shifts into the destination register, then we fall back to the
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;; normal shifting code for the residual shifts.
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(define_split
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[(set (match_operand:SI 0 "register_operand" "=r")
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(ashift:SI (match_operand:SI 1 "register_operand" "r")
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(match_operand:SI 2 "immediate_operand" "I")))]
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"reload_completed
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&& ! optimize_size
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&& ((int)ix86_cpu == (int)PROCESSOR_PENTIUM
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|| (int)ix86_cpu == (int)PROCESSOR_PENTIUMPRO)
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&& GET_CODE (operands[2]) == CONST_INT
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&& INTVAL (operands[2]) > 3
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&& true_regnum (operands[0]) != true_regnum (operands[1])"
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[(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
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(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 3)))]
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"
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{
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operands[3] = GEN_INT (INTVAL (operands[2]) - 3);
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operands[2] = GEN_INT (3);
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}")
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;; On i386 and i486, "addl reg,reg" is faster than "sall $1,reg"
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;; On i486, movl/sall appears slightly faster than leal, but the leal
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;; is smaller - use leal for now unless the shift count is 1.
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;;
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(define_insn ""
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[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
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(ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,r")
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(match_operand:SI 2 "nonmemory_operand" "cI,M")))]
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"! optimize_size
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&& ! ((int)ix86_cpu == (int)PROCESSOR_PENTIUM
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|| (int)ix86_cpu == (int)PROCESSOR_PENTIUMPRO)"
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"*
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{
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if (REG_P (operands[0]) && REGNO (operands[0]) != REGNO (operands[1]))
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{
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if (TARGET_DOUBLE_WITH_ADD && INTVAL (operands[2]) == 1)
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{
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output_asm_insn (AS2 (mov%L0,%1,%0), operands);
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return AS2 (add%L0,%1,%0);
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}
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else
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{
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CC_STATUS_INIT;
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if (operands[1] == stack_pointer_rtx)
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{
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output_asm_insn (AS2 (mov%L0,%1,%0), operands);
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operands[1] = operands[0];
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}
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operands[1] = gen_rtx_MULT (SImode, operands[1],
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GEN_INT (1 << INTVAL (operands[2])));
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return AS2 (lea%L0,%a1,%0);
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}
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}
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if (REG_P (operands[2]))
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return AS2 (sal%L0,%b2,%0);
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if (REG_P (operands[0]) && operands[2] == const1_rtx)
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return AS2 (add%L0,%0,%0);
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return AS2 (sal%L0,%2,%0);
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}")
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""
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"* return output_ashlsi3 (operands);")
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(define_insn "ashlhi3"
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[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
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